JPH10200403A - Frequency synthesizer - Google Patents
Frequency synthesizerInfo
- Publication number
- JPH10200403A JPH10200403A JP9000346A JP34697A JPH10200403A JP H10200403 A JPH10200403 A JP H10200403A JP 9000346 A JP9000346 A JP 9000346A JP 34697 A JP34697 A JP 34697A JP H10200403 A JPH10200403 A JP H10200403A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- signal
- vco
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明はネットワークアナ
ライザ、スペクトラムアナライザ、その他比較的広帯域
にわたり出力信号周波数を可変させることができる周波
数合成器（シンセサイザ）に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a network analyzer, a spectrum analyzer, and a frequency synthesizer capable of varying an output signal frequency over a relatively wide band.
【０００２】[0002]
【従来の技術】図２に従来の周波数合成器を示す。可変
周波数発振器、いわゆる可変電圧制御発振器（以下ＶＣ
Ｏと記す）１１の発振出力信号は可変分周器１２で周波
数がＮ分の１に分周され、その分周出力信号は位相比較
器１３で、水晶発振器のような安定度の優れた基準発振
器１４から基準周波数信号と位相比較され、その比較出
力はループフィルタ１５で平滑され、フィルタ１５の出
力でＶＣＯ１１の発振周波数が制御され、可変分周器１
２の出力信号の周波数が基準発振器１４の基準周波数信
号の周波数と一致するようになる。ＶＣＯ１１、分周器
１２、位相比較器１３、ループフィルタ１５により位相
周期ループ（ＰＬＬ）が構成されている。2. Description of the Related Art FIG. 2 shows a conventional frequency synthesizer. Variable frequency oscillator, so-called variable voltage controlled oscillator (hereinafter VC)
The oscillation output signal 11 is divided by a variable frequency divider 12 into a frequency of 1 / N, and the frequency-divided output signal is outputted from a phase comparator 13 to a reference having excellent stability such as a crystal oscillator. The phase is compared with the reference frequency signal from the oscillator 14, the comparison output is smoothed by the loop filter 15, the oscillation frequency of the VCO 11 is controlled by the output of the filter 15, and the variable frequency divider 1
2 becomes equal to the frequency of the reference frequency signal of the reference oscillator 14. The VCO 11, the frequency divider 12, the phase comparator 13, and the loop filter 15 form a phase period loop (PLL).
【０００３】一方、可変周波数発振器（ＶＣＯ）１７の
出力が分周器１８で周波数がＭ分の１に分周され、この
分周出力信号は水晶発振器のような基準発振器１９から
基準周波数信号と位相比較器２１で位相比較され、その
位相比較出力はループフィルタ２２を通じてＶＣＯ１７
へ制御信号として供給され、分周器１８の出力信号周波
数が基準発振器１９の発振信号周波数と等しくなる。Ｖ
ＣＯ１７、分周器１８、位相比較器２１、ループフィル
タ２２はＰＬＬを構成している。ＶＣＯ１１の出力信号
はＶＣＯ１７の出力信号で周波数変換器２３により周波
数変換されて出力端子２４へ供給される。On the other hand, the output of a variable frequency oscillator (VCO) 17 is frequency-divided by a frequency divider 18 into 1 / M. This frequency-divided output signal is output from a reference oscillator 19 such as a crystal oscillator to a reference frequency signal. The phase is compared by the phase comparator 21, and the phase comparison output is passed through the loop filter 22 to the VCO 17.
The frequency of the output signal of the frequency divider 18 becomes equal to the frequency of the oscillation signal of the reference oscillator 19. V
The CO 17, the frequency divider 18, the phase comparator 21, and the loop filter 22 constitute a PLL. The output signal of the VCO 11 is frequency-converted by the frequency converter 23 with the output signal of the VCO 17 and supplied to the output terminal 24.
【０００４】ＶＣＯ１７の発振周波数ｆf は例えば２０
０ＭＨｚに保持され、ＶＣＯ１１の発振周波数をｆV 、
基準発振器１４の発振周波数をｆr とすると、ｆV ＝Ｎ
ｆrとなり、可変分周器１２の分周比１／Ｎを変更する
ことにより、例えば２００．１ＭＨｚ〜３００ＭＨｚの
範囲でＶＣＯ１１の発振周波数ｆV を変化させることに
より、出力端子２４に１００ｋＨｚ〜１００ＭＨｚの範
囲で変化する出力信号を得ることができる。端子２４の
出力信号の周波数ｆ0 を１００ｋＨｚとするにはＮ＝２
００．１とし、つまりｆV ＝２００．１ＭＨｚとし、ｆ
0 を１００ＭＨｚとするには、Ｎ＝３００、つまりｆV
＝３００ＭＨｚとする。[0004] The oscillation frequency f f of VCO17 is, for example, 20
0 MHz, and the oscillation frequency of the VCO 11 is f V ,
Assuming that the oscillation frequency of the reference oscillator 14 is f r , f V = N
f r , and by changing the frequency division ratio 1 / N of the variable frequency divider 12, for example, by changing the oscillation frequency f V of the VCO 11 in the range of 200.1 MHz to 300 MHz, 100 kHz to 100 MHz is applied to the output terminal 24. Can be obtained. To set the frequency f 0 of the output signal of the terminal 24 to 100 kHz, N = 2
00.1, that is, f V = 200.1 MHz, f
To set 0 to 100 MHz, N = 300, that is, f V
= 300 MHz.
【０００５】[0005]
【発明が解決しようとする課題】出力端子２４に得られ
る信号の信号対雑音比は２０ logＮの割合で劣化する。
つまり分周数Ｎが大きい程、信号対雑音比が劣化する。
従来の周波数合成器では前記例のように、出力周波数ｆ
0 が３００ＭＨｚでＮ＝３００と分周数Ｎが可成り大き
な値となり、信号対雑音比が悪かった。The signal to noise ratio of the signal obtained at the output terminal 24 degrades at a rate of 20 logN.
In other words, as the frequency division number N increases, the signal-to-noise ratio deteriorates.
In the conventional frequency synthesizer, the output frequency f
When 0 is 300 MHz, N = 300 and the frequency division number N is a considerably large value, and the signal-to-noise ratio is poor.
【０００６】また、ＶＣＯ１１の発振周波数ｆV が出力
したい信号周波数ｆ0 の最高周波数より、前記例では２
〜３倍も高く、同様にＶＣＯ１７の発振周波数も、ｆ0
の最高周波数の２倍も高いものであった。このように所
望信号周波数ｆ0 より高い周波数の信号を処理する必要
があり、回路や素子間を互いに隔離（アイソレーショ
ン）するためシールドを十分に行う必要があり、規模が
大きくなり、かつ増幅器や回路素子なども高価なものと
なるなどの問題があった。In the above example, the oscillation frequency f V of the VCO 11 is 2 higher than the highest frequency of the signal frequency f 0 to be output.
Up to three times higher, and the oscillation frequency of the VCO 17 is also f 0
Was twice as high as the highest frequency. As described above, it is necessary to process a signal having a frequency higher than the desired signal frequency f 0, it is necessary to perform sufficient shielding to isolate circuits and elements from each other, and the scale becomes large. There has been a problem that circuit elements and the like also become expensive.
【０００７】[0007]
【課題を解決するための手段】この発明によれば、ＶＣ
Ｏの出力信号を可変分周器で周波数分周した出力信号が
直接デジタルシンセサイザ（以下ＤＤＳと記す）の出力
信号で低い周波数に周波数変換器により変換され、その
周波数変換された信号と基準周波数信号が位相比較さ
れ、その位相比較出力によりＶＣＯが制御される。また
このＶＣＯの出力信号とＤＤＳの出力信号とが切替えス
イッチにより切替えられて周波数合成器の出力端子へ供
給される。According to the present invention, a VC is provided.
An output signal obtained by frequency-dividing the output signal of O by a variable frequency divider is directly converted into a lower frequency by an output signal of a digital synthesizer (hereinafter referred to as DDS) by a frequency converter, and the frequency-converted signal and a reference frequency signal are output. Are compared, and the VCO is controlled by the phase comparison output. The output signal of the VCO and the output signal of the DDS are switched by a switch and supplied to the output terminal of the frequency synthesizer.
【０００８】[0008]
【発明の実施の形態】図１にこの発明の実施例を示し、
図２と対応する部分に同一符号を付けてある。この発明
ではＶＣＯ３１は周波数合成器の出力端子２４へ供給す
る信号の周波数ｆ0 の帯域を発振周波数とするものであ
り、また直接デジタルシンセサイザ（ＤＤＳ）３２が設
けられ、このＤＤＳの出力信号により可変分周器１２の
分周出力が周波数変換器３３で低い周波数に変換され、
この周波数変換器３３の出力信号が位相比較器１３で基
準発振器１４の基準周波数信号と位相比較され、この位
相比較出力がループフィルタ１５を通じてＶＣＯ３１に
制御信号として供給される。ＶＣＯ３１の出力信号とＤ
ＤＳ３２の出力信号とが切替えスイッチ３４で切替えら
れて出力端子２４へ供給される。ＤＤＳ３２は簡単に述
べると、発生したい周波数を設定すると、これと対応し
た数値を累積加算し、その加算値をアドレスとして、正
弦波形が記憶されたメモリを読出し、その読出された値
がアナログ信号に変換して出力するものであり、著しく
低い周波数から可成り高い周波数の安定な周波数信号を
出力する。可変分周器１２、周波数変換器３３、位相比
較器１３、ループフィルタ１５、ＶＣＯ３１でＰＬＬが
構成される。FIG. 1 shows an embodiment of the present invention.
Parts corresponding to those in FIG. 2 are denoted by the same reference numerals. In the present invention, the VCO 31 uses the band of the frequency f 0 of the signal supplied to the output terminal 24 of the frequency synthesizer as the oscillation frequency, and is directly provided with a digital synthesizer (DDS) 32, which can be changed by the output signal of the DDS The frequency divided output of the frequency divider 12 is converted to a lower frequency by the frequency converter 33,
The output signal of the frequency converter 33 is compared in phase with the reference frequency signal of the reference oscillator 14 by the phase comparator 13, and this phase comparison output is supplied to the VCO 31 through the loop filter 15 as a control signal. Output signal of VCO 31 and D
The output signal of the DS 32 is switched by the switch 34 and supplied to the output terminal 24. In brief, the DDS 32 sets a frequency to be generated, accumulatively adds a numerical value corresponding to the frequency, reads a memory storing a sine waveform using the added value as an address, and converts the read value into an analog signal. It converts and outputs a stable frequency signal from a remarkably low frequency to a considerably high frequency. The variable frequency divider 12, the frequency converter 33, the phase comparator 13, the loop filter 15, and the VCO 31 constitute a PLL.
【０００９】ＶＣＯ３１の発振周波数ｆV 、可変分周器
１２の分周数Ｎ、基準発振器１４の基準周波数ｆr 、Ｄ
ＤＳ３２の出力信号周波数ｆD との関係は （ｆD ＋ｆr ）×Ｎ＝ｆV となる。予め決めた周波数ｆVL以下の周波数信号を出力
する場合は、スイッチ３４をＤＤＳ３２側に接続して、
ＤＤＳ３２の出力信号を出力端子２４へ出力し、ｆVL以
上の周波数の信号を出力する場合は、スイッチ３４をＶ
ＣＯ３１側に接続してＶＣＯ３１の出力信号を出力端子
２４へ出力する。前記例と同様に例えば、１００ｋＨｚ
〜１００ＭＨｚの範囲の周波数信号を出力したい場合
で、基準周波数ｆr を１ＭＨｚとすると、３０〜１００
ＭＨｚ帯はＶＣＯ３１から出力させたものを用い、例え
ば３１ＭＨｚの周波数信号を出力させるにはＮ＝１、ｆ
D ＝３０ＭＨｚとすれば、ｆV ＝３１ＭＨｚとなり、こ
の周波数信号を出力端子２４へ出力し、１００ＭＨｚを
出力したい場合はＮ＝４、ｆD ＝２４ＭＨｚとすればｆ
V ＝１００ＭＨｚとなり、ＶＣＯ３１の出力信号を出力
端子２４へ出力する。１００ｋＨｚ〜３０ＭＨｚの周波
数信号を出力する場合は発振したい周波数をＤＤＳ３２
に設定し、スイッチ３４をＤＤＳ３２側に接続すればよ
い。なお、ＶＣＯ３１から出力端子２４へ出力する周波
数と、ＤＤＳ３２から出力端子２４へ出力する周波数と
が一部重なってもよい。The oscillation frequency f of the VCO 31V, Variable frequency divider
12, the division number N, the reference frequency f of the reference oscillator 14r, D
Output signal frequency f of DS32DIs related to (fD+ Fr) × N = fV Becomes Predetermined frequency fVLOutputs the following frequency signals
If so, connect the switch 34 to the DDS 32 side,
The output signal of the DDS 32 is output to the output terminal 24, and fVLLess than
To output a signal of the above frequency, set the switch 34 to V
Connect to the CO31 side to output the output signal of VCO31
24. For example, as in the above example, for example, 100 kHz
When you want to output a frequency signal in the range of ~ 100MHz
And the reference frequency frIs 1 MHz, 30 to 100
For the MHz band, use the one output from the VCO 31.
For example, to output a frequency signal of 31 MHz, N = 1, f
D= 30 MHz, then fV= 31 MHz,
Output to the output terminal 24 and output 100 MHz
If you want to output, N = 4, fD= 24 MHz, f
V= 100MHz and output the output signal of VCO31
Output to terminal 24. 100kHz-30MHz frequency
When outputting several signals, set the frequency to oscillate to DDS32
And switch 34 connected to DDS 32 side.
No. The frequency output from the VCO 31 to the output terminal 24
And the frequency output from the DDS 32 to the output terminal 24.
May partially overlap.
【００１０】[0010]
【発明の効果】以上述べたように、この発明によれば例
えば前記例の場合は、可変分周器１２の分周数Ｎは最大
で４であり、従来は最大で３００であり、Ｎが著しく小
さくて済み、それだけ信号対雑音比がよいものとなる。
また最高発振周波数は、出力信号の周波数帯の最高値と
一致し、従来は３倍も高い周波数の信号を処理しなけれ
ばならない場合と比較して、各回路、素子間の分離、そ
のためのシールドが頗る簡単になり、規模が小さくて済
み、増幅器、回路素子なども安価なものでよい。As described above, according to the present invention, for example, in the case of the above example, the frequency dividing number N of the variable frequency divider 12 is at most 4 and conventionally 300 at most, and N is conventional. Significantly smaller, resulting in a better signal-to-noise ratio.
In addition, the highest oscillation frequency matches the highest value of the frequency band of the output signal. Compared with the case where a signal of three times higher frequency has to be processed conventionally, the separation between each circuit and element and the shielding for that However, it is very simple, the scale is small, and the amplifiers and circuit elements can be inexpensive.
【図１】この発明の実施例を示すブロック図。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】従来の周波数合成器を示すブロック図。FIG. 2 is a block diagram showing a conventional frequency synthesizer.
Claims (1)
分周器と、 デジタル処理により各種の設定周波数の信号を発生する
直接デジタルシンセサイザと、 上記可変分周器の分周出力信号を上記直接デジタルシン
セサイザの出力信号で周波数変換する周波数変換器と、 基準周波数信号を発生する基準発振器と、 その基準発振器よりの基準周波数信号と上記周波数変換
器の出力信号との位相を比較する位相比較器と、 その位相比較器の出力を平滑し、その平滑出力で上記可
変周波数発振器の発振周波数を制御するループフィルタ
と、 上記可変周波数発振器の出力信号と、上記直接デジタル
シンセサイザの出力信号とを切替えて出力する切替えス
イッチと、 を具備する周波数合成器。1. A variable frequency oscillator, a variable frequency divider for frequency-dividing the oscillation output of the variable frequency oscillator, a direct digital synthesizer for generating signals of various set frequencies by digital processing, and the variable frequency divider A frequency converter that frequency-converts the frequency-divided output signal with the output signal of the direct digital synthesizer, a reference oscillator that generates a reference frequency signal, and a reference frequency signal from the reference oscillator and an output signal of the frequency converter. A phase comparator for comparing phases, a loop filter for smoothing the output of the phase comparator and controlling the oscillation frequency of the variable frequency oscillator with the smoothed output, an output signal of the variable frequency oscillator, and the direct digital synthesizer A changeover switch for switching between the output signal and the output signal of the frequency synthesizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9000346A JPH10200403A (en) | 1997-01-06 | 1997-01-06 | Frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9000346A JPH10200403A (en) | 1997-01-06 | 1997-01-06 | Frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10200403A true JPH10200403A (en) | 1998-07-31 |
Family
ID=11471301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9000346A Withdrawn JPH10200403A (en) | 1997-01-06 | 1997-01-06 | Frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10200403A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010524406A (en) * | 2007-04-12 | 2010-07-15 | テラダイン、 インコーポレイテッド | Cost effective low noise single loop synthesizer |
-
1997
- 1997-01-06 JP JP9000346A patent/JPH10200403A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010524406A (en) * | 2007-04-12 | 2010-07-15 | テラダイン、 インコーポレイテッド | Cost effective low noise single loop synthesizer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040406 |