JPH10189592A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH10189592A JPH10189592A JP35596496A JP35596496A JPH10189592A JP H10189592 A JPH10189592 A JP H10189592A JP 35596496 A JP35596496 A JP 35596496A JP 35596496 A JP35596496 A JP 35596496A JP H10189592 A JPH10189592 A JP H10189592A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- photoresist
- forming
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に、埋め込み配線を備える半導体装置の製
造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having embedded wiring.
【０００２】[0002]
【従来の技術】半導体基板上に形成された層間絶縁膜で
あるシリコン酸化膜に溝を形成し、その溝の内面を窒化
チタン等のバリアメタルで被覆し、しかる後、その溝
に、例えば、銅の金属配線を埋め込むという、いわゆる
ダマシン法において、金属配線上面よりＣｕが層間絶縁
膜であるシリコン酸化膜中に拡散し、シリコン酸化膜の
質を低下させるという問題が有り、それを防止するため
にＣｕ配線形成後、Ｃｕ配線上にチタンタングステン窒
化膜等のバリア膜を形成する方法が有効であることが従
来知られている。2. Description of the Related Art A groove is formed in a silicon oxide film which is an interlayer insulating film formed on a semiconductor substrate, and the inner surface of the groove is covered with a barrier metal such as titanium nitride. In the so-called damascene method of embedding a copper metal wiring, there is a problem that Cu diffuses from the upper surface of the metal wiring into a silicon oxide film which is an interlayer insulating film, thereby deteriorating the quality of the silicon oxide film. It is conventionally known that a method of forming a barrier film such as a titanium tungsten nitride film on a Cu wiring after forming a Cu wiring is effective.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上述の方法で
は、半導体基板全面にバリア膜が形成されるので、層間
容量が増大し、素子の動作速度を低下させるという問題
が有った。However, in the above method, since a barrier film is formed on the entire surface of the semiconductor substrate, there is a problem that the interlayer capacitance increases and the operation speed of the device decreases.
【０００４】そこで、本発明の目的は、ダマシン法に従
って形成したＣｕ配線のバリア膜を層間容量を増大させ
ることなく形成することができる半導体装置の製造方法
を提供することである。An object of the present invention is to provide a method of manufacturing a semiconductor device in which a barrier film of a Cu wiring formed according to a damascene method can be formed without increasing interlayer capacitance.
【０００５】[0005]
【課題を解決するための手段】上述した課題を解決する
本発明の半導体装置の製造方法は、半導体基板上に形成
した絶縁膜に溝を形成する第１の工程と、前記溝が形成
された前記絶縁膜上に、前記溝の内面を被覆するように
第１の導電膜を形成する第２の工程と、前記第２の工程
後、前記第１の導電膜上に、前記溝内を埋め込むように
金属配線を形成する第３の工程と、化学的機械研磨法に
より、前記溝内以外の前記金属配線及び前記第１の導電
膜を除去し、更に、前記溝内の前記金属配線の表層を除
去して、前記金属配線近傍の前記絶縁膜の表面に対して
前記金属配線の表面を陥没させ、前記金属配線に凹部を
形成する第４の工程と、前記第４の工程後、前記凹部を
含む前記半導体基板上に第２の導電膜を形成する第５の
工程と、前記凹部内以外に形成された前記第２の導電膜
を除去する第６の工程と、を備える。According to a method of manufacturing a semiconductor device of the present invention, which solves the above-mentioned problems, a first step of forming a groove in an insulating film formed on a semiconductor substrate, and a step of forming the groove, A second step of forming a first conductive film on the insulating film so as to cover an inner surface of the groove; and filling the groove in the first conductive film after the second step. Forming the metal wiring and removing the metal wiring and the first conductive film other than in the groove by a chemical mechanical polishing method, and further, a surface layer of the metal wiring in the groove. Removing the surface of the metal wiring with respect to the surface of the insulating film near the metal wiring to form a recess in the metal wiring; and after the fourth step, removing the recess A fifth step of forming a second conductive film on the semiconductor substrate, the method including: And a sixth step of removing the formed second conductive film in addition.
【０００６】また、本発明の別の態様による半導体装置
の製造方法は、半導体基板上に形成した絶縁膜に溝を形
成する第１の工程と、前記溝が形成された前記絶縁膜上
に、前記溝の内面を被覆するように第１の導電膜を形成
する第２の工程と、前記第２の工程後、前記第１の導電
膜上に、前記溝内を埋め込むように金属配線を形成する
第３の工程と、前記溝内以外の前記金属配線及び前記第
１の導電膜を除去する第４の工程と、前記第４の工程
後、前記半導体基板上にフォトレジストを形成する第５
の工程と、前記フォトレジストを露光して、前記金属配
線上のフォトレジストを除去する第６の工程と、前記第
６の工程後、前記フォトレジストをマスクとして前記金
属配線の表層をエッチングにより除去し、前記金属配線
近傍の前記絶縁膜の表面に対して前記金属配線の表面を
陥没させ、前記金属配線に凹部を形成する第７の工程
と、前記凹部を含む前記半導体基板上に第２の導電膜を
形成する第８の工程と、前記凹部内以外に形成された前
記第２の導電膜及び前記フォトレジストを除去する第９
の工程と、を備える。Further, a method of manufacturing a semiconductor device according to another aspect of the present invention includes a first step of forming a groove in an insulating film formed on a semiconductor substrate, and a step of forming a groove on the insulating film on which the groove is formed. A second step of forming a first conductive film so as to cover the inner surface of the groove; and after the second step, forming a metal wiring on the first conductive film so as to fill the groove. A third step of removing the metal wiring and the first conductive film other than in the trench, and a fifth step of forming a photoresist on the semiconductor substrate after the fourth step.
And a sixth step of exposing the photoresist to remove the photoresist on the metal wiring. After the sixth step, a surface layer of the metal wiring is removed by etching using the photoresist as a mask. A seventh step of depressing the surface of the metal wiring with respect to the surface of the insulating film near the metal wiring to form a recess in the metal wiring; and forming a second step on the semiconductor substrate including the recess. An eighth step of forming a conductive film, and a ninth step of removing the second conductive film and the photoresist formed other than in the recess.
And a step of
【０００７】本発明の一態様では、前記第６の工程が、
前記第２の導電膜上にフォトレジストを形成する第７の
工程と、前記フォトレジスト及び前記第２の導電膜を、
前記絶縁膜の表面が露出し、且つ、前記凹部が前記第２
の導電膜により埋まる程度にエッチバックする第８の工
程と、を更に備える。In one embodiment of the present invention, the sixth step includes:
A seventh step of forming a photoresist on the second conductive film; and forming the photoresist and the second conductive film on the second conductive film.
The surface of the insulating film is exposed, and the concave portion is the second
An eighth step of etching back to such an extent that the conductive film is filled with the conductive film.
【０００８】本発明の一態様では、前記第６の工程が、
前記絶縁膜の表面が露出し、且つ、前記凹部が前記第２
の導電膜により埋まる程度に前記第２の導電膜に化学的
機械研磨を行う第７の工程、を更に備える。[0008] In one embodiment of the present invention, the sixth step includes:
The surface of the insulating film is exposed, and the concave portion is the second
A seventh step of performing chemical mechanical polishing on the second conductive film to such an extent that the second conductive film is filled with the conductive film.
【０００９】本発明の一態様では、前記第２の導電膜
が、多結晶シリコン、窒化チタン及び窒化チタンタング
ステンのうちのいずれか１つである。In one embodiment of the present invention, the second conductive film is any one of polycrystalline silicon, titanium nitride, and titanium tungsten nitride.
【００１０】本発明の一態様では、前記第９の工程が、
前記第２の導電膜上に第２のフォトレジストを形成する
第１０の工程と、前記第２のフォトレジスト、前記第２
の導電膜及び前記フォトレジストを、前記絶縁膜の表面
が露出し、且つ、前記凹部が前記第２の導電膜により埋
まる程度にエッチバックする第１１の工程と、を更に備
える。In one embodiment of the present invention, the ninth step is:
A tenth step of forming a second photoresist on the second conductive film;
An eleventh step of etching back the conductive film and the photoresist to such an extent that the surface of the insulating film is exposed and the concave portion is filled with the second conductive film.
【００１１】本発明の一態様では、前記第９の工程が、
前記絶縁膜の表面が露出し、且つ、前記凹部が前記第２
の導電膜により埋まる程度に前記第２の導電膜に化学的
機械研磨を行う第１０の工程、を更に備える。In one embodiment of the present invention, the ninth step is:
The surface of the insulating film is exposed, and the concave portion is the second
A tenth step of performing chemical mechanical polishing on the second conductive film to such an extent that the second conductive film is filled with the conductive film.
【００１２】本発明の一態様では、前記第６の工程で、
前記フォトレジストを全面露光し、前記金属配線による
反射を用いて前記金属配線上のフォトレジストを除去す
る。[0012] In one embodiment of the present invention, in the sixth step,
The photoresist is entirely exposed, and the photoresist on the metal wiring is removed using reflection by the metal wiring.
【００１３】[0013]
【実施例】次に、本発明の実施例を図面を参照して説明
する。Next, an embodiment of the present invention will be described with reference to the drawings.
【００１４】図１（ａ）〜（ｄ）は、本発明の第１の実
施例を説明するために工程順に示した半導体基板の断面
図である。FIGS. 1A to 1D are sectional views of a semiconductor substrate shown in the order of steps for explaining a first embodiment of the present invention.
【００１５】まず、図１（ａ）に示すように、シリコン
半導体基板１０の上に、層間絶縁膜となるシリコン酸化
膜３を形成した後、シリコン酸化膜３の表面にフォトリ
ソグラフィー技術及びエッチング技術を用いて、深さ
０．５μｍ程度の配線形成用パターンを有する溝ＤＴを
形成する。次に、溝ＤＴを含むシリコン酸化膜３の上に
スパッタ法により厚さ０．１μｍ程度のバリアメタル
（ＴｉＮ）膜１及びＣｕ膜２を順次形成する。なお、Ｃ
ｕ膜２は、Ｃｕに限らず、金属ならば良く、例えば、Ａ
ｌを用いても良い。First, as shown in FIG. 1A, after a silicon oxide film 3 serving as an interlayer insulating film is formed on a silicon semiconductor substrate 10, a photolithography technique and an etching technique are formed on the surface of the silicon oxide film 3. Is used to form a trench DT having a wiring forming pattern with a depth of about 0.5 μm. Next, a barrier metal (TiN) film 1 and a Cu film 2 having a thickness of about 0.1 μm are sequentially formed on the silicon oxide film 3 including the trench DT by a sputtering method. Note that C
The u film 2 is not limited to Cu, but may be a metal.
1 may be used.
【００１６】次に、図１（ｂ）に示すように、化学的機
械研磨（ＣＭＰ）処理を行い、シリコン酸化膜３の表面
を露出させ、更に、Ｃｕ膜２の表層を陥没させて、Ｃｕ
膜２近傍のシリコン酸化膜３表面よりもＣｕ膜２の表面
の方を低くする。このように、Ｃｕ等の金属は、シリコ
ン酸化膜３やバリアメタル（ＴｉＮ）膜１に比し柔らか
いので、ＣＭＰ処理を施すと、周囲のシリコン酸化膜３
やバリアメタル（ＴｉＮ）膜１の表面よりもやや削れ具
合が大きい。Next, as shown in FIG. 1B, a chemical mechanical polishing (CMP) process is performed to expose the surface of the silicon oxide film 3, and further, the surface layer of the Cu
The surface of the Cu film 2 is made lower than the surface of the silicon oxide film 3 near the film 2. As described above, the metal such as Cu is softer than the silicon oxide film 3 and the barrier metal (TiN) film 1.
It is slightly larger than the surface of the barrier metal (TiN) film 1.
【００１７】次に、図１（ｃ）に示すように、スパッタ
方により、Ｃｕ膜２のバリア膜となる厚さ０．３μｍ程
度のチタンタングステン窒化膜４を形成する。次に、レ
ジスト膜５を厚さ１μｍ程度に形成する。Next, as shown in FIG. 1C, a titanium tungsten nitride film 4 having a thickness of about 0.3 μm to be a barrier film of the Cu film 2 is formed by sputtering. Next, a resist film 5 is formed to a thickness of about 1 μm.
【００１８】次に、図１（ｄ）に示すように、Ａｒスパ
ッタ法によりエッチバックを行い、Ｃｕ膜２上のみチタ
ンタングステン窒化膜４を残す。なお、バリア膜となる
チタンタングステン窒化膜４の代わりに、チタン窒化膜
若しくは多結晶シリコン膜を用いても良い。このよう
に、チタンタングステン窒化膜４上にレジスト膜５を塗
布することにより、Ｃｕ膜２上のチタンタングステン窒
化膜４の陥没部分がレジスト膜５で埋められ、表面が平
坦になるので、図１（ｄ）に示す工程においてエッチバ
ック処理を施した場合、Ｃｕ膜２上にのみチタンタング
ステン窒化膜４を残存させることができる。Next, as shown in FIG. 1D, etch back is performed by an Ar sputtering method to leave the titanium tungsten nitride film 4 only on the Cu film 2. Note that a titanium nitride film or a polycrystalline silicon film may be used instead of the titanium tungsten nitride film 4 serving as a barrier film. By applying the resist film 5 on the titanium tungsten nitride film 4 as described above, the recessed portion of the titanium tungsten nitride film 4 on the Cu film 2 is filled with the resist film 5, and the surface becomes flat. When the etch-back process is performed in the step shown in FIG. 4D, the titanium tungsten nitride film 4 can be left only on the Cu film 2.
【００１９】或いは、図１（ｃ）に示す工程において、
チタンタングステン窒化膜４を形成した後、レジスト膜
５を塗布せずにＣＭＰでチタンタングステン窒化膜４を
研磨することにより、シリコン酸化膜３表面を露出さ
せ、Ｃｕ膜２上にのみチタンタングステン窒化膜４を残
しても良い。Alternatively, in the step shown in FIG.
After forming the titanium tungsten nitride film 4, the surface of the silicon oxide film 3 is exposed by polishing the titanium tungsten nitride film 4 by CMP without applying the resist film 5, and the titanium tungsten nitride film is formed only on the Cu film 2. 4 may be left.
【００２０】図２（ａ）〜（ｅ）は、本発明の第２の実
施例を説明するために工程順に示した半導体基板の断面
図である。FIGS. 2A to 2E are sectional views of a semiconductor substrate shown in the order of steps for explaining a second embodiment of the present invention.
【００２１】まず、図２（ａ）に示すように、シリコン
半導体基板１０の上にシリコン酸化膜３を形成した後、
シリコン酸化膜３の表面に、フォトリソグラフィー技術
及びエッチング技術を用いて、深さ０．５μｍ程度の配
線形成用パターンを有する溝ＤＴを形成する。次に、溝
ＤＴを含むシリコン酸化膜３の上にスパッタ法により厚
さ０．１μｍ程度のバリアメタル（ＴｉＮ）膜１及びＣ
ｕ膜２を順次形成する。しかる後、化学的機械研磨（Ｃ
ＭＰ）処理を行い、シリコン酸化膜３の表面を露出させ
る。First, as shown in FIG. 2A, after a silicon oxide film 3 is formed on a silicon semiconductor substrate 10,
A trench DT having a wiring forming pattern with a depth of about 0.5 μm is formed on the surface of the silicon oxide film 3 by using a photolithography technique and an etching technique. Next, a barrier metal (TiN) film 1 having a thickness of about 0.1 .mu.m is formed on the silicon oxide film 3 including the trench DT by sputtering.
The u film 2 is formed sequentially. Thereafter, chemical mechanical polishing (C
MP) treatment to expose the surface of the silicon oxide film 3.
【００２２】次に、図２（ｂ）に示すように、レジスト
膜５を形成し、Ｃｕ膜２の反射による全面露光を行う。Next, as shown in FIG. 2B, a resist film 5 is formed, and the entire surface is exposed by reflection of the Cu film 2.
【００２３】次に、図２（ｃ）に示すように、Ｃｕ膜２
上以外にのみレジスト膜５を残してＣｕ膜２のエッチン
グを行い、Ｃｕ膜２の上に窪みを付ける。Next, as shown in FIG.
The Cu film 2 is etched while leaving the resist film 5 only on the portions other than the upper portion, so that a depression is formed on the Cu film 2.
【００２４】次に、図２（ｄ）に示すように、半導体基
板１０全面に、バリア膜４としてシリコン窒化膜或いは
ポリシリコン膜を堆積させる。Next, as shown in FIG. 2D, a silicon nitride film or a polysilicon film is deposited as a barrier film 4 on the entire surface of the semiconductor substrate 10.
【００２５】次に、図２（ｅ）に示すように、化学的機
械研磨を行い、Ｃｕ配線上以外のレジスト膜５及びバリ
ア膜４を除去することで、Ｃｕ膜２上にのみバリア膜４
を残す。この結果、シリコン酸化膜３上にレジスト膜５
が除去しきれずに残存している場合には、アッシング処
理によりレジスト膜５を除去する。Next, as shown in FIG. 2E, chemical mechanical polishing is performed to remove the resist film 5 and the barrier film 4 other than on the Cu wiring, so that the barrier film 4 is formed only on the Cu film 2.
Leave. As a result, the resist film 5 is formed on the silicon oxide film 3.
If the resist film 5 remains without being completely removed, the resist film 5 is removed by ashing.
【００２６】また、図２（ｄ）に示す工程後、バリア膜
４上にレジスト膜（不図示）を塗布し、レジスト膜５に
よる段差を緩和して表面を平坦化した後、エッチバック
処理を施して、Ｃｕ配線上以外のレジスト膜５及びバリ
ア膜４を除去することで、Ｃｕ膜２上にのみバリア膜４
を残しても良い。After the step shown in FIG. 2 (d), a resist film (not shown) is applied on the barrier film 4, the step due to the resist film 5 is relaxed, and the surface is flattened. By removing the resist film 5 and the barrier film 4 other than on the Cu wiring, the barrier film 4 is formed only on the Cu film 2.
May be left.
【００２７】[0027]
【発明の効果】本発明により、例えば、ダマシン法に従
って形成されたＣｕ等の金属配線において、金属配線の
上面のみをチタンタングステン窒化膜で被覆することに
より、この金属配線上面からＣｕ等が層間絶縁膜中へ拡
散することを防ぐことができ、且つ、層間容量の増大が
抑制され、素子の動作速度低下を防ぐことができる。According to the present invention, for example, in a metal wiring of Cu or the like formed according to the damascene method, only the upper surface of the metal wiring is covered with a titanium tungsten nitride film, so that Cu or the like is interlayer-insulated from the upper surface of the metal wiring. Diffusion into the film can be prevented, and an increase in interlayer capacitance can be suppressed, and a decrease in the operation speed of the element can be prevented.
【図１】本発明の第１の実施例を説明するために工程順
に示した断面図である。FIG. 1 is a cross-sectional view shown in a process order for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するために工程順
に示した断面図である。FIG. 2 is a cross-sectional view shown in the order of steps for explaining a second embodiment of the present invention.
１ バリアメタル ２ Ｃｕ配線 ３ シリコン酸化膜 ４ チタンタングステン窒化膜（バリア膜） ５ レジスト １０ シリコン半導体基板 ＤＴ 溝 DESCRIPTION OF SYMBOLS 1 Barrier metal 2 Cu wiring 3 Silicon oxide film 4 Titanium tungsten nitride film (barrier film) 5 Resist 10 Silicon semiconductor substrate DT groove
Claims (8)
成する第１の工程と、 前記溝が形成された前記絶縁膜上に、前記溝の内面を被
覆するように第１の導電膜を形成する第２の工程と、 前記第２の工程後、前記第１の導電膜上に、前記溝内を
埋め込むように金属配線を形成する第３の工程と、 化学的機械研磨法により、前記溝内以外の前記金属配線
及び前記第１の導電膜を除去し、更に、前記溝内の前記
金属配線の表層を除去して、前記金属配線近傍の前記絶
縁膜の表面に対して前記金属配線の表面を陥没させ、前
記金属配線に凹部を形成する第４の工程と、 前記第４の工程後、前記凹部を含む前記半導体基板上に
第２の導電膜を形成する第５の工程と、 前記凹部内以外に形成された前記第２の導電膜を除去す
る第６の工程と、 を備えることを特徴とする半導体装置の製造方法。A first step of forming a groove in an insulating film formed on a semiconductor substrate; and a first conductive film on the insulating film on which the groove is formed so as to cover an inner surface of the groove. A second step of forming a metal wiring on the first conductive film so as to fill the trench, after the second step, and a chemical mechanical polishing method, The metal wiring and the first conductive film other than in the groove are removed, and further, the surface layer of the metal wiring in the groove is removed, and the surface of the insulating film in the vicinity of the metal wiring is exposed to the metal. A fourth step of recessing the surface of the wiring to form a recess in the metal wiring; and a fifth step of forming a second conductive film on the semiconductor substrate including the recess after the fourth step. A sixth step of removing the second conductive film formed other than in the concave portion. A method for manufacturing a semiconductor device, comprising:
成する第１の工程と、 前記溝が形成された前記絶縁膜上に、前記溝の内面を被
覆するように第１の導電膜を形成する第２の工程と、 前記第２の工程後、前記第１の導電膜上に、前記溝内を
埋め込むように金属配線を形成する第３の工程と、 前記溝内以外の前記金属配線及び前記第１の導電膜を除
去する第４の工程と、 前記第４の工程後、前記半導体基板上にフォトレジスト
を形成する第５の工程と、 前記フォトレジストを露光して、前記金属配線上のフォ
トレジストを除去する第６の工程と、 前記第６の工程後、前記フォトレジストをマスクとして
前記金属配線の表層をエッチングにより除去し、前記金
属配線近傍の前記絶縁膜の表面に対して前記金属配線の
表面を陥没させ、前記金属配線に凹部を形成する第７の
工程と、 前記凹部を含む前記半導体基板上に第２の導電膜を形成
する第８の工程と、 前記凹部内以外に形成された前記第２の導電膜及び前記
フォトレジストを除去する第９の工程と、 を備えることを特徴とする半導体装置の製造方法。2. A first step of forming a groove in an insulating film formed on a semiconductor substrate, and a first conductive film on the insulating film on which the groove is formed so as to cover an inner surface of the groove. A second step of forming a metal wiring on the first conductive film so as to fill the trench, after the second step, A fourth step of removing wiring and the first conductive film; a fifth step of forming a photoresist on the semiconductor substrate after the fourth step; exposing the photoresist to the metal; A sixth step of removing a photoresist on the wiring; and after the sixth step, removing a surface layer of the metal wiring by etching using the photoresist as a mask, and removing a surface of the insulating film near the metal wiring. The surface of the metal wiring is depressed, A seventh step of forming a concave portion in the metal wiring, an eighth step of forming a second conductive film on the semiconductor substrate including the concave portion, and the second conductive film formed other than in the concave portion And a ninth step of removing the photoresist. A method of manufacturing a semiconductor device, comprising:
前記第２の導電膜上にフォトレジストを形成する第７の
工程と、 前記フォトレジスト及び前記第２の導電膜を、前記絶縁
膜の表面が露出し、且つ、前記凹部が前記第２の導電膜
により埋まる程度にエッチバックする第８の工程と、 を更に備えることを特徴とする半導体装置の製造方法。3. The method according to claim 1, wherein the sixth step includes:
A seventh step of forming a photoresist on the second conductive film; and forming the photoresist and the second conductive film such that a surface of the insulating film is exposed and the concave portion is formed of the second conductive film. An eighth step of performing etch-back to such an extent that the film is filled with the film.
前記絶縁膜の表面が露出し、且つ、前記凹部が前記第２
の導電膜により埋まる程度に前記第２の導電膜に化学的
機械研磨を行う第７の工程、 を更に備えることを特徴とする半導体装置の製造方法。4. The method according to claim 1, wherein the sixth step includes:
The surface of the insulating film is exposed, and the concave portion is the second
A seventh step of performing chemical mechanical polishing on the second conductive film to such an extent that the second conductive film is filled with the conductive film.
電膜が、多結晶シリコン、窒化チタン及び窒化チタンタ
ングステンのうちのいずれか１つであることを特徴とす
る半導体装置の製造方法。5. The method according to claim 1, wherein the second conductive film is one of polycrystalline silicon, titanium nitride, and titanium tungsten nitride.
前記第２の導電膜上に第２のフォトレジストを形成する
第１０の工程と、 前記第２のフォトレジスト、前記第２の導電膜及び前記
フォトレジストを、前記絶縁膜の表面が露出し、且つ、
前記凹部が前記第２の導電膜により埋まる程度にエッチ
バックする第１１の工程と、 を更に備えることを特徴とする半導体装置の製造方法。6. The method according to claim 2, wherein the ninth step is:
A tenth step of forming a second photoresist on the second conductive film, and exposing a surface of the insulating film to the second photoresist, the second conductive film, and the photoresist; and,
An eleventh step of etching back to such an extent that the recess is filled with the second conductive film.
前記絶縁膜の表面が露出し、且つ、前記凹部が前記第２
の導電膜により埋まる程度に前記第２の導電膜に化学的
機械研磨を行う第１０の工程、 を更に備えることを特徴とする半導体装置の製造方法。7. The method according to claim 2, wherein the ninth step is:
The surface of the insulating film is exposed, and the concave portion is the second
A tenth step of performing chemical mechanical polishing on the second conductive film to such an extent that the second conductive film is filled with the conductive film.
前記フォトレジストを全面露光し、前記金属配線による
反射を用いて前記金属配線上のフォトレジストを除去す
ることを特徴とする半導体装置の製造方法。8. The method according to claim 2, wherein in the sixth step,
A method of manufacturing a semiconductor device, comprising: exposing the entire surface of the photoresist, and removing the photoresist on the metal wiring by using reflection by the metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35596496A JPH10189592A (en) | 1996-12-25 | 1996-12-25 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35596496A JPH10189592A (en) | 1996-12-25 | 1996-12-25 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10189592A true JPH10189592A (en) | 1998-07-21 |
Family
ID=18446639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35596496A Withdrawn JPH10189592A (en) | 1996-12-25 | 1996-12-25 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10189592A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251774B1 (en) | 1998-11-10 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
| KR20010061017A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Method for forming a metal line in Semiconductor device |
| KR100309474B1 (en) * | 1999-11-05 | 2001-11-02 | 박종섭 | Metal line forming method |
| US6492260B1 (en) * | 1998-12-02 | 2002-12-10 | Samsung Electronics Co., Ltd. | Method of fabricating damascene metal wiring |
| KR100367734B1 (en) * | 2000-01-27 | 2003-01-10 | 주식회사 하이닉스반도체 | Method for fabricating an interconnection layer for semiconductor device |
| KR100419021B1 (en) * | 2001-03-30 | 2004-02-19 | 주식회사 하이닉스반도체 | Method of fabricating Copper line of semiconductor device |
| US6709973B1 (en) | 1998-12-18 | 2004-03-23 | Rohm Co., Ltd | Method of fabricating semiconductor device |
| KR20040041879A (en) * | 2002-11-12 | 2004-05-20 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100462762B1 (en) * | 2002-06-18 | 2004-12-20 | 동부전자 주식회사 | Method for forming copper metal line of semiconductor device |
-
1996
- 1996-12-25 JP JP35596496A patent/JPH10189592A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251774B1 (en) | 1998-11-10 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
| US6492260B1 (en) * | 1998-12-02 | 2002-12-10 | Samsung Electronics Co., Ltd. | Method of fabricating damascene metal wiring |
| US6709973B1 (en) | 1998-12-18 | 2004-03-23 | Rohm Co., Ltd | Method of fabricating semiconductor device |
| KR100309474B1 (en) * | 1999-11-05 | 2001-11-02 | 박종섭 | Metal line forming method |
| KR20010061017A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Method for forming a metal line in Semiconductor device |
| KR100367734B1 (en) * | 2000-01-27 | 2003-01-10 | 주식회사 하이닉스반도체 | Method for fabricating an interconnection layer for semiconductor device |
| KR100419021B1 (en) * | 2001-03-30 | 2004-02-19 | 주식회사 하이닉스반도체 | Method of fabricating Copper line of semiconductor device |
| KR100462762B1 (en) * | 2002-06-18 | 2004-12-20 | 동부전자 주식회사 | Method for forming copper metal line of semiconductor device |
| KR20040041879A (en) * | 2002-11-12 | 2004-05-20 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
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