JPH10167804A - Ceramic substrate, circuit board using same and its production - Google Patents
Ceramic substrate, circuit board using same and its productionInfo
- Publication number
- JPH10167804A JPH10167804A JP8330651A JP33065196A JPH10167804A JP H10167804 A JPH10167804 A JP H10167804A JP 8330651 A JP8330651 A JP 8330651A JP 33065196 A JP33065196 A JP 33065196A JP H10167804 A JPH10167804 A JP H10167804A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- circuit board
- circuit
- metal
- warpage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
Landscapes
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Ceramic Products (AREA)
- Compositions Of Oxide Ceramics (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高い信頼性、放熱
性を要する電子部品のパワーモジュール等に使用される
金属回路を有する回路基板に用いられるセラミックス基
板及びそれを用いた回路基板及びその回路基板の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic substrate used for a circuit board having a metal circuit used for a power module of an electronic component requiring high reliability and heat radiation, a circuit board using the same, and a circuit using the same. The present invention relates to a method for manufacturing a substrate.
【０００２】[0002]
【従来の技術】従来から各種電子機器の構成部品とし
て、アルミナ（Ａｌ2Ｏ3）、窒化アルミニウム（Ａｌ
Ｎ）、酸化ベリリウム（ＢｅＯ）などのセラミックス焼
結体基板表面に導電層として銅（Ｃｕ）回路板等を一体
に接合した回路基板が広く使用されている。2. Description of the Related Art Conventionally, alumina (Al 2 O 3 ), aluminum nitride (Al
N), a circuit board in which a copper (Cu) circuit board or the like is integrally bonded as a conductive layer to the surface of a ceramic sintered body substrate such as beryllium oxide (BeO) is widely used.
【０００３】これらの回路基板は、熱伝導性および電気
伝導性に優れたＣｕ等の金属により回路板を形成してい
るため、回路動作の遅延が減少するとともに回路配線の
寿命も向上する利点がある。また半田等の接合材料に対
する濡れ性が向上し、セラミックス焼結体表面に半導体
素子（ＩＣチップ）や電極板を高い接合強さで接合する
ことができる。その結果、半導体素子からの発熱の放散
性や素子の動作信頼性を良好に保つことができ、更にセ
ラミックス基板の放熱面にもＣｕ等の金属板を接合する
ことにより、セラミックス基板の応力緩和および熱変形
防止の目的も達成できるという利点を有している。[0003] In these circuit boards, since the circuit board is formed of a metal such as Cu having excellent heat conductivity and electric conductivity, there is an advantage that the delay of the circuit operation is reduced and the life of the circuit wiring is improved. is there. In addition, the wettability to a bonding material such as solder is improved, and a semiconductor element (IC chip) or an electrode plate can be bonded to the surface of the ceramic sintered body with high bonding strength. As a result, the heat dissipation from the semiconductor element and the operation reliability of the element can be kept good. Further, by joining a metal plate such as Cu to the heat radiation surface of the ceramic substrate, the stress relaxation of the ceramic substrate can be reduced. It has the advantage that the object of preventing thermal deformation can also be achieved.
【０００４】[0004]
【発明が解決しようとする課題】回路基板は、ヒートシ
ンクへの接合や電極を接合するなどのモジュールへの実
装工程における実装時の熱応力やモジュールを各種装置
へ装着する時にかかる荷重によって、金属回路間のセラ
ミックス基板や金属回路の端部付近のセラミックス基板
に微小クラックが発生する。その後、モジュールを使用
時の繰り返し加熱冷却による応力のため、微小クラック
が拡大する。クラックの部分で絶縁不良となり、リーク
電流により破壊に至り、パワーモジュールが使用不能と
なる問題がある。A circuit board is formed by a metal circuit due to a thermal stress at the time of mounting in a mounting process to a module, such as bonding to a heat sink and bonding electrodes, and a load applied when the module is mounted to various devices. Fine cracks occur in the ceramic substrate between the ceramic substrates and the ceramic substrate near the end of the metal circuit. Thereafter, the microcracks are enlarged due to the stress caused by repeated heating and cooling when the module is used. There is a problem that the insulation failure occurs at the crack portion, the breakdown occurs due to the leak current, and the power module becomes unusable.
【０００５】回路基板の製造方法としてはいくつかの方
法が知られているが、良好な生産性を得るためには、フ
ルエッチ法がよく使われる。フルエッチ法は、セラミッ
クス基板と金属板をろう材ペーストや基板と金属の共晶
を用いるなどして接合し、回路面とする金属板上に回路
パターンをエッチングレジストにより形成させた後、エ
ッチング処理して不要部分を除去する方法である。フル
エッチ法は、生産性は良好であるが、不要な回路及びろ
う材や共晶の除去工程を経るため、エッチング後金属回
路間のセラミックス基板に大きな引張応力が残留する。[0005] Several methods are known as a method of manufacturing a circuit board, but a full-etch method is often used to obtain good productivity. In the full-etch method, a ceramic substrate and a metal plate are joined by using a brazing material paste or a eutectic of the substrate and the metal, and a circuit pattern is formed on the metal plate serving as a circuit surface using an etching resist, and then an etching process is performed. Then, unnecessary portions are removed. The full-etch method has good productivity, but a large tensile stress remains on the ceramic substrate between the metal circuits after the etching, because the circuit goes through an unnecessary circuit and a step of removing a brazing material and a eutectic.
【０００６】回路基板をパワーモジュールに実装する場
合、熱処理を施した後、ヒートシンク銅板へ接合する。
さらに半導体チップや電極が回路基板に接合される。こ
れらの工程は、エッチング後金属回路間のセラミックス
基板や金属回路の端部付近のセラミックス基板に残留す
る大きな引張応力をさらに増大させるため、クラックが
発生し易い問題があった。さらに、パワーモジュールを
装置に装着する場合においても、ヒートシンクにあらか
じめ開けておいた穴に固定用のボルトを通し、装置にね
じ止めするときの荷重で、セラミックス基板に残留する
大きな引張応力をさらに増大させるため、この時点に於
いてもクラックが発生すると云う問題があった。When a circuit board is mounted on a power module, it is heat-treated and then joined to a heat sink copper plate.
Further, a semiconductor chip and an electrode are joined to the circuit board. These processes further increase the large tensile stress remaining on the ceramic substrate between the metal circuits after etching and the ceramic substrate near the end of the metal circuit, and thus have a problem that cracks are easily generated. Furthermore, even when the power module is mounted on the device, the fixing bolt is passed through the hole previously drilled in the heat sink, and the load when screwing it to the device further increases the large tensile stress remaining on the ceramic substrate. Therefore, there is a problem that cracks are generated even at this time.
【０００７】以上の問題に対して、従来の窒化アルミニ
ウム回路基板においては、ヒートショックやヒートサイ
クルなどの熱衝撃、熱履歴によって生じる損傷に対して
十分な耐久性をもたせるため、銅回路と窒化アルミニウ
ム基板との間に介在させる接合層の厚みを例えば２０μ
ｍ以上に厚くする方法が提案されている。（特開平６−
１９６８２８号公報）しかしながら、接合層の厚みを厚
くすると不要なろう材の除去が困難となるなど、未だ解
決すべき課題があった。In order to solve the above problems, the conventional aluminum nitride circuit board requires a copper circuit and an aluminum nitride in order to have sufficient durability against damage caused by heat shock and heat history such as heat shock and heat cycle. The thickness of the bonding layer interposed between the substrate and the substrate is, for example, 20 μm.
A method of increasing the thickness to m or more has been proposed. (Japanese Unexamined Patent Publication No.
However, when the thickness of the bonding layer is increased, there is still a problem to be solved, for example, it becomes difficult to remove unnecessary brazing material.
【０００８】本発明は、上記に鑑みてなされたものであ
り、回路基板の放熱性、絶縁耐圧を損なうことなく、ク
ラック発生を低減させ、信頼性の高い回路基板を提供す
ること及びその製造方法を提供すること及びそれらに適
したセラミックス基板を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above, and provides a highly reliable circuit board which reduces the occurrence of cracks and does not impair the heat dissipation and dielectric strength of the circuit board, and a method of manufacturing the same. And a ceramic substrate suitable for them.
【０００９】[0009]
【課題を解決するための手段】そこで本発明者らは、セ
ラミックス基板の接合前の初期形状を工夫し、回路基板
の製造時にセラミックス基板の金属回路接合面側に予め
圧縮応力を与えることにより、クラックの発生を低減す
ることが可能であることを見出し、本発明に到達したも
のである。Therefore, the present inventors devised the initial shape of the ceramic substrate before the bonding and applied a compressive stress to the metal circuit bonding surface side of the ceramic substrate in advance during the manufacture of the circuit board. The inventors have found that the occurrence of cracks can be reduced, and have reached the present invention.
【００１０】すなわち本発明は、本質的に板状体であ
り、そりを持つセラミックス焼結体であって、一方向の
そり量が、該方向の長さの１／４０００から１／１００
で有り、該方向の直角方向のそり量が該方向のそり量の
１／２以下（０を含む）であることを特徴とするセラミ
ックス基板である。That is, the present invention relates to a ceramic sintered body having a plate shape and a warp, wherein the warp amount in one direction is 1/4000 to 1/100 of the length in the direction.
Wherein the warpage in a direction perpendicular to the direction is not more than 1/2 (including 0) of the warpage in the direction.
【００１１】更に、本発明は反りを持つセラミックス基
板の室温の熱膨張係数が５×１０-6１／℃以下であるこ
とを特徴とする上記セラミックス基板である。Further, the present invention is the above-mentioned ceramic substrate, wherein the warped ceramic substrate has a coefficient of thermal expansion at room temperature of 5 × 10 −6 1 / ° C. or less.
【００１２】また、本発明は、上記セラミックス基板を
用いたことを特徴とする回路基板である。Further, the present invention is a circuit board using the above ceramic substrate.
【００１３】更に、本発明は上記セラミックス基板の凸
面側に回路形成用金属板を、凹面側に放熱部形成用金属
板を配置して、加熱接合することを特徴とする上記回路
基板の製造方法である。Further, the present invention provides a method of manufacturing a circuit board according to the present invention, wherein a metal plate for forming a circuit is disposed on a convex side of the ceramic substrate, and a metal plate for forming a heat radiating portion is disposed on a concave side of the ceramic substrate, and the substrates are heated and joined. It is.
【００１４】[0014]
【発明の実施の形態】以下、さらに詳しく本発明につい
て説明する。本発明で使用されるセラミックス基板はア
ルミナ、ムライト、窒化珪素、窒化アルミ、酸化ベリリ
ウムなど絶縁性、耐熱性に優れる材料であればいずれを
用いても良い。一般に窒化アルミニウム基板、窒化珪素
基板のように非酸化物セラミックスの基板は室温に於け
る熱膨張係数が５×１０-6 １／℃以下と小さく、金属
との熱膨張係数差が大きい。この為製造工程で金属回路
との間に応力が発生しやすい為、本発明によるクラック
防止効果が大きい。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in more detail. As the ceramic substrate used in the present invention, any material having excellent insulation and heat resistance such as alumina, mullite, silicon nitride, aluminum nitride, and beryllium oxide may be used. In general, a non-oxide ceramic substrate such as an aluminum nitride substrate or a silicon nitride substrate has a small thermal expansion coefficient at room temperature of 5 × 10 −6 / ° C. or less, and has a large difference in thermal expansion coefficient from metals. For this reason, a stress is easily generated between the metal circuit and the metal circuit in the manufacturing process, and the effect of preventing cracks according to the present invention is great.
【００１５】セラミックス基板として材料特性には特に
制限はないが、良好な放熱性を示すためには、熱伝導率
が８０Ｗ／ｍＫ以上のものが適している。また、基板の
曲げ強さについては、回路基板形成後の強さに影響を及
ぼすため３５０ＭＰａ以上のものが適当である。このよ
うな特性を示すセラミックスとして窒化アルミニウム或
いは窒化珪素が知られている。The material properties of the ceramic substrate are not particularly limited, but those having a thermal conductivity of 80 W / mK or more are suitable for exhibiting good heat dissipation. Also, the bending strength of the substrate is preferably 350 MPa or more because it affects the strength after the formation of the circuit board. Aluminum nitride or silicon nitride is known as a ceramic exhibiting such characteristics.
【００１６】セラミックス基板の厚みは、要求される回
路基板の強さによって異なるが、通常、０．３ｍｍから
１．５ｍｍのものが使われる。The thickness of the ceramic substrate varies depending on the required strength of the circuit board, but usually a thickness of 0.3 mm to 1.5 mm is used.
【００１７】本発明のセラミックス基板において重要な
ことは、本質的に板状体であり、そりを持つ燒結体であ
って、一方向のそり量が、該方向の長さの１／４０００
から１／１００である事である。この方向は基板形状が
長方形の場合いわゆる長手方向であることが望ましい。
該方向の直角方向のそり量が該方向のそり量の１／２以
下（０を含む）であることである。そり量が該方向の長
さの１／４０００をしたまわると本発明の効果が得られ
ず、そり量が該方向の１／１００を越えると、接合時に
生じる、セラミックス基板の内部ひずみが大きくなりす
ぎ、強さの小さいセラミックス基板では、破壊してしま
うこともある。また、該方向の直角方向のそり量は小さ
い方が好ましい、すなわち反りは一方向に一様が好まし
いが、該方向の１／２迄許容される。該方向のそり量の
１／２を越えると回路基板にした場合に金属板との接合
不良が起きやすくなる。What is important in the ceramic substrate of the present invention is that the sintered body is essentially a plate-like body and has a warp, and the amount of warp in one direction is 1/4000 of the length in the direction.
From 1/100. This direction is preferably a so-called longitudinal direction when the substrate is rectangular.
The amount of warpage in the direction perpendicular to the direction is less than or equal to 1/2 (including 0) of the amount of warpage in the direction. If the amount of warp is less than 1/4000 of the length in the direction, the effect of the present invention cannot be obtained. If the amount of warp exceeds 1/100 of the direction, the internal strain of the ceramic substrate generated at the time of joining increases. If the ceramic substrate is too weak, it may be broken. Also, it is preferable that the amount of warp in the direction perpendicular to the direction is small, that is, the warp is preferably uniform in one direction, but is allowed up to 1/2 of the direction. If the amount of warpage exceeds １ ／, the bonding failure with the metal plate tends to occur when the circuit board is used.
【００１８】セラミックス基板に形成される金属回路も
しくは金属回路と金属放熱板の材質は、銅、ニッケル、
アルミニウム、モリブデン、タングステン等の純金属も
しくは合金であって、その厚みは０．１〜２．０ｍｍが
使われる。The material of the metal circuit formed on the ceramic substrate or the metal circuit and the metal radiator plate may be copper, nickel,
It is a pure metal or alloy such as aluminum, molybdenum and tungsten, and its thickness is 0.1 to 2.0 mm.
【００１９】本発明に係る接合層はろう材ペーストを用
いて形成されたものであっても、セラミックスと金属の
共晶相により形成されたものでもよい。ここで使用され
るろう材ペーストは、例えば金属回路又は金属放熱板の
材質がＣｕである場合、ＡｇもしくはＣｕもしくはＡｇ
とＣｕを含むろう材である。また、ここで用いる共晶相
は、例えば、セラミックス基板がアルミナで金属回路又
は金属放熱板の材質がＣｕの場合にはＣｕ−Ｏの共晶相
である。The bonding layer according to the present invention may be formed using a brazing material paste or may be formed using a eutectic phase of ceramic and metal. The brazing material paste used here is, for example, Ag or Cu or Ag when the material of the metal circuit or the metal radiator plate is Cu.
And a brazing material containing Cu. Further, the eutectic phase used here is, for example, a Cu-O eutectic phase when the ceramic substrate is alumina and the material of the metal circuit or the metal radiator plate is Cu.
【００２０】本発明の回路基板において重要なことは、
図１の概念図に示すようにそりのあるセラミックス基板
と金属回路、金属放熱板を接合するときに、セラミック
ス基板のそりの凸面側に回路形成用金属板を、凹面側に
放熱部形成用金属板を配置して、セラミックス基板をた
わませ、そりを修正した状態（みかけの反り量が該方向
の長さの１／４０００未満）で、加熱接合することであ
る。また、金属回路のパターン抜き部分が連続している
場合には、それとは直角な方向にそりのあるセラミック
ス基板を用いる方が効果は著しく大きくなる。What is important in the circuit board of the present invention is that
As shown in the conceptual diagram of FIG. 1, when a warped ceramic substrate is bonded to a metal circuit and a metal heat radiating plate, a circuit forming metal plate is formed on the convex surface of the ceramic substrate and a heat radiating portion forming metal is formed on the concave surface. A board is placed, a ceramic substrate is bent, and the ceramic substrate is heated and joined in a corrected warp state (the apparent amount of warpage is less than 1/4000 of the length in the direction). In the case where the pattern cut portion of the metal circuit is continuous, the use of a ceramic substrate having a warp in a direction perpendicular to the pattern portion has a remarkable effect.
【００２１】本発明のセラミックス基板を製造する方法
について、セラミックス基板が窒化アルミニウムの場合
について一例を示す。窒化アルミニウム粉末と燒結助剤
を含むスラリーを調整した後グリーンシートに成形す
る。このグリーンシートを本請求項に係る形状を持つよ
うに作製した窒化ボロン製の治具にのせ、バインダーを
除去した後、不活性雰囲気下、１７００℃以上の温度で
燒結させる。An example of the method for manufacturing a ceramic substrate according to the present invention will be described in the case where the ceramic substrate is aluminum nitride. After preparing a slurry containing aluminum nitride powder and a sintering aid, it is formed into a green sheet. This green sheet is placed on a jig made of boron nitride manufactured to have the shape according to the present invention, and after removing the binder, it is sintered at a temperature of 1700 ° C. or more in an inert atmosphere.
【００２２】本発明の回路基板を製造する方法について
一例を説明する。先ず、本発明の請求項に示すセラミッ
クス基板の表面全体にＡｇとＣｕ及び活性金属を含むろ
う材ペーストを塗布する。An example of a method for manufacturing a circuit board according to the present invention will be described. First, a brazing material paste containing Ag, Cu and an active metal is applied to the entire surface of the ceramic substrate according to the present invention.
【００２３】ペースト面を覆うに十分な広さの放熱板側
のベタ金属板を置き、次ぎにセラミックス基板をそりの
凸面側を上面にして置き、更に金属回路側のベタ金属板
を置いて、その上からセラミックス基板のそりを修正す
るための荷重をかけ、荷重を負荷したまま熱処理を行い
接合する。荷重をかける方法は、重しであっても良い
し、ホットプレスのように油圧又は機械的な圧力をかけ
る等いずれの方法であっても加熱と荷重に耐える治具を
適宜選択して実施すればよい。A solid metal plate on the heatsink side large enough to cover the paste surface is placed, then a ceramic substrate is placed with the convex side of the sled facing up, and further a solid metal plate on the metal circuit side is placed. A load for correcting the warpage of the ceramic substrate is applied from above, and heat treatment is performed while applying the load to perform joining. The method of applying a load may be weighting, or a method of applying a hydraulic pressure or a mechanical pressure such as a hot press, whichever method is used, may be performed by appropriately selecting a jig that can withstand the heating and the load. I just need.
【００２４】次いで、接合体の金属板上にエッチングレ
ジストを用いて回路パターンをスクリーン印刷し、レジ
スト回路パターンを形成させる。Next, a circuit pattern is screen-printed on the metal plate of the joined body using an etching resist to form a resist circuit pattern.
【００２５】エッチング処理してパターン外の不要な金
属やろう材等を除去した後、エッチングレジスト膜を除
去して金属回路を有するセラミックス基板とする。その
後、金属回路の酸化と腐食を防止するため、必要に応じ
てＮｉメッキ等により選択的に金属回路上に保護膜を形
成させる。以下に実施例に基づいて、本発明を更に詳細
に説明する。After removing unnecessary metal and brazing material outside the pattern by etching, the etching resist film is removed to obtain a ceramic substrate having a metal circuit. Thereafter, in order to prevent oxidation and corrosion of the metal circuit, a protective film is selectively formed on the metal circuit by Ni plating or the like as necessary. Hereinafter, the present invention will be described in more detail based on examples.
【００２６】[0026]
【実施例】窒化アルミニウム粉末と燒結助剤を含むスラ
リーを調整した後グリーンシートに成形する。このグリ
ーンシートを以下に示す反りを持つＢＮ製の治具にの
せ、バインダーを除去した後、窒素雰囲気下、１８５０
℃の温度で燒結させる。このようにして、一方向のそり
量がそれぞれ５、１０、５０、１００、２００、３０
０、４００、５００μｍでサイズ４０ｍｍ×４０ｍｍ、
厚み０．６３５ｍｍの窒化アルミニウム基板を製造し
た。これらの窒化アルミニウム基板は該方向の直角方向
のそり量は該方向のそり量の１／２以下であった。EXAMPLE A slurry containing aluminum nitride powder and a sintering aid is prepared and then formed into a green sheet. This green sheet was placed on a BN jig having the following warpage, and after removing the binder, 1850 was placed under a nitrogen atmosphere.
Sinter at a temperature of ° C. In this way, the warpage amounts in one direction are 5, 10, 50, 100, 200, and 30, respectively.
0, 400, 500 μm and size 40 mm × 40 mm,
An aluminum nitride substrate having a thickness of 0.635 mm was manufactured. In these aluminum nitride substrates, the warpage in the direction perpendicular to the direction was not more than １ ／ of the warpage in the direction.
【００２７】また、窒化アルミニウム粉末の変わりに窒
化珪素粉末を用いる以外は上記と同様にして、一方向の
そり量がそれぞれ２００、５００μｍでサイズ４０ｍｍ
×４０ｍｍ、厚み０．６３５ｍｍの窒化珪素基板を製造
した。これらの窒化珪素基板は該方向の直角方向のそり
量は該方向のそり量の１／２以下であった。In the same manner as described above except that silicon nitride powder was used instead of aluminum nitride powder, the warpage in one direction was 200 and 500 μm, respectively, and the size was 40 mm.
A silicon nitride substrate having a size of × 40 mm and a thickness of 0.635 mm was manufactured. In these silicon nitride substrates, the amount of warpage in the direction perpendicular to the direction was not more than の of the amount of warpage in the direction.
【００２８】また、窒化アルミニウム粉末の変わりにア
ルミナ粉末を用いる以外は上記と同様にして、一方向の
そり量がそれぞれ２００、５００μｍでサイズ４０ｍｍ
×４０ｍｍ、厚み０．６３５ｍｍのアルミナ基板を製造
した。これらのアルミナ基板は該方向の直角方向のそり
量は該方向のそり量の１／２以下であった。In the same manner as described above except that alumina powder was used instead of aluminum nitride powder, the warpage in one direction was 200 and 500 μm, respectively, and the size was 40 mm.
An alumina substrate having a size of × 40 mm and a thickness of 0.635 mm was produced. In these alumina substrates, the amount of warpage in a direction perpendicular to the direction was not more than の of the amount of warpage in the direction.
【００２９】上記の各基板の両面にＡｇ−Ｃｕ系の活性
金属含有ろう材ペーストをスクリーン印刷法により塗布
し乾燥した後、凸面側に厚み０．３ｍｍの金属回路用Ｃ
ｕ板を、凹面側に厚み０．１５ｍｍの金属放熱用Ｃｕ板
を接触配置するように１０Ｋｇの重しを載せ、真空中８
３０℃で３０分間熱処理を行いセラミックス基板とＣｕ
板の接合体を得た。An Ag-Cu-based active metal-containing brazing material paste is applied to both surfaces of each of the above substrates by screen printing and dried, and then a 0.3 mm thick metal circuit C
A 10 kg weight is placed on the u plate so that a 0.15 mm thick metal heat dissipation Cu plate is placed in contact with the concave side, and the plate is placed in a vacuum.
Heat treatment at 30 ° C. for 30 minutes to make ceramic substrate and Cu
A bonded plate was obtained.
【００３０】また、そり量が５０、１００μｍの窒化ア
ルミニウム基板の両面にＡｇ−Ｃｕ系の活性金属含有ろ
う材ペーストをスクリーン印刷法により塗布し乾燥した
後、凹面側に厚み０．３ｍｍの金属回路用Ｃｕ板を、凸
面側に厚み０．１５ｍｍの金属放熱用Ｃｕ板を接触配置
するように重しを載せ、真空中８３０℃で３０分間熱処
理を行い窒化アルミニウム基板とＣｕ板の接合体を得
た。さらに、そりのない窒化アルミニウム基板について
も同様に行い窒化アルミニウム基板とＣｕ板の接合体を
得た。Further, an Ag-Cu-based active metal-containing brazing material paste is applied on both sides of an aluminum nitride substrate having a warpage of 50 or 100 μm by screen printing and dried, and then a metal circuit having a thickness of 0.3 mm is formed on the concave side. Is placed on the convex surface side so that a metal heat dissipation Cu plate having a thickness of 0.15 mm is placed in contact therewith, and heat-treated at 830 ° C. for 30 minutes in vacuum to obtain a joined body of the aluminum nitride substrate and the Cu plate. Was. Further, the same procedure was applied to an aluminum nitride substrate having no warp to obtain a joined body of the aluminum nitride substrate and the Cu plate.
【００３１】これらの接合体のＣｕ板上に紫外線硬化型
エッチングレジストをスクリーン印刷法により回路パタ
ーンに印刷し硬化させた後、塩化第２鉄溶液でパターン
外の不要なＣｕを除去した。次いで、フッ化水素アンモ
ニウムと過酸化水素を含む水溶液に入れ、Ｃｕ回路パタ
ーン間の不要ろう材を除去した後、レジストを除去し
た。更に、無電解ＮｉメッキによりＣｕ回路に選択的に
Ｎｉ保護膜を形成させた。An ultraviolet-curable etching resist was printed on the circuit board by a screen printing method on the Cu plates of these joined bodies and cured, and unnecessary Cu outside the pattern was removed with a ferric chloride solution. Next, the substrate was placed in an aqueous solution containing ammonium hydrogen fluoride and hydrogen peroxide to remove unnecessary brazing material between Cu circuit patterns, and then the resist was removed. Further, a Ni protective film was selectively formed on the Cu circuit by electroless Ni plating.
【００３２】以上のようにして、実施例１から８、及び
比較例１から７の試料を得た。このようにして、表１の
実施例、比較例に示すような回路基板を完成させた。As described above, samples of Examples 1 to 8 and Comparative Examples 1 to 7 were obtained. Thus, the circuit boards as shown in the examples and comparative examples in Table 1 were completed.
【００３３】これらの回路基板についてヒートサイクル
試験を実施した。ヒートサイクル試験は、−４０℃で３
０分間保持し、１２５℃で３０分間保持する加熱冷却操
作を１サイクルとし、ＪＩＳ-Ｃ-００２５温度変化試験
方法に準じて実施した。１０回、３０回、５０回、１０
０回のヒートサイクル試験後にクラック発生の有無を評
価した。クラックの評価は、回路間のクラックの有無を
蛍光探傷検査により観察することで行った。結果を表１
に示す。クラックは発生率（％）で示した。A heat cycle test was performed on these circuit boards. The heat cycle test was performed at -40 ° C for 3 hours.
The heating / cooling operation in which the temperature was held for 0 minute and the temperature was held at 125 ° C. for 30 minutes was defined as one cycle, and the test was performed in accordance with JIS-C-0025 temperature change test method. 10, 30, 50, 10
After 0 heat cycle tests, the occurrence of cracks was evaluated. The evaluation of cracks was performed by observing the presence or absence of cracks between circuits by fluorescence inspection. Table 1 shows the results
Shown in Cracks are indicated by the incidence (%).
【００３４】[0034]
【表１】 [Table 1]
【００３５】表１に示す結果から明らかなように、実施
例１〜８に示す回路基板は、ヒートサイクル試験３０回
後のヒートシンク接合でもセラミックス基板にクラック
は発生しておらず、高い信頼性を有し、実用的である。As is clear from the results shown in Table 1, the circuit boards shown in Examples 1 to 8 had no cracks in the ceramic substrate even after the heat sink bonding after the heat cycle test was performed 30 times, and showed high reliability. Has and is practical.
【００３６】一方、比較例１及び５〜７に係る回路基板
は、ヒートサイクル試験３０回でヒートシンク接合でク
ラックが発生し、ヒートサイクルの繰り返し回数の増加
に伴い、基板に発生するクラックが多くなったため、充
分な信頼性が得られない。また、比較例２〜４に係る回
路基板は初期反り量が大きいため、ヒートサイクル実施
前にクラック発生が多数認められた。また、実施例４、
７、８を比較すると、室温の熱膨張係数が５×１０-6
１／℃以下であるセラミックス基板を用いた４、７の方
が効果が高いことが明白である。On the other hand, in the circuit boards according to Comparative Examples 1 and 5 to 7, cracks were generated by heat sink bonding in the heat cycle test 30 times, and the number of cracks generated on the board increased with an increase in the number of heat cycles. Therefore, sufficient reliability cannot be obtained. Further, since the circuit boards according to Comparative Examples 2 to 4 had a large initial warpage, many cracks were observed before the heat cycle was performed. Example 4
Comparing 7 and 8, the thermal expansion coefficient at room temperature is 5 × 10 -6.
It is clear that the effects 4 and 7 using the ceramic substrate at 1 / ° C. or lower are more effective.
【００３７】[0037]
【発明の効果】本発明によれば、高い信頼性、放熱性を
有する回路基板、及びそのためのセラミックス基板を提
供することができる。According to the present invention, it is possible to provide a circuit board having high reliability and heat dissipation, and a ceramic substrate therefor.
【図１】本発明に係る回路基板について概略図を示した
ものである。FIG. 1 is a schematic diagram showing a circuit board according to the present invention.
ｗ：本発明のセラミックス基板のそり量を示す。 w: indicates the amount of warpage of the ceramic substrate of the present invention.
Claims (4)
一方向のそり量が、その方向の長さの１／４０００から
１／１００で有り、該方向の直角方向のそり量が該方向
のそり量の１／２以下（０を含む）であることを特徴と
するセラミックス基板。1. A sintered ceramic plate having a sled,
The amount of warp in one direction is 1/4000 to 1/100 of the length in that direction, and the amount of warp in the direction perpendicular to the direction is 1/2 or less (including 0) the amount of warp in the direction. A ceramic substrate characterized by the following:
×１０-6 １／℃以下であることを特徴とする請求項１
に記載のセラミックス基板。2. A ceramic substrate having a thermal expansion coefficient of 5 at room temperature.
2. The temperature is not higher than × 10 −6 1 / ° C.
A ceramic substrate according to item 1.
を用いたことを特徴とする回路基板。3. A circuit board using the ceramic substrate according to claim 1.
の凸面側に回路形成用金属板を、凹面側に放熱部形成用
金属板を配置して、加熱接合することを特徴とする請求
項３に記載の回路基板の製造方法4. The ceramic substrate according to claim 1, wherein a metal plate for forming a circuit is disposed on a convex surface side of the ceramic substrate, and a metal plate for forming a heat radiating portion is disposed on the concave surface side, and heat bonding is performed. 3. The method for manufacturing a circuit board according to item 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33065196A JP3722573B2 (en) | 1996-12-11 | 1996-12-11 | Ceramic substrate, circuit board using the same, and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33065196A JP3722573B2 (en) | 1996-12-11 | 1996-12-11 | Ceramic substrate, circuit board using the same, and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10167804A true JPH10167804A (en) | 1998-06-23 |
| JP3722573B2 JP3722573B2 (en) | 2005-11-30 |
Family
ID=18235060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33065196A Expired - Fee Related JP3722573B2 (en) | 1996-12-11 | 1996-12-11 | Ceramic substrate, circuit board using the same, and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3722573B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000024692A1 (en) * | 1998-10-28 | 2000-05-04 | Sumitomo Electric Industries, Ltd. | Silicon nitride composite substrate |
| US7403395B2 (en) | 2005-12-14 | 2008-07-22 | Omron Corporation | Power module structure and solid state relay using same |
| CN114667806A (en) * | 2019-11-15 | 2022-06-24 | 电化株式会社 | Ceramic substrate, composite substrate, circuit substrate, method for manufacturing ceramic substrate, method for manufacturing composite substrate, method for manufacturing circuit substrate, and method for manufacturing plurality of circuit substrates |
| CN114830837A (en) * | 2019-11-15 | 2022-07-29 | 电化株式会社 | Ceramic substrate, composite substrate, circuit substrate, method for manufacturing ceramic substrate, method for manufacturing composite substrate, method for manufacturing circuit substrate, and method for manufacturing plurality of circuit substrates |
| CN116504683A (en) * | 2023-06-25 | 2023-07-28 | 江苏富乐华半导体科技股份有限公司 | Method for controlling warpage of copper DBC (copper-nickel) product |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315179A (en) * | 2011-09-03 | 2012-01-11 | 江苏宏微科技有限公司 | Metal-coated ceramic baseplate and manufacturing method thereof |
-
1996
- 1996-12-11 JP JP33065196A patent/JP3722573B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000024692A1 (en) * | 1998-10-28 | 2000-05-04 | Sumitomo Electric Industries, Ltd. | Silicon nitride composite substrate |
| US6599637B1 (en) | 1998-10-28 | 2003-07-29 | Sumitomo Electric Industries, Ltd. | Silicon nitride composite substrate |
| US7403395B2 (en) | 2005-12-14 | 2008-07-22 | Omron Corporation | Power module structure and solid state relay using same |
| DE102006058347B4 (en) * | 2005-12-14 | 2010-09-16 | Omron Corp. | Structure of a power module and this using semiconductor relay |
| CN114667806A (en) * | 2019-11-15 | 2022-06-24 | 电化株式会社 | Ceramic substrate, composite substrate, circuit substrate, method for manufacturing ceramic substrate, method for manufacturing composite substrate, method for manufacturing circuit substrate, and method for manufacturing plurality of circuit substrates |
| CN114830837A (en) * | 2019-11-15 | 2022-07-29 | 电化株式会社 | Ceramic substrate, composite substrate, circuit substrate, method for manufacturing ceramic substrate, method for manufacturing composite substrate, method for manufacturing circuit substrate, and method for manufacturing plurality of circuit substrates |
| CN114830837B (en) * | 2019-11-15 | 2024-04-02 | 电化株式会社 | Ceramic substrate, composite substrate, circuit substrate, and method for manufacturing ceramic substrate, method for manufacturing composite substrate, method for manufacturing circuit substrate, and method for manufacturing a plurality of circuit substrates |
| CN114667806B (en) * | 2019-11-15 | 2024-04-02 | 电化株式会社 | Ceramic substrate, composite substrate, circuit substrate, and method for manufacturing ceramic substrate, method for manufacturing composite substrate, method for manufacturing circuit substrate, and method for manufacturing a plurality of circuit substrates |
| CN116504683A (en) * | 2023-06-25 | 2023-07-28 | 江苏富乐华半导体科技股份有限公司 | Method for controlling warpage of copper DBC (copper-nickel) product |
| CN116504683B (en) * | 2023-06-25 | 2023-08-25 | 江苏富乐华半导体科技股份有限公司 | Method for controlling warpage of copper DBC (copper-nickel) product |
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| Publication number | Publication date |
|---|---|
| JP3722573B2 (en) | 2005-11-30 |
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