JPH10125850A - Lead frame, semiconductor device and manufacturing method thereof - Google Patents

Lead frame, semiconductor device and manufacturing method thereof

Info

Publication number
JPH10125850A
JPH10125850A JP8275684A JP27568496A JPH10125850A JP H10125850 A JPH10125850 A JP H10125850A JP 8275684 A JP8275684 A JP 8275684A JP 27568496 A JP27568496 A JP 27568496A JP H10125850 A JPH10125850 A JP H10125850A
Authority
JP
Japan
Prior art keywords
lead
lead frame
semiconductor device
bump
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8275684A
Other languages
Japanese (ja)
Inventor
Fujiaki Nose
藤明 野瀬
Yuji Watanabe
祐二 渡邊
Taku Kikuchi
卓 菊池
Takashi Miwa
孝志 三輪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8275684A priority Critical patent/JPH10125850A/en
Publication of JPH10125850A publication Critical patent/JPH10125850A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48481—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball
    • H01L2224/48482—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of bonding wires and realize a thin type package. SOLUTION: Above a semiconductor chip 2 a lead frame locates through an insulation tape 3 to form a lead-on-chip(LOC) structure of the semiconductor device. Bumps BB are formed on bonding pads of the chip 2. The top ends of inner leads 4a overlay the bumps BB. Connection fixing recesses 4a1 having the same width as that of the bump BB and depth ranging from 50μm to about a half the thickness of the lead are formed into the top ends of the leads 4a by the half etching, etc. When die-bonding the chip 2, the inner leads 4a and the bumps BB are thermally compression welded so that the recesses 4a1 cover the bumps BB.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、リードフレーム、
半導体装置およびその製造方法に関し、特に、ＬＯＣ
（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）構造の半導体装置におけ
るパッケージの薄型化に適用して有効な技術に関するも
のである。TECHNICAL FIELD The present invention relates to a lead frame,
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly
The present invention relates to a technology effective when applied to a thin package in a semiconductor device having a (Lead On Chip) structure.

【０００２】[0002]

【従来の技術】本発明者が検討したところによれば、多
ピン化、薄型化に対応するパッケージング技術としてＬ
ＯＣ構造の半導体装置が広く知られている。2. Description of the Related Art According to studies made by the present inventor, it has been found that a packaging technology corresponding to an increase in the number of pins and a reduction in thickness has been developed.
Semiconductor devices having the OC structure are widely known.

【０００３】このＬＯＣ構造の半導体装置は、半導体チ
ップの上方にリードフレームのリードの先端部が位置し
ており、当該半導体チップの中央部付近に設けられた電
極部とリードの先端部とをボンディングワイヤによって
電気的に接続し、熱硬化性樹脂などで半導体チップが位
置しているキャビティを封止している。In this semiconductor device having a LOC structure, the tip of a lead of a lead frame is located above a semiconductor chip, and an electrode provided near the center of the semiconductor chip is bonded to the tip of the lead. The cavities where the semiconductor chips are located are sealed by a thermosetting resin or the like, which are electrically connected by wires.

【０００４】なお、この種の半導体装置について詳しく
述べてある例としては、１９９３年５月３１日、日経Ｐ
Ｂ社発行、香山晋、成瀬邦彦（監修）、「実践講座 Ｖ
ＬＳＩパッケージング技術（下）」Ｐ１７９〜Ｐ１８１
があり、この文献には、ＬＯＣ構造のようなリードフレ
ームを用いて構成されたＶＳＭＰ（ＶｅｒｔｉｃａｌＳ
ｕｒｆａｃｅ Ｍｏｕｎｔ Ｐａｃｋａｇｅ）の半導体
装置の構造などが記載されている。[0004] As an example describing this kind of semiconductor device in detail, see Nikkei P. on May 31, 1993.
Published by Company B, Susumu Kayama, Kunihiko Naruse (supervised), "Practical Course V
LSI Packaging Technology (Bottom) "P179-P181
In this document, there is a VSMP (VerticalShell) configured using a lead frame such as a LOC structure.
This document describes the structure of a semiconductor device of a surface mount package.

【０００５】[0005]

【発明が解決しようとする課題】ところが、上記のよう
なＬＯＣ構造の半導体装置では、次のような問題点があ
ることが本発明者により見い出された。However, the present inventors have found that the semiconductor device having the LOC structure as described above has the following problems.

【０００６】すなわち、リードフレームのリードと半導
体チップの電極部とをボンディングワイヤによって電気
的に接続するので、ボンディングワイヤが弧状に形成さ
れ、この弧を描いたボンディングワイヤにおける弧の最
高点、すなわち、ループ高さを最低限確保してパッケー
ジを形成しなければならず、ＬＯＣ構造の半導体装置の
薄型化の懸案事項となっている。That is, since the leads of the lead frame and the electrode portions of the semiconductor chip are electrically connected by the bonding wires, the bonding wires are formed in an arc shape, and the highest point of the arc in the bonding wire that draws this arc, that is, A package must be formed with a minimum loop height secured, which is a concern for thinning a LOC-structured semiconductor device.

【０００７】本発明の目的は、ボンディングワイヤを不
要とし、パッケージを薄型化することのできるリードフ
レーム、半導体装置およびその製造方法を提供すること
にある。An object of the present invention is to provide a lead frame, a semiconductor device, and a method of manufacturing the same, which eliminate the need for bonding wires and can reduce the thickness of the package.

【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【０００９】[0009]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１０】すなわち、本発明のリードフレームは、半
導体チップの電極部に設けられたバンプと直接電気的に
接続されるインナリードの先端部に、該バンプを密着さ
せる接続固定部を設けた構造よりなるものである。That is, the lead frame of the present invention has a structure in which a connection fixing portion for closely contacting the bump is provided at the tip of the inner lead which is directly electrically connected to the bump provided on the electrode portion of the semiconductor chip. It becomes.

【００１１】それにより、インナリードとバンプとを直
接電気的に接続することができるのでワイヤボンディン
グを不要とすることができ、且つインナリードとバンプ
との接触面積が大きくなることによって電気的特性を向
上させることができる。As a result, since the inner leads and the bumps can be directly electrically connected, wire bonding can be eliminated, and the electrical characteristics can be improved by increasing the contact area between the inner leads and the bumps. Can be improved.

【００１２】また、本発明のリードフレームは、前記接
続固定部が、接続固定用凹部よりなるものである。Further, in the lead frame of the present invention, the connection fixing portion is formed by a connection fixing concave portion.

【００１３】それにより、半導体チップの電極部に設け
られたバンプとインナリードとを確実に直接電気的に接
続することができる。Thus, the bumps provided on the electrode portions of the semiconductor chip and the inner leads can be reliably and directly connected electrically.

【００１４】さらに、本発明のリードフレームは、前記
接続固定用凹部の深さが、５０μｍ以上から前記インナ
リードの半分以下の厚さ程度であり、前記接続固定凹部
の幅が、バンプ径程度よりなるものである。Further, in the lead frame of the present invention, the depth of the connection fixing recess is about 50 μm or more and about half or less of the inner lead, and the width of the connection fixing recess is larger than the bump diameter. It becomes.

【００１５】それにより、半導体チップの電極部に設け
られたバンプとインナリードとをより確実に直接電気的
に接続することができる。Thus, the bumps provided on the electrode portions of the semiconductor chip and the inner leads can be more reliably and directly connected electrically.

【００１６】また、本発明のリードフレームは、前記接
続固定部が、表面が粗化形状よりなるものである。In the lead frame of the present invention, the connection fixing portion has a roughened surface.

【００１７】それによっても、半導体チップの電極部に
設けられたバンプとインナリードとをより確実に直接電
気的に接続することができる。According to this, the bumps provided on the electrode portions of the semiconductor chip and the inner leads can be more reliably directly electrically connected.

【００１８】さらに、本発明の半導体装置は、前記リー
ドフレームを用いて構成され、該リードフレームにおけ
るインナリードの先端部に設けられた接続固定部と半導
体チップの電極部に設けられたバンプとが直接電気的に
接続された構造よりなるものである。Further, the semiconductor device of the present invention is constituted by using the lead frame, wherein the connection fixing portion provided at the tip of the inner lead and the bump provided at the electrode portion of the semiconductor chip in the lead frame. It consists of a structure that is directly electrically connected.

【００１９】それにより、インナリードとバンプとを直
接電気的に接続することができるのでワイヤボンディン
グを不要とすることができ、半導体装置のパッケージを
より薄型化することができる。Accordingly, the inner leads and the bumps can be directly electrically connected, so that wire bonding can be eliminated, and the package of the semiconductor device can be made thinner.

【００２０】また、本発明の半導体装置は、前記バンプ
が、少なくとも二段以上に重ねて設けられた構造よりな
るものである。Further, the semiconductor device according to the present invention has a structure in which the bumps are provided at least in two or more stages.

【００２１】それにより、ボンディング時などに掛かる
応力を緩和することができるので、バンプとインナリー
ドとの電気的接続の信頼性を向上させることができる。Thus, the stress applied during bonding and the like can be reduced, so that the reliability of the electrical connection between the bump and the inner lead can be improved.

【００２２】さらに、本発明の半導体装置の製造方法
は、半導体チップの電極部に設けられたバンプとリード
フレームのインナリードの先端部に設けられたバンプを
接続固定する接続固定部とを直接電気的に接続しながら
半導体チップをリードフレームに接着固定する工程を有
したものである。Further, in the method of manufacturing a semiconductor device according to the present invention, the bump provided on the electrode portion of the semiconductor chip and the connection fixing portion for connecting and fixing the bump provided on the tip of the inner lead of the lead frame are directly electrically connected. And a step of bonding and fixing the semiconductor chip to the lead frame while electrically connecting.

【００２３】それにより、ワイヤボンディング工程が不
要となり半導体装置の製造効率を向上させることができ
る。This eliminates the need for a wire bonding step, thereby improving the manufacturing efficiency of the semiconductor device.

【００２４】以上のことにより、インナリードとバンプ
との電気的接続の信頼性を向上させ、且つ電気的特性を
向上させながら半導体装置のパッケージを薄型化するこ
とができる。As described above, the reliability of the electrical connection between the inner lead and the bump can be improved, and the package of the semiconductor device can be reduced in thickness while improving the electrical characteristics.

【００２５】[0025]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.

【００２６】（実施の形態１）図１は、本発明の実施の
形態１による半導体装置の断面図、図２は、本発明の実
施の形態１による半導体装置の説明図、図３は、本発明
の実施の形態１による接続固定用凹部が設けられたイン
ナリードとバンプとの接続状態を示した説明図、図４
は、本発明の実施の形態１による接続表面が粗化された
インナリードとバンプとの接続状態を示した説明図、図
５は、本発明者が検討したＬＯＣ構造の半導体装置の説
明図、図６は、本発明者が検討したＬＯＣ構造の半導体
装置におけるワイヤボンディングの説明図、図７は、本
発明者が検討したＬＯＣ構造の半導体装置の説明図、図
８は、本発明の実施の形態１による多段重ね方式の半導
体装置の説明図、図９は、本発明の実施の形態１による
多段重ね方式の半導体装置におけるインナリードとバン
プとの接続状態を示した説明図である。(Embodiment 1) FIG. 1 is a sectional view of a semiconductor device according to Embodiment 1 of the present invention, FIG. 2 is an explanatory view of the semiconductor device according to Embodiment 1 of the present invention, and FIG. FIG. 4 is an explanatory view showing a connection state between an inner lead provided with a connection fixing concave portion and a bump according to the first embodiment of the invention, and a bump;
FIG. 5 is an explanatory view showing a connection state between inner leads and bumps having a roughened connection surface according to the first embodiment of the present invention, FIG. 5 is an explanatory view of a semiconductor device having a LOC structure studied by the present inventors, FIG. 6 is an explanatory diagram of wire bonding in a semiconductor device having a LOC structure studied by the present inventors, FIG. 7 is an explanatory diagram of a semiconductor device having a LOC structure studied by the present inventors, and FIG. FIG. 9 is an explanatory diagram of a multi-stage semiconductor device according to the first embodiment. FIG. 9 is an explanatory diagram showing a connection state between inner leads and bumps in the multi-stage semiconductor device according to the first embodiment of the present invention.

【００２７】本実施の形態１において、たとえば、表面
実装形パッケージの一種であるＳＯＪ（Ｓｍａｌｌ Ｏ
ｕｔｌｉｎｅ Ｊ−ｌｅａｄｅｄ Ｐａｃｋａｇｅ）形
の樹脂封止パッケージからなる半導体装置１は、図１に
示すように、半導体チップ２の上方に、たとえば、ポリ
ミイドテープなどの絶縁テープ３を介してリードフレー
ム４が位置するＬＯＣ構造となっており、半導体チップ
２、後述するインナリードが、たとえば、エポキシレジ
ンなどの樹脂体５により封止されている。In Embodiment 1, for example, SOJ (Small O
As shown in FIG. 1, in a semiconductor device 1 composed of a U.S. U-line J-leaded Package type resin-sealed package, a lead frame 4 is located above a semiconductor chip 2 via an insulating tape 3 such as a polyimide tape. It has a LOC structure, and the semiconductor chip 2 and inner leads to be described later are sealed with a resin body 5 such as an epoxy resin.

【００２８】また、ＬＯＣ構造の半導体装置１は、半導
体チップ２の中央部付近には、電極部であるボンディン
グパッドが配置され、これらボンディングパッドの上部
には、たとえば、金（Ａｕ）からなるバンプＢＢが電気
的に接続固定されている。In the semiconductor device 1 having the LOC structure, bonding pads as electrodes are arranged near the center of the semiconductor chip 2, and bumps made of, for example, gold (Au) are provided above these bonding pads. BB is electrically connected and fixed.

【００２９】さらに、リードフレーム４には、図２に示
すように、半導体チップ２のボンディングパッドとバン
プＢＢ（図１）を介して電気的に接続されるインナリー
ド４ａが形成され、これらインナリード４ａの一方の端
部は、ボンディングパッドの上部に位置するように形成
されている。Further, as shown in FIG. 2, inner leads 4a electrically connected to the bonding pads of the semiconductor chip 2 via the bumps BB (FIG. 1) are formed on the lead frame 4, and these inner leads 4a are formed. One end of 4a is formed so as to be located above the bonding pad.

【００３０】また、リードフレーム４は、実装基板とな
るプリント配線基板などの電極部と電気的に接続される
外部引出線であるアウタリード４ｂが設けられており、
これらインナリード４ａおよびアウタリード４ｂによっ
てリードＬが構成されている。The lead frame 4 is provided with outer leads 4b, which are external leads electrically connected to electrode portions of a printed wiring board or the like serving as a mounting board.
A lead L is constituted by the inner lead 4a and the outer lead 4b.

【００３１】また、エポキシレジンなどの樹脂体５によ
り封止された半導体装置１における樹脂体５の対向する
１対の側面から前述したアウタリード４ｂが突出して設
けられており、当該アウタリード４ｂは、Ｊ字状に形成
されている。Further, the above-mentioned outer leads 4b are provided so as to protrude from a pair of opposite side surfaces of the resin body 5 in the semiconductor device 1 sealed with the resin body 5 such as an epoxy resin. It is formed in a character shape.

【００３２】ここで、半導体チップ２のボンディングパ
ッド上に設けられたバンプＢＢと重合するインナリード
４ａの先端部には、図３に示すように、バンプＢＢと同
じ程度の幅で、深さが、５０μｍ程度以上からリードＬ
の厚さの半分程度以下に形成された形状の接続固定用凹
部（接続固定部）４ａ1 が、たとえば、ハーフエッチに
よって形成されている。Here, as shown in FIG. 3, the tip of the inner lead 4a which overlaps with the bump BB provided on the bonding pad of the semiconductor chip 2 has the same width and depth as the bump BB. , Lead L from about 50 μm or more
The thickness of the formed about half or less the shape of the connection fixing recesses (connecting the fixed portion) 4a 1 is, for example, is formed by half etching.

【００３３】そして、このインナリード４ａに設けられ
た接続固定用凹部４ａ1 は、バンプＢＢの上方に設けら
れ、インナリード４ａとバンプＢＢとの接続時には、こ
の接続固定用凹部４ａ1 がバンプＢＢを覆うよう接続さ
れる位置となっている。[0033] Then, the inner lead connecting fixing recess 4a provided in the 4a 1 is provided above the bump BB, at the time of connection of the inner lead 4a and the bumps BB, the connection fixing recess 4a 1 bump BB Is connected so as to cover the.

【００３４】次に、半導体装置１におけるバンプＢＢを
介したボンディングパッドとインナリード４ａとの電気
的な接続方法について説明する。Next, a method of electrically connecting the bonding pads and the inner leads 4a via the bumps BB in the semiconductor device 1 will be described.

【００３５】まず、ダイボンダなどによって各々のボン
ディングパッドにバンプＢＢが仮止めされた半導体チッ
プ２をリードフレーム４の所定の位置に接着されている
絶縁テープ３上に装着し、たとえば、１８０℃程度に加
熱しながら圧着を行う熱圧着方式によって絶縁テープ３
と半導体チップ２を接着固定する。First, a semiconductor chip 2 having bumps BB temporarily fixed to respective bonding pads by a die bonder or the like is mounted on an insulating tape 3 adhered to a predetermined position of a lead frame 4. Insulation tape 3 by thermocompression bonding method that performs compression while heating
And the semiconductor chip 2 are bonded and fixed.

【００３６】また、このダイボンディング時に、同時に
ボンディングパッドの上方に位置しているインナリード
４ａの先端部もダイボンダによって熱圧着を行い、イン
ナリード４ａとバンプＢＢとを電気的に接続し、前述し
たように、インナリード４ａの接続固定用凹部４ａ1 が
バンプＢＢを覆うように確実に固定される。At the same time as the die bonding, the tip of the inner lead 4a located above the bonding pad is also thermocompression-bonded by a die bonder to electrically connect the inner lead 4a and the bump BB. as such, the connection fixing recess 4a 1 of the inner lead 4a is securely fixed to cover the bumps BB.

【００３７】さらに、インナリード４ａの先端部には、
図４に示すように、接続固定用凹部４ａ1 （図３）の代
わりに、たとえば、プレスなどによってディンプルなど
を形成し、バンプＢＢと接触する表面を粗化することに
よって接触面積を大きくした形状の粗化表面（接続固定
部）４ａ2 とし、バンプＢＢとの接触面積を大きくする
ことによっても良好にインナリード４ａとバンプＢＢと
を電気的に接続することができる。Further, at the tip of the inner lead 4a,
As shown in FIG. 4, instead of the connection fixing recess 4a 1 (FIG. 3), for example, a dimple or the like is formed by pressing or the like, and the contact area is increased by roughening the surface in contact with the bump BB. the roughened surface (connecting the fixed portion) 4a 2 and then, a good inner lead 4a and the bumps BB also by increasing the contact area between the bump BB can be electrically connected.

【００３８】次に、本発明者が検討したＳＯＪ形の樹脂
封止パッケージからなるＬＯＣ構造の半導体装置２０
は、図５に示すように、半導体チップ２１の上方に絶縁
テープ２２を介してリードフレーム２３が位置してい
る。Next, the semiconductor device 20 having the LOC structure formed of the SOJ type resin-sealed package examined by the present inventors.
As shown in FIG. 5, a lead frame 23 is located above a semiconductor chip 21 via an insulating tape 22.

【００３９】また、半導体チップ２１の中央部付近に
は、図６に示すように、電極であるボンディングパッド
が配置されており、これらボンディングパッド上には、
たとえば、金からなるバンプ２４が設けられている。As shown in FIG. 6, bonding pads, which are electrodes, are disposed near the center of the semiconductor chip 21.
For example, a bump 24 made of gold is provided.

【００４０】そして、図５に示すように、リードフレー
ムに形成された外部引出線であるリード２３ａとボンデ
ィングパッド上に設けられたバンプ２４とがボンディン
グワイヤ２５によってそれぞれ電気的に接続されてい
る。As shown in FIG. 5, the leads 23a, which are external leads formed on the lead frame, and the bumps 24 provided on the bonding pads are electrically connected by bonding wires 25, respectively.

【００４１】さらに、図７に示すように、半導体チップ
２１、ボンディングワイヤ２５、リード２３ａの一部
が、たとえば、エポキシレジンなどの樹脂体２６により
封止され、この樹脂体２６の対向する１対の側面から突
出しているリード２３ａがＪ字状に形成されている。Further, as shown in FIG. 7, a part of the semiconductor chip 21, the bonding wires 25, and the leads 23a are sealed with a resin body 26 such as an epoxy resin, for example. The lead 23a protruding from the side surface of is formed in a J-shape.

【００４２】ここで、図５に示すように、半導体装置２
０の場合は、ワイヤループ高さにバンプ２４の高さを加
えた樹脂体２６の厚さ、すなわち、パッケージ厚が最低
限必要となるので、明らかに本実施の形態における半導
体装置１のパッケージ厚が、本発明者が検討した半導体
装置２０のパッケージ厚よりも薄く形成できることが分
かる。Here, as shown in FIG.
In the case of 0, the thickness of the resin body 26 obtained by adding the height of the bump 24 to the wire loop height, that is, the minimum package thickness is required. However, it can be seen that the semiconductor device 20 can be formed thinner than the package thickness studied by the present inventors.

【００４３】そして、このダイボンディングが終了する
と、エポキシレジンなどの樹脂によりモールドを行い、
樹脂体５を形成し、リードフレーム４に設けられている
アウタリード４ｂのめっき処理などの所定の処理を行
い、図１に示すように、リード加工機などによって樹脂
体５から突出したアウタリード４ａをＪ字状に切断成形
する。When the die bonding is completed, molding is performed using a resin such as an epoxy resin.
The resin body 5 is formed, a predetermined process such as plating of the outer lead 4b provided on the lead frame 4 is performed, and as shown in FIG. Cut and molded into a letter shape.

【００４４】また、図８に示すように、このＬＯＣ構造
の半導体チップ２を複数個多段に重ねる、いわゆる、多
段重ね方式の半導体装置１ａに用いることにより、より
一層パッケージ厚を薄くすることができる。As shown in FIG. 8, the package thickness can be further reduced by using a semiconductor device 1a of a so-called multi-stage type in which a plurality of semiconductor chips 2 having the LOC structure are stacked in multiple stages. .

【００４５】この半導体装置１ａは、各々の半導体チッ
プ２の上方に絶縁テープを介してリードフレーム４が位
置するＬＯＣ構造となっており、半導体チップ２の中央
部付近には、電極であるボンディングパッドが配置さ
れ、これらボンディングパッドの上部には、金などのバ
ンプＢＢが電気的に接続固定されている。This semiconductor device 1a has a LOC structure in which a lead frame 4 is located above each semiconductor chip 2 via an insulating tape, and a bonding pad as an electrode is provided near the center of the semiconductor chip 2. Are arranged, and a bump BB of gold or the like is electrically connected and fixed above these bonding pads.

【００４６】ここで、各々の半導体装置２は、図９に示
すように、最下段の半導体チップ２の上部に絶縁テープ
３が設けられ、その絶縁テープ３を介して固定されたイ
ンナリード４ａの先端部がバンプＢＢと電気的に接続さ
れている。Here, as shown in FIG. 9, each semiconductor device 2 is provided with an insulating tape 3 above the lowermost semiconductor chip 2, and an inner lead 4 a fixed via the insulating tape 3. The tip is electrically connected to the bump BB.

【００４７】そして、そのインナリード４ａの上部にも
同じく絶縁テープ３が設けられ、その絶縁テープ３を介
して二段目の半導体チップ２が固定され、同じく二段目
の半導体チップ２の上部にも絶縁テープ３が設けられ、
二段目の半導体チップに設けられたバンプＢＢと電気的
に接続されるインナリード４ａが固定されており、各々
の半導体チップ２とインナリード４ａとが絶縁テープ３
を介して所定の段数にリードフレーム４が設けられた半
導体チップ２が重ね合わされた構造となっている。An insulating tape 3 is also provided on the inner lead 4a, and the second-stage semiconductor chip 2 is fixed via the insulating tape 3, and also on the second-stage semiconductor chip 2. Is also provided with an insulating tape 3,
Inner leads 4a that are electrically connected to the bumps BB provided on the second-stage semiconductor chip are fixed, and each semiconductor chip 2 and the inner lead 4a
And the semiconductor chips 2 provided with the lead frames 4 in a predetermined number of stages are overlapped.

【００４８】さらに、リードフレーム４に形成された外
部引出線であるリードＬの一方の端部は、ボンディング
パッドの上部に位置するように形成されており、これら
リードＬとボンディングパッドは、バンプＢＢを介して
それぞれ電気的に接続されている。Further, one end of a lead L, which is an external lead formed on the lead frame 4, is formed so as to be located above a bonding pad, and the lead L and the bonding pad are connected to a bump BB. Are electrically connected to each other.

【００４９】そして、各々のリードフレーム４に設けら
れたリードＬは、最上部に位置するリードフレーム４に
設けられた所定のリードＬと電気的に接続され、外部引
出線として用いられる。The leads L provided on each of the lead frames 4 are electrically connected to predetermined leads L provided on the lead frame 4 located at the uppermost portion, and are used as external leads.

【００５０】また、各々の半導体チップ２、リードＬの
一部は、たとえば、エポキシレジンなどの樹脂体５によ
り封止され、この樹脂体５の対向する１対の側面から前
述した外部引出線となるリードＬが突出して設けられて
おり、当該リードＬは、Ｊ字状に形成されている。A part of each of the semiconductor chips 2 and the leads L is sealed with a resin body 5 such as an epoxy resin, for example. The lead L is provided in a protruding manner, and the lead L is formed in a J-shape.

【００５１】さらに、リードＬの先端部の形状も、同様
にバンプＢＢと同じ程度の幅で、深さが、５０μｍ程度
以上からリードＬの厚さの半分以下程度にハーフエッチ
された形状となっている。Further, the shape of the tip of the lead L is also the same width as the bump BB, and the shape is half-etched from a depth of about 50 μm or more to about a half or less of the thickness of the lead L. ing.

【００５２】また、図１０に示すように、インナリード
４ａの先端部を樹脂体の一方の周辺部近傍に設けられた
絶縁テープ３だけでなく、対向する樹脂体の他方の周辺
部近傍に設けられた絶縁テープ３の上方に位置する長さ
に形成し、インナリード４ａとバンプＢＢと電気的に接
続することによっても、インナリード４ａとバンプＢＢ
との密着性を向上させることができる。As shown in FIG. 10, the tip of the inner lead 4a is provided not only near the insulating tape 3 provided near one peripheral portion of the resin body but also near the other peripheral portion of the facing resin body. The inner leads 4a and the bumps BB can also be formed by forming them in a length located above the insulating tape 3 and electrically connecting the inner leads 4a and the bumps BB.
And the adhesiveness with the adhesive can be improved.

【００５３】それにより、本実施の形態１によれば、イ
ンナリード４ａとバンプＢＢとをダイボンディング時に
直接電気的に接続するので、ボンディングワイヤが不要
となるので樹脂体５の厚さを薄く形成することができ
る。Thus, according to the first embodiment, since the inner leads 4a and the bumps BB are directly electrically connected at the time of die bonding, a bonding wire is not required, so that the thickness of the resin body 5 is reduced. can do.

【００５４】また、本実施の形態１においては、ワイヤ
ボンディングが不要となるので、電気的特性を向上させ
ることができ、半導体装置１の組立コストも少なくする
ことができる。In the first embodiment, since wire bonding is not required, electrical characteristics can be improved, and the cost of assembling the semiconductor device 1 can be reduced.

【００５５】さらに、本実施の形態１では、インナリー
ド４ａの先端部に接続固定用凹部４ａ1 を設けたが、た
とえば、図１１に示すように、インナリード４ａの先端
部を加工せずにバンプＢＢと電気的に接続してもよい。[0055] Further, in the first embodiment is provided with the connection fixing recesses 4a 1 to the distal end of the inner lead 4a, for example, as shown in FIG. 11, without processing the tip of the inner lead 4a It may be electrically connected to the bump BB.

【００５６】（実施の形態２）図１２は、本発明の実施
の形態２による半導体装置におけるインナリードと二段
重ねされたバンプとの接続状態を示した説明図である。(Second Embodiment) FIG. 12 is an explanatory diagram showing a connection state between an inner lead and a two-staged bump in a semiconductor device according to a second embodiment of the present invention.

【００５７】本実施の形態２においては、ＬＯＣ構造の
半導体装置１においては、図１２に示すように、インナ
リード４ａと電気的に接続されるボンディングパッドの
上部に設けられたバンプＢＢが二段重ねとなって形成さ
れている。In the second embodiment, in the semiconductor device 1 having the LOC structure, as shown in FIG. 12, two bumps BB provided above the bonding pads electrically connected to the inner leads 4a are provided. They are formed in layers.

【００５８】また、二段重ねとなったバンプＢＢと電気
的に接続されるインナリード４ａの先端部は前記実施の
形態１と同様に、バンプＢＢと同じ程度の幅で、深さ
が、５０μｍ以上からリードＬの厚さの半分以下程度の
接続固定用凹部４ａ1 が、たとえば、ハーフエッチによ
って形成されている。Further, as in the first embodiment, the tip of the inner lead 4a electrically connected to the two-tiered bump BB has the same width as the bump BB and a depth of 50 μm. connection fixing recesses 4a 1 half degree or less of the thickness of the lead L from the above, for example, it is formed by half etching.

【００５９】さらに、このインナリード４ａに設けられ
た接続固定用凹部４ａ1 は、バンプＢＢの上方に設けら
れ、インナリード４ａとバンプＢＢとの接続時には、こ
の接続固定用凹部４ａ1 が上段に位置するバンプＢＢを
覆うよう接続される位置となっている。[0059] Furthermore, the connection fixing recess 4a 1 provided for this inner lead 4a, is provided above the bump BB, at the time of connection of the inner lead 4a and the bumps BB, the connection fixing recess 4a 1 is in the upper It is a position where it is connected so as to cover the located bump BB.

【００６０】そして、ダイボンダなどによって各々のボ
ンディングパッドに二段重ねされたバンプＢＢが仮止め
された半導体チップ２をリードフレーム４の所定の位置
に接着されている絶縁テープ３上に装着し、たとえば、
１８０℃程度に加熱しながら圧着を行う熱圧着方式によ
って絶縁テープ３と半導体チップ２を接着固定する。Then, the semiconductor chip 2 to which the bumps BB superimposed on the respective bonding pads in two steps are temporarily fixed by a die bonder or the like is mounted on the insulating tape 3 adhered to a predetermined position of the lead frame 4. ,
The insulating tape 3 and the semiconductor chip 2 are bonded and fixed by a thermocompression bonding method of performing compression while heating to about 180 ° C.

【００６１】その後、ダイボンディングが終了すると、
同様にエポキシレジンなどの樹脂によりモールドを行
い、樹脂体５を形成し、リードフレーム４に設けられて
いるアウタリード４ｂのめっき処理などの所定の処理を
行い、リード加工機などによって樹脂体５から突出した
アウタリード４ｂをＪ字状に切断成形する。After that, when the die bonding is completed,
Similarly, molding is performed with a resin such as an epoxy resin to form a resin body 5, predetermined processing such as plating of outer leads 4 b provided on the lead frame 4 is performed, and the resin body 5 is protruded from the resin body 5 by a lead processing machine or the like. The formed outer lead 4b is cut and formed into a J-shape.

【００６２】それにより、本実施の形態２によれば、接
合時の熱応力などを吸収することができ、バンプＢＢの
応力を緩和し、電気的接続の信頼性を向上させることが
できる。Thus, according to the second embodiment, the thermal stress and the like at the time of joining can be absorbed, the stress of the bump BB can be reduced, and the reliability of the electrical connection can be improved.

【００６３】また、本実施の形態２では、バンプＢＢを
二段重ねとしたが、二段以上の多段にバンプＢＢを形成
することによって良好に接合時の熱応力などを吸収する
ことができ、バンプＢＢの応力を緩和し、電気的接続の
信頼性を向上させることができる。In the second embodiment, the bumps BB are stacked in two stages. However, by forming the bumps BB in two or more stages, it is possible to favorably absorb thermal stress and the like at the time of joining. The stress of the bump BB can be reduced, and the reliability of the electrical connection can be improved.

【００６４】さらに、二段重ねとなったバンプＢＢと電
気的に接続されるインナリード４ａの先端部に、図１３
に示すように、ハーフエッチなどの加工を施さずにバン
プＢＢと電気的接続を行うようにしても良好に接続固定
を行うことができる。Further, the tip of the inner lead 4a electrically connected to the two-stage stacked bumps BB is
As shown in (2), even if electrical connection with the bump BB is performed without performing processing such as half-etching, the connection can be satisfactorily fixed.

【００６５】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることはいうまでも
ない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

【００６６】[0066]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

【００６７】（１）本発明によれば、インナリードの接
続固定部を設けたことにより位置合わせ精度が向上し、
インナリードとバンプとを確実に直接電気的に接続でき
るのでワイヤボンディングが不要となり、且つ電気的特
性を向上させることができる。(1) According to the present invention, the positioning accuracy is improved by providing the connection fixing portion of the inner lead.
Since the inner leads and the bumps can be reliably electrically connected directly, wire bonding becomes unnecessary, and electrical characteristics can be improved.

【００６８】（２）また、本発明では、インナリードと
バンプとを直接電気的に接続することができるのでワイ
ヤボンディングを不要とすることができ、半導体装置の
パッケージをより薄型化することができる。(2) Further, according to the present invention, since the inner leads and the bumps can be directly electrically connected, wire bonding can be omitted, and the package of the semiconductor device can be made thinner. .

【００６９】（３）さらに、本発明においては、バンプ
が、少なくとも二段以上に重ねて設けることにより、バ
ンプとインナリードとの電気的接続の信頼性を向上させ
ることができる。(3) Further, in the present invention, the reliability of the electrical connection between the bump and the inner lead can be improved by providing the bump in at least two layers.

【００７０】（４）本発明によれば、上記（１）〜
（３）により、インナリードとバンプとの電気的接続の
信頼性を向上ならびに半導体装置の製造効率を向上させ
ることができる。(4) According to the present invention, the above (1) to (5)
According to (3), the reliability of the electrical connection between the inner lead and the bump can be improved, and the manufacturing efficiency of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態１による半導体装置の断面
図である。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;

【図２】本発明の実施の形態１による半導体装置の説明
図である。FIG. 2 is an explanatory diagram of the semiconductor device according to the first embodiment of the present invention;

【図３】本発明の実施の形態１による接続固定用凹部が
設けられたインナリードとバンプとの接続状態を示した
説明図である。FIG. 3 is an explanatory diagram showing a connection state between an inner lead provided with a connection fixing concave portion and a bump according to the first embodiment of the present invention.

【図４】本発明の実施の形態１による接続表面が粗化さ
れたインナリードとバンプとの接続状態を示した説明図
である。FIG. 4 is an explanatory diagram showing a connection state between inner leads and bumps whose connection surfaces are roughened according to the first embodiment of the present invention.

【図５】本発明者が検討したＬＯＣ構造の半導体装置の
説明図である。FIG. 5 is an explanatory diagram of a semiconductor device having a LOC structure studied by the present inventors.

【図６】本発明者が検討したＬＯＣ構造の半導体装置に
おけるワイヤボンディングの説明図である。FIG. 6 is an explanatory diagram of wire bonding in a semiconductor device having a LOC structure studied by the present inventors.

【図７】本発明者が検討したＬＯＣ構造の半導体装置の
説明図である。FIG. 7 is an explanatory diagram of a semiconductor device having a LOC structure studied by the present inventors.

【図８】本発明の実施の形態１による多段重ね方式の半
導体装置の説明図である。FIG. 8 is an explanatory diagram of a multi-stage semiconductor device according to the first embodiment of the present invention;

【図９】本発明の実施の形態１による多段重ね方式の半
導体装置におけるインナリードとバンプとの接続状態を
示した説明図である。FIG. 9 is an explanatory diagram showing a connection state between inner leads and bumps in the multi-stage semiconductor device according to the first embodiment of the present invention;

【図１０】本発明の他の実施の形態によるインナリード
とバンプとの接続状態を示した説明図である。FIG. 10 is an explanatory diagram showing a connection state between an inner lead and a bump according to another embodiment of the present invention.

【図１１】本発明の他の実施の形態によるインナリード
とバンプとの接続状態を示した説明図である。FIG. 11 is an explanatory diagram showing a connection state between an inner lead and a bump according to another embodiment of the present invention.

【図１２】本発明の実施の形態２による半導体装置にお
けるインナリードと二段重ねされたバンプとの接続状態
を示した説明図である。FIG. 12 is an explanatory diagram showing a connection state between an inner lead and a two-staged bump in a semiconductor device according to a second embodiment of the present invention;

【図１３】本発明の他の実施の形態による半導体装置に
おけるインナリードと二段重ねされたバンプとの接続状
態を示した説明図である。FIG. 13 is an explanatory diagram showing a connection state between an inner lead and a two-staged bump in a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体装置 １ａ 半導体装置 ２ 半導体チップ ３ 絶縁テープ ４ リードフレーム ４ａ インナリード ４ｂ アウタリード ４ａ1 接続固定用凹部（接続固定部） ４ａ2 粗化表面（接続固定部） ５ 樹脂体 ＢＢ バンプ Ｌ リード ２０ 半導体装置 ２１ 半導体チップ ２２ 絶縁テープ ２３ リードフレーム ２３ａ リード ２４ バンプ ２５ ボンディングワイヤ ２６ 樹脂体Reference Signs List 1 semiconductor device 1a semiconductor device 2 semiconductor chip 3 insulating tape 4 lead frame 4a inner lead 4b outer lead 4a 1 connection fixing recess (connection fixing portion) 4a 2 roughened surface (connection fixing portion) 5 resin body BB bump L lead 20 semiconductor Apparatus 21 Semiconductor chip 22 Insulating tape 23 Lead frame 23a Lead 24 Bump 25 Bonding wire 26 Resin body

───────────────────────────────────────────────────── フロントページの続き (72)発明者 三輪 孝志 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Miwa 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 電極部にバンプが設けられた半導体チッ
プの上方にインナリードが位置するリードフレームであ
って、前記インナリードの先端部に、前記バンプを密着
させる接続固定部を設けた構造よりなることを特徴とす
るリードフレーム。1. A lead frame in which an inner lead is located above a semiconductor chip having a bump provided on an electrode portion, wherein a lead fixing portion is provided at a tip end of the inner lead so as to closely contact the bump. A lead frame, comprising: a lead frame; 【請求項２】 請求項１記載のリードフレームにおい
て、前記接続固定部が、接続固定用凹部よりなることを
特徴とするリードフレーム。2. The lead frame according to claim 1, wherein said connection fixing portion comprises a connection fixing concave portion. 【請求項３】 請求項２記載のリードフレームにおい
て、前記接続固定用凹部の幅が、バンプと同じ程度で、
前記接続固定凹部の深さが、５０μｍ以上からリードフ
レームの厚さの半分以下程度よりなることを特徴とする
リードフレーム。3. The lead frame according to claim 2, wherein the width of the connection fixing recess is substantially equal to that of the bump.
The lead frame, wherein the depth of the connection fixing recess is about 50 μm or more and about half or less of the thickness of the lead frame. 【請求項４】 請求項１記載のリードフレームにおい
て、前記接続固定部が、表面が粗化形状であることを特
徴とするリードフレーム。4. The lead frame according to claim 1, wherein the connection fixing portion has a roughened surface. 【請求項５】 請求項１〜４のいずれか１項に記載のリ
ードフレームを用いて構成され、前記リードフレームに
おけるインナリードの先端部に設けられた前記接続固定
部と前記半導体チップの電極部に設けられた前記バンプ
とが直接電気的に接続された構造よりなることを特徴と
する半導体装置。5. An electrode portion of the semiconductor chip, wherein the connection fixing portion is formed using the lead frame according to claim 1 and is provided at a tip portion of an inner lead in the lead frame. A semiconductor device having a structure in which the bumps provided on the substrate are directly electrically connected to each other. 【請求項６】 請求項５記載の半導体装置において、前
記バンプが、少なくとも二段以上に重ねて設けられた構
造よりなることを特徴とする半導体装置。6. The semiconductor device according to claim 5, wherein the bumps have a structure provided at least in two or more stages. 【請求項７】 半導体チップの上方にリードフレームが
位置するＬＯＣ構造の半導体装置の製造方法であって、
前記半導体チップの電極部に設けられたバンプと前記リ
ードフレームのインナリードの先端部に設けられた前記
バンプを接続固定する接続固定部とを直接電気的に接続
しながら前記半導体チップを前記リードフレームに接着
固定する工程を有することを特徴とする半導体装置の製
造方法。7. A method for manufacturing a semiconductor device having a LOC structure in which a lead frame is located above a semiconductor chip,
The semiconductor chip is connected to the lead frame while directly electrically connecting a bump provided on an electrode portion of the semiconductor chip and a connection fixing portion provided for connecting and fixing the bump provided on a tip of an inner lead of the lead frame. A method of manufacturing a semiconductor device, comprising a step of bonding and fixing the semiconductor device to a semiconductor device.
JP8275684A 1996-10-18 1996-10-18 Lead frame, semiconductor device and manufacturing method thereof Pending JPH10125850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8275684A JPH10125850A (en) 1996-10-18 1996-10-18 Lead frame, semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8275684A JPH10125850A (en) 1996-10-18 1996-10-18 Lead frame, semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH10125850A true JPH10125850A (en) 1998-05-15

Family

ID=17558919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8275684A Pending JPH10125850A (en) 1996-10-18 1996-10-18 Lead frame, semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH10125850A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023133A (en) * 2001-07-06 2003-01-24 Matsushita Electric Ind Co Ltd Lead frame, plastic molded type semiconductor device using the same and its manufacturing method
JP2008177618A (en) * 2004-11-11 2008-07-31 Sharp Corp Flexible wiring board, semiconductor device and electronic equipment using the wiring board
US7977805B2 (en) 2004-11-11 2011-07-12 Sharp Kabushiki Kaisha Flexible wiring substrate, semiconductor device and electronic device using flexible wiring substrate, and fabricating method of flexible wiring substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003023133A (en) * 2001-07-06 2003-01-24 Matsushita Electric Ind Co Ltd Lead frame, plastic molded type semiconductor device using the same and its manufacturing method
JP4598316B2 (en) * 2001-07-06 2010-12-15 パナソニック株式会社 Resin-sealed semiconductor device and manufacturing method thereof
JP2008177618A (en) * 2004-11-11 2008-07-31 Sharp Corp Flexible wiring board, semiconductor device and electronic equipment using the wiring board
US7977805B2 (en) 2004-11-11 2011-07-12 Sharp Kabushiki Kaisha Flexible wiring substrate, semiconductor device and electronic device using flexible wiring substrate, and fabricating method of flexible wiring substrate

Similar Documents

Publication Publication Date Title
US5770888A (en) Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
US6528353B2 (en) Chip stack-type semiconductor package and method for fabricating the same
US7084490B2 (en) Leads under chip IC package
US5917242A (en) Combination of semiconductor interconnect
JP4195804B2 (en) Dual die package
JPH1093001A (en) Semiconductor package and manufacture thereof
US6153922A (en) Semiconductor device
JP2007521643A (en) Lead frame with passive device
JPH0444347A (en) Semiconductor device
JPH0722454A (en) Semiconductor integrated circuit device
JP3075617B2 (en) Semiconductor integrated circuit device
JPH10125850A (en) Lead frame, semiconductor device and manufacturing method thereof
JPH1140601A (en) Structure of semiconductor device
JPH10335366A (en) Semiconductor device
JPH0529528A (en) Semiconductor integrated circuit device and lead frame used for same
JP2971594B2 (en) Semiconductor integrated circuit device
JP2001267484A (en) Semiconductor device and manufacturing method thereof
JPH0621305A (en) Semiconductor device
JP2001332684A (en) Resin-sealed semiconductor device and manufacturing method thereof
JP2001015669A (en) Lead frame, resin sealed semiconductor device using the same, and its manufacture
JPH08279575A (en) Semiconductor package
JP2681145B2 (en) Resin-sealed semiconductor device
JP3203209B2 (en) Semiconductor device
JP2536439B2 (en) Lead frame for semiconductor device and resin-sealed semiconductor device using the same
JPH1168015A (en) Lead frame, semiconductor device provided therewith, and manufacture thereof

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term