JPH10124235A - Coordinate input device - Google Patents
Coordinate input deviceInfo
- Publication number
- JPH10124235A JPH10124235A JP29808996A JP29808996A JPH10124235A JP H10124235 A JPH10124235 A JP H10124235A JP 29808996 A JP29808996 A JP 29808996A JP 29808996 A JP29808996 A JP 29808996A JP H10124235 A JPH10124235 A JP H10124235A
- Authority
- JP
- Japan
- Prior art keywords
- resistance layer
- resistance
- input device
- coordinate input
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、入力ペンで位置し
た座標をコンピュ−タに入力する座標入力装置に関す
る。[0001] 1. Field of the Invention [0002] The present invention relates to a coordinate input device for inputting the coordinates of an input pen to a computer.
【０００２】[0002]
【従来の技術】従来の座標入力装置を、図３により説明
する。図３は、従来の、抵抗層を用いた座標入力装置の
要部断面図であり、ポリエチレンテレフタレ−ト等から
なって透明で可撓性のある上基板２１と、透明なガラス
性の下基板２２との対向面に抵抗層２３、２４を印刷等
によって形成し、抵抗層２３、２４間に複数の絶縁性の
ドットスペ−サ２５を設けて両抵抗層２３、２４間を所
定の間隔に隔てている。そして、一方の抵抗層２３の端
部の対向する２辺にはＸ軸電極が設けられ、他方の抵抗
層２４の端部には前記Ｘ軸と直交するＹ軸電極が設けら
れている。そして、可撓性の上基板２１の上面を入力ペ
ン２６で押圧して、上基板２１の抵抗層２３と下基板２
２の抵抗層２４とを接触させ、この接触位置を電気的に
検出するようにしているが、接触位置の検出方法は、図
示しない処理回路により、上下の電極と電極とに交互に
電圧が時分割的に印加し、電圧が印加されいない方の抵
抗層の電極から電圧を検知してそれぞれの方向の位置を
検出するようにしている。2. Description of the Related Art A conventional coordinate input device will be described with reference to FIG. FIG. 3 is a cross-sectional view of a main part of a conventional coordinate input device using a resistive layer. The transparent and flexible upper substrate 21 made of polyethylene terephthalate or the like and the transparent glassy lower substrate are shown. Resistive layers 23 and 24 are formed on the surface facing the substrate 22 by printing or the like, and a plurality of insulating dot spacers 25 are provided between the resistive layers 23 and 24 so that a predetermined interval is provided between the resistive layers 23 and 24. Separated. An X-axis electrode is provided on two opposing sides of one end of the resistance layer 23, and a Y-axis electrode orthogonal to the X-axis is provided on an end of the other resistance layer 24. Then, the upper surface of the flexible upper substrate 21 is pressed by the input pen 26, and the resistance layer 23 of the upper substrate 21 and the lower substrate 2 are pressed.
The second contact layer is in contact with the second resistance layer 24, and the contact position is electrically detected. However, the contact position is detected by a processing circuit (not shown) in which a voltage is alternately applied to the upper and lower electrodes and the electrodes. The voltage is applied in a divided manner, and the voltage is detected from the electrode of the resistive layer to which the voltage is not applied, and the position in each direction is detected.
【０００３】そして、この種の電圧分割方式の座標入力
装置にあっては、抵抗層２３、２４に用いる抵抗材料と
して、高抵抗で透過率（透明度）のよいものが望まれて
いるが、高抵抗と高透過率とを両立させる材料は得難い
ため、目的に応じて材料の選択をしていた。例えば、高
抵抗を重視する場合はＳｎＯ２等を用い、高透過率を重
視する場合はＩＴＯ（酸化インジウム）等を用いるよう
にしている。そして、この場合、抵抗層２３、２４の膜
厚は、ＳｎＯ２を用いる場合は、ほぼ２５０オングスト
ロ−ム、ＩＴＯを用いる場合は、ほぼ１００オングスト
ロ−ムにしていた。この結果、抵抗層２３、２４の面積
抵抗は、ＳｎＯ２を用いた場合で１２００オ−ム、ＩＴ
Ｏを用いた場合でほぼ８００オ−ムを得ていた。In this type of voltage division type coordinate input device, it is desired that the resistance layers 23 and 24 have high resistance and good transmittance (transparency). Since it is difficult to obtain a material satisfying both the resistance and the high transmittance, the material has been selected according to the purpose. For example, when importance is placed on high resistance, SnO2 or the like is used, and when importance is placed on high transmittance, ITO (indium oxide) or the like is used. In this case, the thicknesses of the resistance layers 23 and 24 are approximately 250 angstroms when using SnO2, and approximately 100 angstroms when using ITO. As a result, the sheet resistance of the resistance layers 23 and 24 is 1200 ohms when SnO2 is used,
Almost 800 ohms was obtained when O was used.
【０００４】[0004]
【発明が解決しようとする課題】しかし、昨今、この種
の座標入力装置においては、省電力に対する要求がます
ます強くなっており、そのためには、抵抗層２３、２４
の厚みを薄くすれば抵抗層の面積抵抗を高くすることが
でき、さらに、それによって透明度も高めることができ
るが、例えば、ＩＴＯで１００オングストロ−ム以下の
膜厚にすると抵抗層の形成面の位置による厚みのバラツ
キが抵抗値のバラツキに大きく影響し、入力位置に対す
る正確な電圧を検知出来なくなるという問題があった。
そこで本発明では、面積抵抗がそれほど高くはないが高
透過率のＩＴＯを用いて電極間の抵抗値を高め、これに
よって省電力が可能な座標入力装置を提供することを目
的とする。However, recently, in this type of coordinate input device, there is an increasing demand for power saving, and for that purpose, the resistance layers 23 and 24 are required.
When the thickness of the resistive layer is reduced, the sheet resistance of the resistive layer can be increased, and the transparency can be increased. There is a problem that the variation in thickness depending on the position greatly affects the variation in the resistance value, making it impossible to detect an accurate voltage with respect to the input position.
In view of the above, an object of the present invention is to provide a coordinate input device capable of increasing the resistance between electrodes by using ITO having a low sheet resistance but having a high transmittance, thereby saving power.
【０００５】[0005]
【課題を解決するための手段】上記の課題を解決するた
め、本発明の座標入力装置は、上基板の表面に透明な第
一抵抗層を設けるとともに前記第一抵抗層の両端に第一
電極を設け、下基板の表面に透明な第二抵抗層を設ける
とともに前記第二抵抗層の両端に、前記第一電極間を結
ぶ方向とほぼ直交する方向に第二電極を設け、前記上基
板と前記下基板とを、前記第一抵抗層と前記第二抵抗層
とが対向するように配置し、少なくとも前記第一抵抗層
または前記第二抵抗層に複数の抵抗層除去部を設けた。In order to solve the above-mentioned problems, a coordinate input device according to the present invention is provided with a transparent first resistance layer on the surface of an upper substrate and first electrodes on both ends of the first resistance layer. Is provided, a transparent second resistance layer is provided on the surface of the lower substrate, and both ends of the second resistance layer are provided with second electrodes in a direction substantially orthogonal to a direction connecting the first electrodes, and the upper substrate and The lower substrate was disposed such that the first resistance layer and the second resistance layer faced each other, and a plurality of resistance layer removal portions were provided on at least the first resistance layer or the second resistance layer.
【０００６】また、本発明の座標入力装置は、前記抵抗
層除去部を、前記電極間を結ぶ方向及び前記電極間を結
ぶ方向とほぼ直交する方向に規則的に設けた。Further, in the coordinate input device of the present invention, the resistance layer removing portions are regularly provided in a direction connecting the electrodes and a direction substantially orthogonal to the direction connecting the electrodes.
【０００７】また、本発明の座標入力装置は、前記抵抗
層除去部を六角形、四角形、三角形または円形に形成し
た。Further, in the coordinate input device of the present invention, the resistance layer removing portion is formed in a hexagon, a square, a triangle or a circle.
【０００８】また、本発明の座標入力装置は、前記抵抗
層除去部の幅を０．０１ｍｍ乃至０．３ｍｍとした。Further, in the coordinate input device of the present invention, the width of the resistive layer removing portion is set to 0.01 mm to 0.3 mm.
【０００９】また、本発明の座標入力装置は、前記抵抗
層除去部を０．０２ｍｍ乃至０．４ｍｍのピッチで設け
た。Further, in the coordinate input device of the present invention, the resistive layer removing portions are provided at a pitch of 0.02 mm to 0.4 mm.
【００１０】さらに、本発明の座標入力装置は、前記抵
抗層にＩＴＯを用いた。Further, in the coordinate input device of the present invention, ITO is used for the resistance layer.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態を図１
及び図２に基づいて説明する。ここで、図１は、本発明
の座標入力装置における抵抗層の平面図、図２は本発明
の座標入力装置の要部断面図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
A description will be given based on FIG. Here, FIG. 1 is a plan view of a resistance layer in the coordinate input device of the present invention, and FIG. 2 is a sectional view of a main part of the coordinate input device of the present invention.
【００１２】図１および図２において、上基板１および
下基板２は従来と同様に、それぞれポリエチレンテレフ
タレ−ト等からなる透明なフィルムおよび透明ガラスか
らなり、この上基板１および下基板２の表面にＩＴＯ
（酸化インジュウム）からなる抵抗層３、４が印刷によ
ってほぼ１００オングストロ−ム（０．０１μｍ）の厚
さに形成されている。以下、図１では上基板１について
説明するが下基板２についても上基板１と全く同様であ
る。そして、抵抗層３には、この抵抗層３を、エッチン
グ等によって除去した複数の抵抗層除去部５が、抵抗層
３の両端に設けた電極６、７間方向（Ｘ軸方向）とこの
Ｘ軸方向と直交する方向（Ｙ軸方向）とに沿って所定間
隔で規則的に（例えばマトリックス状に）設けられてい
る。このように、複数の抵抗層除去部５を形成すること
によって、電極６、７間を流れる電流の通路が狭められ
て電極６、７間の抵抗値が高くなるようにしている。ま
た、この抵抗層除去部５を規則的に形成することで電極
６、７間での入力ペンの位置に対する抵抗値が直線的に
なるようにし、さらに、Ｙ軸方向での抵抗値の違いが生
じないようにしている。なお、下基板２の抵抗層４の両
端設ける電極（図示せず）はＹ軸方向に形成されてい
る。1 and 2, the upper substrate 1 and the lower substrate 2 are made of a transparent film and a transparent glass made of polyethylene terephthalate or the like, respectively, as in the prior art. ITO on the surface
The resistance layers 3 and 4 made of (indium oxide) are formed by printing to a thickness of about 100 angstroms (0.01 μm). Hereinafter, the upper substrate 1 will be described with reference to FIG. 1, but the lower substrate 2 is completely the same as the upper substrate 1. The resistance layer 3 is provided with a plurality of resistance layer removal portions 5 obtained by removing the resistance layer 3 by etching or the like. They are provided regularly (for example, in a matrix) at predetermined intervals along a direction orthogonal to the axial direction (Y-axis direction). By forming the plurality of resistance layer removing portions 5 in this manner, the path of the current flowing between the electrodes 6 and 7 is narrowed, and the resistance value between the electrodes 6 and 7 is increased. Further, by forming the resistance layer removing portion 5 regularly, the resistance value between the electrodes 6 and 7 with respect to the position of the input pen becomes linear, and further, the difference in the resistance value in the Y-axis direction is reduced. It does not happen. Note that electrodes (not shown) provided at both ends of the resistance layer 4 of the lower substrate 2 are formed in the Y-axis direction.
【００１３】この抵抗層除去部５は四角形状になってお
り、その大きさ（一辺の長さ）Ｌはおよそ０．０１ｍｍ
乃至０．３ｍｍとなっている。この一辺の長さＬは、入
力ペン８の先端がこの抵抗層除去部５上に位置した際に
も上基板１の抵抗層３が、対向する下基板２上の抵抗層
４（図２参照）と接触するように考慮され、例えば、入
力ペン８の先端の径が０．８ｍｍ（Ｒ＝０．８）程度の
場合、抵抗層２３、２４同士の接触部の径がほぼ０．５
ｍｍ程度になることがわかり、抵抗層除去部５の一辺の
長さＬはそれより小さく０．０１ｍｍ乃至０．３ｍｍに
設定するようにした。また、隣接する抵抗層除去部５間
の間隔、即ち、ピッチＰは、小さくするほど電極６、７
間の抵抗値を高くすることができるが、あまり小さくす
ると入力ペン８のわずかな移動で接触が離れるおそれが
あり、また、あまり大きくすると抵抗値の増加の効果が
なく、およそ０．０２ｍｍ乃至０．４ｍｍにしている。
これによって、抵抗層３、４同士の連続的な接触と抵抗
値の適宜の増加が得られるようにしている。The resistance layer removing portion 5 has a rectangular shape, and its size (length of one side) L is about 0.01 mm.
To 0.3 mm. The length L of this side is such that even when the tip of the input pen 8 is located on the resistance layer removing portion 5, the resistance layer 3 of the upper substrate 1 is opposed to the resistance layer 4 of the lower substrate 2 (see FIG. 2). For example, when the diameter of the tip of the input pen 8 is about 0.8 mm (R = 0.8), the diameter of the contact portion between the resistance layers 23 and 24 is approximately 0.5.
mm, and the length L of one side of the resistance layer removing portion 5 was set to a smaller value, 0.01 mm to 0.3 mm. In addition, the smaller the distance between adjacent resistance layer removing portions 5, that is, the pitch P, the smaller the electrodes 6, 7 are.
However, if the resistance is too small, the contact may be separated by a slight movement of the input pen 8, and if the resistance is too large, there is no effect of increasing the resistance. 0.4 mm.
Thus, continuous contact between the resistance layers 3 and 4 and an appropriate increase in the resistance value can be obtained.
【００１４】このように、抵抗層３、抵抗層除去部５を
形成した上基板１と抵抗層４、抵抗層除去部５を形成し
た下基板２を、図３に示す従来の座標入力装置と同様
に、抵抗層３、４同士が対向するように配置し、互いに
向かい合った上基板１と下基板２間にドットスペ−サ９
を設けて所定の間隔に隔てている。このドットスペ−サ
９は、高さがおよそ０．００４ｍｍ（４μｍ）、径がお
よそ０．０５ｍｍ（５０μｍ）であり、このドットスペ
−サ９がほぼ１ｍｍ間隔でマトリックス状に配列されて
座標入力装置を構成している。As described above, the upper substrate 1 on which the resistance layer 3 and the resistance layer removal part 5 are formed and the lower substrate 2 on which the resistance layer 4 and the resistance layer removal part 5 are formed are combined with the conventional coordinate input device shown in FIG. Similarly, the resistor layers 3 and 4 are arranged so as to face each other, and a dot spacer 9 is provided between the upper substrate 1 and the lower substrate 2 facing each other.
Are provided at predetermined intervals. The dot spacer 9 has a height of approximately 0.004 mm (4 μm) and a diameter of approximately 0.05 mm (50 μm). The dot spacers 9 are arranged in a matrix at intervals of approximately 1 mm to provide a coordinate input device. Make up.
【００１５】このように構成した本発明の座標入力装置
において、電極６、７間の抵抗値を測定した結果によれ
ば、抵抗層３あるいは４の全体での等価的な面積抵抗
は、従来の８００オ−ムに対して２．５倍の２Ｋオ−ム
を達成することが出来た。これによって電極６、７間で
消費される電力を少なくすることができた。また、抵抗
層３、４にＩＴＯを用いていることから抵抗層３、４の
透過率を損なうこともない。According to the coordinate input device of the present invention configured as described above, according to the measurement result of the resistance value between the electrodes 6 and 7, the equivalent sheet resistance of the entire resistive layer 3 or 4 is equal to that of the conventional device. 2K ohms, 2.5 times that of 800 ohms, could be achieved. As a result, the power consumed between the electrodes 6 and 7 could be reduced. Further, since the resistance layers 3 and 4 are made of ITO, the transmittance of the resistance layers 3 and 4 is not impaired.
【００１６】以上の実施の形態では、抵抗層除去部５は
上基板１と下基板２の双方に形成しているが、座標入力
装置として必ずしも双方に形成する必要は無く、この座
標入力装置が接続される処理回路との関係でいずれか一
方に形成したものであってもよい。また、抵抗層除去部
５の形状も、四角形に形成することで説明したが、四角
形に限ることはなく、六角形、三角形あるいは円形であ
ってもよい。このような単純な形状にすることでエッチ
ングで形成した抵抗層除去部５の形状が均一にすること
ができ、従って、抵抗層除去部５おける抵抗層３、４同
士の接触が均一に保たれる。In the above embodiment, the resistance layer removing portion 5 is formed on both the upper substrate 1 and the lower substrate 2, but it is not always necessary to form the coordinate input device on both of them. It may be formed on any one of them in relation to the processing circuit to be connected. Also, the shape of the resistance layer removing portion 5 has been described as being formed in a quadrangle, but is not limited to a quadrangle, and may be a hexagon, a triangle, or a circle. With such a simple shape, the shape of the resistance layer removing portion 5 formed by etching can be made uniform, so that the contact between the resistance layers 3 and 4 in the resistance layer removing portion 5 is kept uniform. It is.
【００１７】[0017]
【発明の効果】以上説明したように、少なくとも第一抵
抗層または第二抵抗層に複数の抵抗層除去部を設けたの
で、抵抗層を流れる電流の通路が狭くなることから電極
間の抵抗値が高くなり、これによって電流を少なくする
ことができ、座標入力装置の省電力化が図れる。As described above, since a plurality of resistance layer removing portions are provided in at least the first resistance layer or the second resistance layer, the path of the current flowing through the resistance layer is narrowed, so that the resistance value between the electrodes is reduced. And the current can be reduced, and the power consumption of the coordinate input device can be reduced.
【００１８】また、本発明の座標入力装置は、抵抗層除
去部を、電極間を結ぶ方向及びこの電極間を結ぶ方向と
ほぼ直交する方向に規則的に設けたので、電極間での入
力ペンの位置に対する抵抗の値が直線的にすることがで
き、さらに、電極間方向と直交する方向での抵抗の違い
が生じないようにできる。Further, in the coordinate input device of the present invention, since the resistance layer removing portion is regularly provided in a direction connecting the electrodes and in a direction substantially orthogonal to the direction connecting the electrodes, the input pen between the electrodes is provided. Can be made linear, and furthermore, it is possible to prevent a difference in resistance in a direction perpendicular to the inter-electrode direction.
【００１９】また、本発明の座標入力装置は、抵抗層除
去部を六角形、四角形、三角形または円形に形成するよ
うにしたので、この抵抗層除去部の形状は単純となり、
従って、エッチングで形成した場合の抵抗層除去部の形
状が均一にすることができ、抵抗層除去部における抵抗
層同士の接触が均一に保たれる。Further, in the coordinate input device of the present invention, the resistance layer removing portion is formed in a hexagon, a quadrangle, a triangle, or a circle, so that the shape of the resistance layer removing portion becomes simple.
Therefore, the shape of the resistance layer removed portion when formed by etching can be made uniform, and the contact between the resistance layers in the resistance layer removed portion can be kept uniform.
【００２０】また、本発明の座標入力装置は、抵抗層除
去部の幅を０．０１ｍｍ乃至０．３ｍｍとしたので、入
力ペンが抵抗層除去部上に位置したときでも抵抗層同士
を確実に接触させることができる。Further, in the coordinate input device of the present invention, since the width of the resistive layer removing portion is set to 0.01 mm to 0.3 mm, even if the input pen is positioned on the resistive layer removing portion, the resistive layers can be securely connected to each other. Can be contacted.
【００２１】また、本発明の座標入力装置は、抵抗層除
去部を０．０２ｍｍ乃至０．４ｍｍのピッチで設けたの
で、入力ペンが隣接する抵抗層除去部間に位置したとき
でも抵抗層同士の接触が離れるおそれがなく、これによ
って、抵抗層同士の連続的な接触と抵抗値の適宜の増加
が得られるようなる。Further, in the coordinate input device of the present invention, since the resistive layer removing portions are provided at a pitch of 0.02 mm to 0.4 mm, even when the input pen is located between adjacent resistive layer removing portions, the resistive layer removing portions are formed. There is no danger of the contacts being separated from each other, whereby continuous contact between the resistance layers and an appropriate increase in the resistance value can be obtained.
【００２２】さらに、本発明の座標入力装置は、抵抗層
にＩＴＯを用いたので、ＩＴＯの持つ高透過率の特徴を
生かしたまま、エッチングによって簡単に抵抗層除去部
を形成することで省電力化が図れる。Further, since the coordinate input device of the present invention uses ITO for the resistive layer, power saving can be achieved by forming the resistive layer removed portion by etching easily while taking advantage of the high transmittance characteristic of ITO. Can be achieved.
【図１】本発明の座標入力装置における抵抗層の平面図
である。FIG. 1 is a plan view of a resistive layer in a coordinate input device according to the present invention.
【図２】本発明の座標入力装置の要部断面図である。FIG. 2 is a sectional view of a main part of the coordinate input device of the present invention.
【図３】従来の座標入力装置の要部断面図である。FIG. 3 is a sectional view of a main part of a conventional coordinate input device.
１ 上基板 ２ 下基板 ３．４ 抵抗層 ５ 抵抗層除去部 ６．７ 電極 ８ 入力ペン ９ ドットスペ−サ Ｌ 抵抗層除去部の長さ Ｐ 抵抗層除去部のピッチ Reference Signs List 1 upper substrate 2 lower substrate 3.4 resistive layer 5 resistive layer removing portion 6.7 electrode 8 input pen 9 dot spacer L length of resistive layer removing portion P pitch of resistive layer removing portion
Claims (6)
るとともに前記第一抵抗層の両端に第一電極を設け、下
基板の表面に透明な第二抵抗層を設けるとともに前記第
二抵抗層の両端に、前記第一電極間を結ぶ方向とほぼ直
交する方向に第二電極を設け、前記上基板と前記下基板
とを、前記第一抵抗層と前記第二抵抗層とが対向するよ
うに配置し、少なくとも前記第一抵抗層または前記第二
抵抗層に複数の抵抗層除去部を設けたことを特徴とする
座標入力装置。A transparent first resistance layer is provided on a surface of an upper substrate, first electrodes are provided at both ends of the first resistance layer, and a transparent second resistance layer is provided on a surface of a lower substrate. At both ends of the resistance layer, a second electrode is provided in a direction substantially orthogonal to a direction connecting the first electrodes, and the upper substrate and the lower substrate are opposed to each other, and the first resistance layer and the second resistance layer face each other. A coordinate input device, wherein a plurality of resistance layer removing portions are provided on at least the first resistance layer or the second resistance layer.
方向及び前記電極間を結ぶ方向とほぼ直交する方向に規
則的に設けたことを特徴とする請求項１記載の座標入力
装置。2. The coordinate input device according to claim 1, wherein said resistance layer removing portion is provided regularly in a direction connecting said electrodes and a direction substantially orthogonal to a direction connecting said electrodes.
角形または円形に形成したことを特徴とする請求項１ま
たは２記載の座標入力装置。3. The coordinate input device according to claim 1, wherein said resistance layer removing portion is formed in a hexagon, a square, a triangle, or a circle.
至０．３ｍｍとしたことを特徴とする請求項１、２また
は３記載の座標入力装置。4. The coordinate input device according to claim 1, wherein the width of the resistance layer removing portion is 0.01 mm to 0.3 mm.
０．４ｍｍのピッチで設けたことを特徴とする請求項４
載の座標入力装置。5. The device according to claim 4, wherein said resistance layer removing portions are provided at a pitch of 0.02 mm to 0.4 mm.
On-board coordinate input device.
とする請求項１、２、３、４または５記載の座標入力装
置。6. The coordinate input device according to claim 1, wherein ITO is used for said resistance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29808996A JPH10124235A (en) | 1996-10-23 | 1996-10-23 | Coordinate input device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29808996A JPH10124235A (en) | 1996-10-23 | 1996-10-23 | Coordinate input device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10124235A true JPH10124235A (en) | 1998-05-15 |
Family
ID=17855029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29808996A Withdrawn JPH10124235A (en) | 1996-10-23 | 1996-10-23 | Coordinate input device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10124235A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001154791A (en) * | 1999-10-18 | 2001-06-08 | Samsung Sdi Co Ltd | Touch panel |
| JP2010009096A (en) * | 2008-06-24 | 2010-01-14 | Epson Imaging Devices Corp | Input device and display with input function |
-
1996
- 1996-10-23 JP JP29808996A patent/JPH10124235A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001154791A (en) * | 1999-10-18 | 2001-06-08 | Samsung Sdi Co Ltd | Touch panel |
| JP4700797B2 (en) * | 1999-10-18 | 2011-06-15 | 三星モバイルディスプレイ株式會社 | Touch panel |
| JP2010009096A (en) * | 2008-06-24 | 2010-01-14 | Epson Imaging Devices Corp | Input device and display with input function |
| JP4636128B2 (en) * | 2008-06-24 | 2011-02-23 | ソニー株式会社 | Input device and display device with input function |
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