JPH1010185A - Go/no go decision method for package arranged with electrode on one side and lead pin/pattern on opposite side using in-circuit tester, and resistor rod - Google Patents
Go/no go decision method for package arranged with electrode on one side and lead pin/pattern on opposite side using in-circuit tester, and resistor rodInfo
- Publication number
- JPH1010185A JPH1010185A JP8181469A JP18146996A JPH1010185A JP H1010185 A JPH1010185 A JP H1010185A JP 8181469 A JP8181469 A JP 8181469A JP 18146996 A JP18146996 A JP 18146996A JP H1010185 A JPH1010185 A JP H1010185A
- Authority
- JP
- Japan
- Prior art keywords
- lead pin
- pattern
- pin
- lead
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measuring Leads Or Probes (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はインサーキットテス
タを用いて行なうPGA型半導体パッケージ、液晶パッ
ケージ等の一面電極、反対面リードピン・パターン配置
型パッケージの良否判定方法並びに抵抗棒に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for judging pass / fail of a single-sided electrode such as a PGA type semiconductor package, a liquid crystal package and the like, and a lead pin / pattern arrangement type package, and a resistance bar using an in-circuit tester.
【0002】[0002]
【従来の技術】従来、実装基板即ち多数の電子部品等を
装着し、半田付けしたプリント基板はインサーキットテ
スタを用いて、その基板の必要な測定点に適宜プローブ
の先端を接触させ、それ等の各部品の有無を電気的に検
出し、或いは各部品の特性値等を電気的に測定して基板
の良否の判定を行っている。この種のインサーキットテ
スタには被検査基板を載せる測定台上に検査治具たるフ
ィクスチュアー(ピンボード)を設置するピンボード方
式のものと、被検査基板を載せる測定台上にX−Yユニ
ット等を設置するX−Y方式のものとがある。2. Description of the Related Art Conventionally, a mounting board, that is, a printed circuit board on which a large number of electronic components are mounted and soldered, uses an in-circuit tester to appropriately contact the tip of a probe to a required measurement point on the board. The presence or absence of each component is electrically detected, or the characteristic value or the like of each component is electrically measured to determine the quality of the board. This type of in-circuit tester includes a pin board type in which a fixture (pin board) as an inspection jig is installed on a measuring table on which a substrate to be inspected is mounted, and an XY on a measuring table on which the substrate to be inspected is mounted. There is an XY type in which units and the like are installed.
【0003】そして、ピンボード方式ではボードに被検
査基板の測定点の数に等しい数のピンプローブを測定点
の位置に対応させて設け、被検査基板の上にフィクスチ
ュアーを載せることにより、各ピンプローブを各測定点
にそれぞれ接触する。一方、X−Y方式ではX軸方向に
可動するアームの上にY軸方向に可動するZ軸ユニット
を備え、そのZ軸ユニットで1本のピンプローブをZ軸
方向に可動可能に支持し、X−Yユニットを制御するこ
とにより、そのピンプローブを基板の上方からX軸、Y
軸、Z軸方向にそれぞれ適宜移動して、予め設定した各
測定点に順次接触する。それ故、ピンボード方式のもの
は多量の同一被検査基板の測定に適するのに対し、X−
Y方式のものは多品種少量の被検査基板の測定に適す
る。In the pin board method, a number of pin probes equal to the number of measurement points on the board to be inspected are provided on the board in correspondence with the positions of the measurement points, and a fixture is mounted on the board to be inspected. Each pin probe is brought into contact with each measurement point. On the other hand, in the XY method, a Z-axis unit movable in the Y-axis direction is provided on an arm movable in the X-axis direction, and one pin probe is movably supported in the Z-axis direction by the Z-axis unit. By controlling the XY unit, the pin probe is moved from above the substrate to the X-axis and Y-axis.
It moves appropriately in the directions of the axis and the Z-axis, and sequentially comes into contact with preset measurement points. Therefore, the pin-board type is suitable for measuring a large number of the same substrates to be inspected, while the X-
The Y type is suitable for measuring a large number of products and a small number of substrates to be inspected.
【0004】これ等の方式によるインサーキットテスタ
を用いて、図4、5に示すような上面にグランド又は電
源電極10を設け、下面の周辺部に多数のリードピン1
2を分散配置し、更に中央部に各パターン列14を方形
状に並べて2組配置して設け、それ等の各リードピン1
2と各パターン16をほぼ1対1に接続したパッケー
ジ、例えばPGA型半導体パッケージ18の良否を判定
する場合、各パターン16毎にグランド電極10と各パ
ターン16の間の静電容量をそれぞれ測定し、その結果
を良品の対応する静電容量とそれぞれ比較することによ
って、そのPGA型半導体パッケージ18の良否の判定
を行なっている。因みに、各パターン16の大部分はセ
ラミック等の材料中に埋設されており、それ等の形状、
厚み、グランド電極10との距離等は不明である。Using an in-circuit tester according to these methods, a ground or power supply electrode 10 is provided on the upper surface as shown in FIGS.
2 are arranged in a distributed manner, and two sets of the pattern rows 14 are further arranged in the center in a rectangular shape.
In the case of determining the quality of a package in which the second and each pattern 16 are connected substantially one-to-one, for example, a PGA type semiconductor package 18, the capacitance between the ground electrode 10 and each pattern 16 is measured for each pattern 16. Then, the quality of the PGA type semiconductor package 18 is determined by comparing the result with the corresponding capacitance of a non-defective product. Incidentally, most of each pattern 16 is buried in a material such as a ceramic, and the shape,
The thickness, the distance from the ground electrode 10, and the like are unknown.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うなPGA型半導体パッケージ18では各パターン列1
4を構成する各パターン16がファインピッチで並んで
いるため、測定用ピンプローブを各パターン16に接触
させる際、高精度の位置決めを必要とするので問題があ
る。しかも、リードピン12と対応するパターン16と
の接続が切断している場合、そのチェックは難しい。何
故なら、リードピン12とパターン16との接続がリー
ドピン12の近くで切断していると、他に問題がなけれ
ば、測定した静電容量を良品のものと比較しても余り変
化がでないからである。なお、X−Y方式インサーキッ
トテスタによって測定を行なうと、各パターン16に測
定用ピンプローブを順次接触させながら移動して各静電
容量の測定を行なうため、当然検査時間が長くなる。However, in such a PGA type semiconductor package 18, each pattern row 1
Since the patterns 16 constituting the pattern 4 are arranged at a fine pitch, there is a problem in that when the measuring pin probe is brought into contact with each pattern 16, high-precision positioning is required. Moreover, when the connection between the lead pin 12 and the corresponding pattern 16 is disconnected, it is difficult to check the connection. This is because if the connection between the lead pin 12 and the pattern 16 is cut near the lead pin 12, if there is no other problem, there is not much change even if the measured capacitance is compared with a good one. is there. When the measurement is performed by the XY system in-circuit tester, the measurement pin probes are sequentially moved while being in contact with the respective patterns 16, and the respective capacitances are measured, so that the inspection time naturally increases.
【0006】本発明はこのような従来の問題点に着目し
てなされたものであり、第1にパターンのファインピッ
チに対応し易く、測定用ピンプローブの位置決めが容易
で、リードピンと対応するパターンとの導通チェックを
簡単に行なうことができる、検査時間の短縮化が可能な
一面電極、反対面リードピン・パターン配置型パッケー
ジのインサーキットテスタによる良否判定方法を提供す
ることを目的とする。又、第2に一面電極、反対面リー
ドピン・パターン配置型パッケージのインサーキットテ
スタによる良否判定方法に使用するのに好適な抵抗棒を
提供することを目的とする。The present invention has been made in view of such conventional problems. First, it is easy to cope with the fine pitch of the pattern, the positioning of the measuring pin probe is easy, and the pattern corresponding to the lead pin is used. It is an object of the present invention to provide a pass / fail judgment method using an in-circuit tester for a one-sided electrode and a lead-pin / pattern-arranged-type package on the opposite side, which can easily check the continuity with the one-side electrode and the opposite-side lead pin / pattern arrangement type package. Another object of the present invention is to provide a resistance bar suitable for use in a pass / fail judgment method using an in-circuit tester for a package having a one-sided electrode and a lead pin / pattern arrangement on the opposite side.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明による第1目的対応の一面電極、反対面リー
ドピン・パターン配置型パッケージのインサーキットテ
スタによる良否判定方法では一面に電極を設け、反対面
に多数のリードピンとパターン列を配設し、それ等の各
リードピンと各パターンとをほぼ1対1に接続してなる
パッケージの静電容量をインサーキットテスタによって
測定し、その測定結果からパッケージの良品を判定す
る。In order to achieve the above-mentioned object, an electrode is provided on one surface of a single-sided electrode according to the first object of the present invention, and a pass / fail judgment method using an in-circuit tester of a package having a lead pin / pattern arrangement type on the opposite side. A large number of lead pins and a pattern row are arranged on the opposite surface, and each lead pin and each pattern are connected almost one-to-one. The capacitance of the package is measured by an in-circuit tester, and the measurement result is obtained. The non-defective product of the package is determined from.
【0008】その際、パターン列を構成する各パターン
に接触するように抵抗棒を押し当て、その抵抗棒に直流
電流を流し、各リードピンに測定用ピンプローブを接触
して各リードピンの電位をそれぞれ測定し、それ等の各
リードピンと対応するパターン間の導通状態をそれぞれ
チェックし、その抵抗棒に流れる電流を止め、それ等の
各導通チェックにより各リードピンと対応するパターン
の全ての導通を確認した後、各リードピン毎に電極と各
リードピン間の静電容量の測定をそれぞれ行なう。At this time, a resistance bar is pressed so as to come into contact with each pattern constituting the pattern row, a DC current is applied to the resistance bar, and a measuring pin probe is brought into contact with each lead pin to set the potential of each lead pin. Measured, the conduction state between each lead pin and the corresponding pattern was checked, the current flowing through the resistance bar was stopped, and all the conduction of each lead pin and the corresponding pattern were confirmed by each conduction check. Thereafter, the capacitance between the electrode and each lead pin is measured for each lead pin.
【0009】又、第2目的対応の抵抗棒は弾力性を有す
る抵抗率の大きな導電体から構成する。The resistance bar for the second purpose is made of a conductive material having elasticity and high resistivity.
【0010】[0010]
【発明の実施の形態】以下添付図面に基づいて、本発明
の実施の形態を説明する。図1は本発明を適用したピン
ボード方式インサーキットテスタによるPGA型半導体
パッケージの良否判定時における下面側を上に向けた各
パターン列に対する各抵抗棒の配置状態を示す平面図で
ある。図中、20が抵抗棒、22がその両端に直流電圧
を印加する電源である。この抵抗棒20には導電性ゴム
等のような弾力性を有する抵抗率の大きな導電体を用い
る。それ故、後述する各リードピン12の電位測定に好
都合なように抵抗棒20に加える電圧値を大きくして
も、発熱量を小さく押えることができ、検査の対象とな
るPGA型半導体パッケージ18を損傷することがな
い。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view showing an arrangement state of each resistance bar with respect to each pattern row in which a lower surface side is upward at the time of judging pass / fail of a PGA type semiconductor package by a pin board type in-circuit tester to which the present invention is applied. In the figure, reference numeral 20 denotes a resistance rod, and reference numeral 22 denotes a power supply for applying a DC voltage to both ends. The resistance bar 20 is made of a conductive material having elasticity and a high resistivity, such as conductive rubber. Therefore, even if the voltage value applied to the resistance bar 20 is increased so as to be convenient for measuring the potential of each lead pin 12 described later, the calorific value can be kept small, and the PGA type semiconductor package 18 to be inspected is damaged. Never do.
【0011】このようなPGA型半導体パッケージ18
のピンボード方式インサーキットテスタによる良否判定
時には、先ず測定台上にパッケージ18を載せ、その下
面を上に向けて固定する。そして、各パターン列14毎
に対応する抵抗棒20をそれぞれ下降させ、そのパター
ン列14を構成する各パターン16に全て良好に接触す
るようにそれぞれ押し当てる。その後、各抵抗棒20に
直流電流を流す。すると、図2に示すように隣接するパ
ターン16の間がいずれも離れており、間隔Lがあるた
め、隣接するパターン16の間でいずれも電圧降下が生
じ、V=Iρ・L/Aの電位差ができる。但し、ρは抵
抗棒20の抵抗率、Aはその断面積、Iはそこに流れる
電流である。Such a PGA type semiconductor package 18
At the time of pass / fail judgment by the pin board type in-circuit tester, first, the package 18 is placed on a measuring table and the lower surface thereof is fixed upward. Then, the resistance bar 20 corresponding to each pattern row 14 is lowered, and is pressed so as to make good contact with each of the patterns 16 constituting the pattern row 14. Thereafter, a direct current is passed through each resistance bar 20. Then, as shown in FIG. 2, the adjacent patterns 16 are all separated and have an interval L, so that a voltage drop occurs between the adjacent patterns 16 and a potential difference of V = Iρ · L / A. Can be. Here, ρ is the resistivity of the resistance bar 20, A is its cross-sectional area, and I is the current flowing therethrough.
【0012】このようにして、全てのパターン16にそ
れぞれ違った電位を与えておく。そこで、図3に示すよ
うにパッケージ18に対し、その上方から矢印方向にピ
ンボードを下降し、各測定用ピンプローブの先端部24
を対応するリードピン12にそれぞれ押し当てる。する
と、隣接するパターン16の間隔はかなり狭いが、隣接
するリードピン12の間隔は広いので、高精度の位置決
めを必要とせずに、各リードピン12の電位をそれぞれ
測定できる。なお、検査治具としてピンボードのボード
に各抵抗棒20を配置して備え付け、その検査治具をエ
アシリンダのピストンロッドの先端部に取り付ける等す
ると、全ての測定用ピンプローブと抵抗棒20とを同時
に上下動できて好ましくなる。In this way, different potentials are applied to all the patterns 16 in advance. Therefore, as shown in FIG. 3, the pin board is lowered from above to the package 18 in the direction of the arrow, and the tip portion 24 of each measuring pin probe is lowered.
To the corresponding lead pins 12. Then, although the interval between the adjacent patterns 16 is considerably narrow, the interval between the adjacent lead pins 12 is wide, so that the potential of each lead pin 12 can be measured without requiring high-precision positioning. When each of the resistance bars 20 is arranged and provided on a pin board as an inspection jig, and the inspection jig is attached to the tip of the piston rod of the air cylinder, etc., all the pin probes for measurement and the resistance rod 20 are connected. Can be simultaneously moved up and down, which is preferable.
【0013】このような各リードピン12の電位測定時
に、リードピン12と対応するパターン16とが切断し
ていれば、そのリードピン12の電位は当然0になる。
なお、リードピン12と対応するパターン16との切断
はリードピン12の近くで発生し易い。それ故、各リー
ドピン12の電位を測定すれば、各リードピン12と対
応するパターン16の間の導通状態をそれぞれチェック
できる。その後、抵抗棒20に流れる電流を止める。因
みに、PGA型半導体パッケージには通常使用しないリ
ードピンも配設してあり、そのリードピンと接続するパ
ターンを増設可能にしてある。At the time of measuring the potential of each lead pin 12, if the lead pin 12 and the corresponding pattern 16 are disconnected, the potential of the lead pin 12 naturally becomes zero.
The cutting of the lead pin 12 and the corresponding pattern 16 is likely to occur near the lead pin 12. Therefore, if the potential of each lead pin 12 is measured, the conduction state between each lead pin 12 and the corresponding pattern 16 can be checked. Thereafter, the current flowing through the resistance bar 20 is stopped. Incidentally, lead pins which are not normally used are also provided in the PGA type semiconductor package, and the pattern connected to the lead pins can be increased.
【0014】各導通チェックにより各リードピン12と
対応するパターン16とが全て導通していることを確認
した後、パッケージ18のグランド電極10に測定用ピ
ンプローブ(図示なし)を押し当てる。そして、交流電
圧を印加して各リードピン12毎にグランド電極10と
各リードピン12の間の静電容量をそれぞれ測定する。
なお、一度に測定用ピンプローブを全てのリードピン1
2に当てて、各リードピン12の電位の測定と静電容量
の測定を行なえば、いずれも瞬時に検査を行なえるた
め、検査時間を短縮できる。After confirming that all the lead pins 12 and the corresponding patterns 16 are all conducting by each conduction check, a measuring pin probe (not shown) is pressed against the ground electrode 10 of the package 18. Then, an AC voltage is applied, and the capacitance between the ground electrode 10 and each lead pin 12 is measured for each lead pin 12.
Note that the measuring pin probe is connected to all lead pins 1 at a time.
If the measurement of the potential of each lead pin 12 and the measurement of the capacitance are performed in the case of No. 2, the inspection can be performed instantaneously in each case, and the inspection time can be reduced.
【0015】このようにして、グランド電極10と各リ
ードピン12の間の静電容量を測定した後、その測定結
果を良品の対応する静電容量とそれぞれ比較し、検査の
対象となっているPGA型半導体パッケージ18の良否
を判定する。そして、導通状態も良く、静電容量も良け
れば良品と決定する。After measuring the capacitance between the ground electrode 10 and each lead pin 12 in this manner, the measurement result is compared with the corresponding capacitance of a non-defective product, and the PGA to be inspected is measured. The quality of the type semiconductor package 18 is determined. If the conduction state is good and the capacitance is good, it is determined that the product is good.
【0016】なお、上記実施の形態では本発明をPGA
型半導体パッケージに適用する場合について説明した
が、他の一面電極、反対面リードピン・パターン配置型
パッケージであるBGA型半導体パッケージ、液晶パッ
ケージ等についても当然適用できる。又、上記実施の形
態では本発明をピンボード方式インサーキットテスタに
適用した場合について説明したが、X−Y方式インサー
キットテスタにも当然適用することができる。In the above embodiment, the present invention is applied to a PGA.
Although the description has been given of the case where the present invention is applied to a type semiconductor package, the present invention can naturally be applied to another one-sided electrode, a BGA type semiconductor package which is a lead pin / pattern arrangement type package on the opposite side, a liquid crystal package and the like. Further, in the above embodiment, the case where the present invention is applied to the pin board type in-circuit tester has been described. However, the present invention can naturally be applied to the XY type in-circuit tester.
【0017】[0017]
【発明の効果】以上説明した本発明によれば、請求項1
記載の発明では測定用ピンプローブを配置間隔の広いリ
ードピンに接触し、抵抗棒をパターン列を構成する配置
間隔の狭い各パターンに接触するため、測定用ピンプロ
ーブの位置決めが容易となり、パターンのファインピッ
チ化に対応できる。そして、抵抗棒に直流電流を流し、
各リードピンの電位をそれぞれ測定することにより、各
リードピンと対応するパターン間の導通状態をチェック
し、パッケージの切断による不良を検出できる。しか
も、ピンボード方式インサーキットテスタによると、一
度に測定用ピンプローブを全ての測定用ピンプローブに
当てて、各リードピンの電位の測定と静電容量の測定等
を行なえるため、検査時間を短縮できる。According to the present invention described above, claim 1
In the described invention, the measuring pin probe is brought into contact with the lead pins having a large arrangement interval, and the resistance bar is brought into contact with each of the patterns having a small arrangement interval constituting the pattern row. Can handle pitching. Then, a direct current is passed through the resistance bar,
By measuring the potential of each lead pin, the conduction state between each lead pin and the corresponding pattern can be checked, and a defect due to the cutting of the package can be detected. Moreover, according to the pin board type in-circuit tester, the measurement pin probe can be applied to all the measurement pin probes at once, and the measurement of the potential of each lead pin and the measurement of the capacitance can be performed, thereby shortening the inspection time. it can.
【0018】又、請求項2記載の発明では抵抗棒とし
て、弾力性を有する抵抗率の大きな導電体を用いるた
め、その抵抗棒をパターン列を構成する全てのパターン
に良好に接触させることができ、その抵抗棒に印加する
電圧値を大きくして隣接するパターン間の電位差を大き
くし、発熱量を少なく押えることができる。それ故、各
リードピンの電位測定に好都合となり、パッケージを損
傷することがない。According to the second aspect of the present invention, since a conductive material having elasticity and high resistivity is used as the resistance bar, the resistance bar can be brought into good contact with all the patterns constituting the pattern row. By increasing the voltage value applied to the resistance bar to increase the potential difference between adjacent patterns, the amount of generated heat can be reduced. Therefore, it is convenient for measuring the potential of each lead pin, and the package is not damaged.
【図1】本発明を適用したピンボード方式インサーキッ
トテスタによるPGA型半導体パッケージの良否判定時
における下面側を上に向けた各パターン列に対する各抵
抗棒の配置状態を示す平面図である。FIG. 1 is a plan view showing an arrangement state of each resistance bar with respect to each pattern row with a lower surface side facing upward when a PGA type semiconductor package is judged to be good or bad by a pin board type in-circuit tester to which the present invention is applied.
【図2】同PGA型半導体パッケージの良否判定時にお
ける1パターン列に対する1抵抗棒の配置状態を示す拡
大平面図である。FIG. 2 is an enlarged plan view showing an arrangement state of one resistance bar for one pattern row at the time of judging pass / fail of the PGA type semiconductor package.
【図3】同PGA型半導体パッケージの良否判定時にお
けるPGA型半導体パッケージの各リードピンとピンボ
ードに備えた各測定用ピンプローブ先端部との対応関係
を示す側面図である。FIG. 3 is a side view showing a correspondence relationship between each lead pin of the PGA type semiconductor package and a tip end of each measurement pin probe provided on a pin board at the time of judging pass / fail of the PGA type semiconductor package.
【図4】PGA型半導体パッケージの平面図である。FIG. 4 is a plan view of a PGA type semiconductor package.
【図5】PGA型半導体パッケージの底面図である。FIG. 5 is a bottom view of the PGA type semiconductor package.
10…グランド電極 12…リードピン 14…パター
ン列 16…パターン 18…PGA型半導体パッケージ 20…抵抗棒 22
…直流電源 24…測定用ピンプローブ先端部DESCRIPTION OF SYMBOLS 10 ... Ground electrode 12 ... Lead pin 14 ... Pattern row 16 ... Pattern 18 ... PGA type semiconductor package 20 ... Resistance bar 22
... DC power supply 24 ... Measurement pin probe tip
Claims (2)
ドピンとパターン列を配設し、それ等の各リードピンと
各パターンとをほぼ1対1に接続してなるパッケージの
静電容量をインサーキットテスタによって測定し、その
測定結果からパッケージの良否を判定する一面電極、反
対面リードピン・パターン配置型パッケージのインサー
キットテスタによる良否判定方法において、上記パター
ン列を構成する各パターンに接触するように抵抗棒を押
し当て、その抵抗棒に直流電流を流し、各リードピンに
測定用ピンプローブを接触して各リードピンの電位をそ
れぞれ測定し、それ等の各リードピンと対応するパター
ン間の導通状態をそれぞれチェックし、その抵抗棒に流
れる電流を止め、それ等の各導通チェックにより各リー
ドピンと対応するパターンの全ての導通を確認した後、
各リードピン毎に電極と各リードピン間の静電容量をそ
れぞれ測定することを特徴とする一面電極、反対面リー
ドピン・パターン配置型パッケージのインサーキットテ
スタによる良否判定方法。An electrode is provided on one surface, a number of lead pins and a pattern array are provided on the opposite surface, and each of the lead pins and each pattern is connected almost one-to-one to reduce the capacitance of a package. One-sided electrodes are measured by an in-circuit tester, and the quality of the package is determined based on the measurement result. A DC current is applied to the resistance bar, and a measuring pin probe is brought into contact with each lead pin to measure the potential of each lead pin.The conduction state between each lead pin and the corresponding pattern is measured. Check each of them, stop the current flowing through the resistance bar, and check the continuity of each of After checking all continuity of the turn,
A pass / fail judgment method using an in-circuit tester for a one-sided electrode and an opposite-sided lead pin / pattern arrangement type package, wherein a capacitance between an electrode and each lead pin is measured for each lead pin.
らなることを特徴とする抵抗棒。2. A resistance bar comprising an electric conductor having elasticity and high resistivity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8181469A JPH1010185A (en) | 1996-06-21 | 1996-06-21 | Go/no go decision method for package arranged with electrode on one side and lead pin/pattern on opposite side using in-circuit tester, and resistor rod |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8181469A JPH1010185A (en) | 1996-06-21 | 1996-06-21 | Go/no go decision method for package arranged with electrode on one side and lead pin/pattern on opposite side using in-circuit tester, and resistor rod |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1010185A true JPH1010185A (en) | 1998-01-16 |
Family
ID=16101307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8181469A Pending JPH1010185A (en) | 1996-06-21 | 1996-06-21 | Go/no go decision method for package arranged with electrode on one side and lead pin/pattern on opposite side using in-circuit tester, and resistor rod |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1010185A (en) |
-
1996
- 1996-06-21 JP JP8181469A patent/JPH1010185A/en active Pending
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