JPH0982935A - Structure of solid-state image pickup element - Google Patents
Structure of solid-state image pickup elementInfo
- Publication number
- JPH0982935A JPH0982935A JP7258236A JP25823695A JPH0982935A JP H0982935 A JPH0982935 A JP H0982935A JP 7258236 A JP7258236 A JP 7258236A JP 25823695 A JP25823695 A JP 25823695A JP H0982935 A JPH0982935 A JP H0982935A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- charge transfer
- barrier
- solid
- hccd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＣＣＤ固体撮像素子
に係り、特に垂直電荷転送領域ＶＣＣＤと水平電荷転送
領域ＨＣＣＤとのインタフェース部にポテンシャルステ
ップ（PotentialStep）が形成されるようにして、電荷
転送効率を高めた固体撮像素子の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD solid-state image pickup device, and more particularly, a potential step is formed in an interface portion between a vertical charge transfer area VCCD and a horizontal charge transfer area HCCD to improve charge transfer efficiency. The present invention relates to a structure of a solid-state image pickup device having improved characteristics.
【０００２】[0002]
【従来の技術】通常のＣＣＤは、マトリックス状に配列
されて光の信号を電気的な映像信号として出力する複数
個のフォトダイオード領域ＰＤと、前記マトリックス状
に配列されたフォトダイオード領域ＰＤの間に垂直方向
に形成され、各フォトダイオードＰＤから生成された映
像信号電荷を垂直方向に転送する複数の垂直電荷転送領
域ＶＣＣＤと、前記垂直電荷転送領域ＶＣＣＤの一方の
端部側に形成され、垂直電荷転送領域に転送された映像
信号電荷を水平方向に転送する水平電荷転送領域ＨＣＣ
Ｄと、前記水平電荷転送領域ＨＣＣＤの出力端に形成さ
れ、転送された映像信号電荷を検出して電気的な信号と
して出力するセンス増幅器と、を有している。2. Description of the Related Art An ordinary CCD is arranged between a plurality of photodiode regions PD arranged in a matrix and outputting light signals as electric image signals, and the photodiode regions PD arranged in the matrix. A plurality of vertical charge transfer regions VCCDs formed in the vertical direction in which the video signal charges generated from the respective photodiodes PD are transferred in the vertical direction, and are formed on one end side of the vertical charge transfer regions VCCDs. Horizontal charge transfer region HCC for horizontally transferring the video signal charges transferred to the charge transfer region
D, and a sense amplifier that is formed at the output end of the horizontal charge transfer area HCCD and that detects the transferred video signal charge and outputs it as an electrical signal.
【０００３】以下、添付図面を参照して従来の固体撮像
素子についてさらに詳しく説明する。図１（ａ）は従来
のＣＣＤのレイアウト図、図１（ｂ）は従来のＣＣＤの
断面構造及びポテンシャルプロファイルである。まず、
図１（ａ）に示すように、複数個のフォトダイオード領
域ＰＤと、各フォトダイオード領域ＰＤから生成された
映像信号電荷を垂直方向に転送する複数個の垂直電荷転
送領域ＶＣＣＤと、前記垂直電荷転送領域ＶＣＣＤの一
端側に設けらた水平電荷転送領域ＨＣＣＤとを含む基板
上にそれぞれのゲートが次のように構成される。Hereinafter, a conventional solid-state image pickup device will be described in more detail with reference to the accompanying drawings. FIG. 1A is a layout diagram of a conventional CCD, and FIG. 1B is a sectional structure and potential profile of the conventional CCD. First,
As shown in FIG. 1A, a plurality of photodiode regions PD, a plurality of vertical charge transfer regions VCCD for vertically transferring a video signal charge generated from each photodiode region PD, and the vertical charges. Each gate is formed as follows on the substrate including the horizontal charge transfer area HCCD provided on one end side of the transfer area VCCD.
【０００４】垂直電荷転送領域上には各フォトダイオー
ド領域から生成された映像信号電荷を順次垂直方向に転
送するための複数個のゲート１、ゲート２が繰り返し形
成される。この際、ポリゲート１は一側がフォトダイオ
ード領域に重なるように構成されてトランスファゲート
として用いられる。A plurality of gates 1 and 2 for sequentially transferring the video signal charges generated from the photodiode regions in the vertical direction are repeatedly formed on the vertical charge transfer region. At this time, the poly gate 1 is configured so that one side thereof overlaps the photodiode region and is used as a transfer gate.
【０００５】前記垂直電荷転送領域上に形成されたゲー
ト電極１、２は、最初のゲート１にはＶΦ1 、最初のポ
リゲート２にはＶΦ2 、第２のゲート１にはＶΦ3 、第
２ゲート２にはＶΦ4 のクロックが印加されて、順次映
像信号電荷を垂直方向に転送する。つまり、４相クロッ
クで映像信号電荷のトランスファ動作が行われる。The gate electrodes 1 and 2 formed on the vertical charge transfer region have VΦ 1 for the first gate 1, VΦ 2 for the first poly gate 2 , VΦ 3 for the second gate 1 and the second gate electrode 2 , respectively. A clock of VΦ 4 is applied to the gate 2 to sequentially transfer the video signal charges in the vertical direction. That is, the transfer operation of the video signal charges is performed with the 4-phase clock.
【０００６】そして、水平電荷転送領域上には２相クロ
ックで垂直電荷転送領域から転送される映像信号電荷を
電気的な映像信号に変換して出力するセンス増幅器へ転
送するためのゲート３、４が構成される。即ち、水平電
荷転送領域上に形成された複数個のゲート３、４にはＨ
Φ1、ＨΦ2のクロックが交互に印加されて順次映像信号
電荷を転送することになる。On the horizontal charge transfer region, gates 3 and 4 for converting the video signal charges transferred from the vertical charge transfer region with a two-phase clock into an electric video signal and outputting the converted electric charge to a sense amplifier. Is configured. That is, the plurality of gates 3 and 4 formed on the horizontal charge transfer region are H
The clocks of Φ 1 and HΦ 2 are alternately applied to sequentially transfer the video signal charges.
【０００７】前記のように構成された従来の固体撮像素
子は、図１（ｂ）に示すように、それぞれの画素領域で
生成された映像信号電荷がＶΦ1、ＶΦ2、ＶΦ3、ＶΦ4
のクロックによりポテンシャルレベルが変わって垂直方
向に転送され、前記の映像信号電荷はさらにＨΦ1、Ｈ
Φ2のクロックによりフローティングゲート領域に転送
されてセンス増幅器を経てアナログ信号に変換されて出
力される。In the conventional solid-state image pickup device configured as described above, as shown in FIG. 1B, the image signal charges generated in the respective pixel regions are VΦ 1 , VΦ 2 , VΦ 3 , and VΦ 4.
The potential level is changed by the clock of the above and is transferred in the vertical direction, and the video signal charges are further transferred to HΦ 1 , H
It is transferred to the floating gate region by the clock of Φ 2 and is converted into an analog signal through the sense amplifier and output.
【０００８】[0008]
【発明が解決しようとする課題】しかし、前記従来の固
体撮像素子では、垂直電荷転送領域と水平電荷転送領域
とのインタフェース部のオーバーラップするウェルで発
生するポテンシャルバリヤ、ポテンシャルポケット等に
より電荷転送効率が低下するという問題点があった。
尚、Ｈ−Ｖインタフェース部のチャンネルストップ層Ｃ
ＳＴによる狭チャンネル効果により映像信号電荷が効率
的に転送されずに画面上にブラックライン等の欠陥が現
れるという問題があった。However, in the conventional solid-state image pickup device described above, the charge transfer efficiency is increased by the potential barrier and potential pockets generated in the overlapping wells of the interface portion between the vertical charge transfer region and the horizontal charge transfer region. However, there was a problem that
The channel stop layer C of the HV interface section
Due to the narrow channel effect of ST, the image signal charges are not efficiently transferred, and defects such as black lines appear on the screen.
【０００９】本発明は前記従来の固体撮像素子の上記問
題を解決するためのものであって、その目的は電荷転送
効率（ＣＴＥ）を高めた固体撮像素子を提供することに
ある。The present invention is to solve the above-mentioned problems of the conventional solid-state image pickup device, and an object thereof is to provide a solid-state image pickup device having improved charge transfer efficiency (CTE).
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するため
の本発明の固体撮像素子の構造は、垂直電荷転送領域Ｖ
ＣＣＤと水平電荷転送領域ＨＣＣＤとのインタフェース
部に外部のＤＣバイアスにより制御されるバリヤゲート
を配置して、インタフェース部にポテンシャルステップ
を形成されるようにしたことを特徴とする。The structure of the solid-state image pickup device of the present invention for achieving the above object is a vertical charge transfer region V.
It is characterized in that a barrier gate controlled by an external DC bias is arranged in an interface portion between the CCD and the horizontal charge transfer area HCCD so that a potential step is formed in the interface portion.
【００１１】[0011]
【発明の実施の形態】以下、図面を参照して本発明の固
体撮像素子の構造について詳しく説明する。図２（ａ）
は本発明のＣＣＤのレイアウト図、図２（ｂ）は本発明
のＣＣＤの断面構造及びポテンシャルプロファイルであ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the solid-state image pickup device of the present invention will be described in detail below with reference to the drawings. Figure 2 (a)
Is a layout diagram of the CCD of the present invention, and FIG. 2B is a sectional structure and potential profile of the CCD of the present invention.
【００１２】先ず、図２（ａ）に示すように、半導体基
板にマトリックス状に配列されて光の信号を電気的な映
像信号に変換して出力する複数個のフォトダイオード領
域ＰＤと、前記フォトダイオード領域の間に垂直方向に
形成され、上側に繰り返し形成されている複数のゲート
電極２１、２０に印加される４相クロックＶΦ1 、ＶΦ
2、ＶΦ3、ＶΦ4 によりフォトダイオード領域から生成
された電荷を垂直方向に転送する複数の垂直電荷転送領
域ＶＣＣＤと、前記垂直電荷転送領域の一方の端部に形
成され、垂直に方向に転送されてきた映像信号電荷をゲ
ート電極２４、２５に印加される２相クロックＨΦ1、
ＨΦ2により水平方向に転送する水平電荷転送領域ＨＣ
ＣＤと、前記垂直電荷転送領域ＶＣＣＤと水平電荷転送
領域ＨＣＣＤとのインタフェース部にＨΦ1 が印加され
るゲート電極（本発明の実施の形態では垂直電荷転送領
域ＶＣＣＤ上のＶΦ4 が印加される最後端のゲート電極
がオーバーラップされるゲート電極なので、水平電荷転
送領域ＨＣＣＤ上のＨΦ1 が印加されるゲート電極はオ
ーバーラップする電極でなければならない）に一部分が
オーバーラップされ、ＶΦ4 が印加される最後端のゲー
ト電極に水平に隣接して形成され、外部のＤＣバイアス
によりインタフェース部にポテンシャルステップを形成
するバリヤゲートとを有する。First, as shown in FIG. 2A, a plurality of photodiode regions PD arranged in a matrix on a semiconductor substrate for converting a light signal into an electric image signal and outputting the electric image signal, and the photodiode regions PD. Four-phase clocks VΦ 1 and VΦ that are vertically formed between the diode regions and are applied to the plurality of gate electrodes 21 and 20 that are repeatedly formed on the upper side.
2 , a plurality of vertical charge transfer regions VCCD for vertically transferring the charges generated from the photodiode region by VΦ 3 , VΦ 4 , and vertical transfer formed at one end of the vertical charge transfer regions. A two-phase clock HΦ 1 that applies the received video signal charges to the gate electrodes 24 and 25,
Horizontal charge transfer area HC for horizontal transfer by HΦ 2
A gate electrode to which HΦ 1 is applied at the interface between the CD and the vertical charge transfer region VCCD and the horizontal charge transfer region HCCD (in the embodiment of the present invention, VΦ 4 on the vertical charge transfer region VCCD is finally applied). Since the end gate electrodes are overlapped gate electrodes, the gate electrodes on the horizontal charge transfer region HCCD to which HΦ 1 is applied must be overlapped electrodes), and VΦ 4 is applied to them. And a barrier gate that is formed horizontally adjacent to the rearmost gate electrode and that forms a potential step in the interface portion by an external DC bias.
【００１３】前記バリヤゲートは第１のバリヤゲート２
２、第２のバリヤゲート２３の二重ゲート構造である。
そして、前記第１、２のバリヤゲート２２、２３のう
ち、いずれか一つの下側領域にはイオン注入工程により
垂直電荷転送領域ＶＣＣＤと水平電荷転送領域ＨＣＣＤ
との中間ポテンシャルレベルを有するバリヤ層が形成さ
れている。The barrier gate is the first barrier gate 2
2. A double gate structure of the second barrier gate 23.
Then, a vertical charge transfer region VCCD and a horizontal charge transfer region HCCD are formed in a lower region of one of the first and second barrier gates 22 and 23 by an ion implantation process.
And a barrier layer having an intermediate potential level between and.
【００１４】前記構成を有する本発明の固体撮像素子
は、各ゲートの下側のポテンシャルプロファイルが図２
（ｂ）のように形成される。In the solid-state image pickup device of the present invention having the above structure, the potential profile under each gate is as shown in FIG.
It is formed as shown in (b).
【００１５】[0015]
【発明の効果】つまり、水平電荷転送領域ＨＣＣＤと垂
直電荷転送領域ＶＣＣＤとのインタフェース部の下側に
中間レベルのポテンシャルステップが外部ＤＣバイアス
により形成され、Ｈ−Ｖインタフェース部に発生するポ
テンシャルバリヤ又はポテンシャルポケットを除去して
電荷転送効率を良くし、低照度で発生するブラックライ
ンの欠陥を無くす効果がある。That is, a potential barrier of an intermediate level is formed by an external DC bias below the interface portion between the horizontal charge transfer area HCCD and the vertical charge transfer area VCCCD, or a potential barrier generated in the HV interface portion or The potential pockets are removed to improve the charge transfer efficiency and to eliminate the black line defects generated at low illuminance.
【図１】 （ａ）は従来のＣＣＤのレイアウト図、
（ｂ）は従来のＣＣＤの断面構造及びポテンシャルプロ
ファイルである。1A is a layout diagram of a conventional CCD, FIG.
(B) is a cross-sectional structure and potential profile of a conventional CCD.
【図２】 （ａ）は本発明のＣＣＤのレイアウト図、
（ｂ）は本発明のＣＣＤの断面構造及びポテンシャルプ
ロファイルである。2A is a layout diagram of a CCD of the present invention, FIG.
(B) is a sectional structure and potential profile of the CCD of the present invention.
２０、２４…ゲート電極、２１、２５…ゲート電極、２
２…第１のバリヤゲート、２３…第２のバリヤゲート。20, 24 ... Gate electrode, 21, 25 ... Gate electrode, 2
2 ... 1st barrier gate, 23 ... 2nd barrier gate.
Claims (3)
て光の信号を電気的な映像信号に変換して出力する複数
個のフォトダイオード領域（ＰＤ）と、 前記フォトダイオード領域の間に垂直方向に形成され、
ゲート電極（２０、２１）に印加される４相クロック
（ＶΦ1、ＶΦ2、ＶΦ3、ＶΦ4）によりフォトダイオー
ド領域で生成された電荷を垂直方向に転送する複数の垂
直電荷転送領域と、 前記垂直電荷転送領域の一端側に形成され、ゲート電極
（２４、２５）に印加される２相クロック（ＨΦ1、Ｈ
Φ2）により垂直方向に転送された映像信号電荷を水平
方向に転送する水平電荷転送領域（ＨＣＣＤ）を備えた
固体撮像素子において、 前記垂直電荷転送領域（ＶＣＣＤ）と水平電荷転送領域
（ＨＣＣＤ）とのインタフェース部に、前記ＶＣＣＤ領
域の最後端のゲート電極とＨＣＣＤ領域の最初のゲート
電極との間に、外部のＤＣバイアスにより前記インタフ
ェース部にポテンシャルステップを形成するバリヤゲー
トを設けたことを特徴とする固体撮像素子の構造。1. A plurality of photodiode regions (PD) arranged in a matrix on a semiconductor substrate to convert an optical signal into an electric image signal and output the image signal, and a vertical direction between the photodiode regions. Formed,
A plurality of vertical charge transfer regions for vertically transferring the charges generated in the photodiode regions by the four-phase clocks (VΦ 1 , VΦ 2 , VΦ 3 , VΦ 4 ) applied to the gate electrodes (20, 21); A two-phase clock (HΦ 1 , H) formed at one end of the vertical charge transfer region and applied to the gate electrodes (24, 25).
In the solid-state image sensor having a horizontal charge transfer area (HCCD) for horizontally transferring the video signal charges transferred in the vertical direction by Φ 2 ), the vertical charge transfer area (VCCD) and the horizontal charge transfer area (HCCD) And a barrier gate for forming a potential step in the interface section by an external DC bias between the last gate electrode of the VCCD area and the first gate electrode of the HCCD area. The structure of the solid-state image sensor.
２のバリヤゲートの二重ゲート構造であることを特徴と
する請求項１記載の固体撮像素子の構造。2. The structure of a solid-state image pickup device according to claim 1, wherein the barrier gate has a double gate structure of a first barrier gate and a second barrier gate.
か一つの下側領域にイオン注入工程によりＶＣＣＤとＨ
ＣＣＤとの中間ポテンシャルレベルを有するバリヤ層が
形成されることを特徴とする請求項１又は請求項２記載
の固体撮像素子の構造。3. The VCCD and H are formed in the lower region of one of the first and second barrier gates by an ion implantation process.
The structure of the solid-state imaging device according to claim 1 or 2, wherein a barrier layer having an intermediate potential level with respect to the CCD is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7258236A JP2866329B2 (en) | 1995-09-12 | 1995-09-12 | Structure of solid-state image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7258236A JP2866329B2 (en) | 1995-09-12 | 1995-09-12 | Structure of solid-state image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0982935A true JPH0982935A (en) | 1997-03-28 |
| JP2866329B2 JP2866329B2 (en) | 1999-03-08 |
Family
ID=17317422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7258236A Expired - Lifetime JP2866329B2 (en) | 1995-09-12 | 1995-09-12 | Structure of solid-state image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2866329B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60160658A (en) * | 1984-02-01 | 1985-08-22 | Hitachi Ltd | Solid-state image pickup element |
| JPH04167470A (en) * | 1990-10-30 | 1992-06-15 | Nec Corp | Solid-state imaging device, solid-state imaging device production method and operating method |
-
1995
- 1995-09-12 JP JP7258236A patent/JP2866329B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60160658A (en) * | 1984-02-01 | 1985-08-22 | Hitachi Ltd | Solid-state image pickup element |
| JPH04167470A (en) * | 1990-10-30 | 1992-06-15 | Nec Corp | Solid-state imaging device, solid-state imaging device production method and operating method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2866329B2 (en) | 1999-03-08 |
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