JPH098063A - Manufacture of semiconductor integrated device - Google Patents
Manufacture of semiconductor integrated deviceInfo
- Publication number
- JPH098063A JPH098063A JP15729695A JP15729695A JPH098063A JP H098063 A JPH098063 A JP H098063A JP 15729695 A JP15729695 A JP 15729695A JP 15729695 A JP15729695 A JP 15729695A JP H098063 A JPH098063 A JP H098063A
- Authority
- JP
- Japan
- Prior art keywords
- resistance element
- metal
- semiconductor integrated
- hole
- integrated device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積装置の製造方
法、特に高精度の抵抗素子を含む半導体集積装置の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated device, and more particularly to a method for manufacturing a semiconductor integrated device including a highly accurate resistance element.
【0002】[0002]
【従来技術】図20〜26は従来の抵抗素子を含む半導
体集積装置の製造方法を工程順に説明する断面図であ
る。20 to 26 are sectional views for explaining a conventional method of manufacturing a semiconductor integrated device including a resistance element in the order of steps.
【0003】図20〜26の従来例は、半絶縁性基板1
の上に導電層を有し、ゲート電極6、ならびにゲート電
極6を挟むように2つのオーミック電極から構成される
半導体素子の形成、抵抗素子を形成する工程から構成さ
れている。The conventional example shown in FIGS. 20 to 26 is a semi-insulating substrate 1.
It includes a step of forming a gate electrode 6 and a semiconductor element composed of two ohmic electrodes so as to sandwich the gate electrode 6, and a step of forming a resistance element.
【0004】まず、半絶縁性GaAs基板1の上にバッ
ファ層2、導電層となる第1のn型GaAs層3、オー
ミック電極のオーム性コンタクト抵抗を低減するために
前記第1のn型GaAs層3よりも高いキャリア濃度の
第2のn型GaAs層4を連続的に分子線エピタキシャ
ル成長法により連続的に成長する。First, on the semi-insulating GaAs substrate 1, a buffer layer 2, a first n-type GaAs layer 3 serving as a conductive layer, and the first n-type GaAs in order to reduce the ohmic contact resistance of the ohmic electrode. The second n-type GaAs layer 4 having a carrier concentration higher than that of the layer 3 is continuously grown by the molecular beam epitaxial growth method.
【0005】次に、図20に示すようにゲート電極6部
の第2のn型GaAs層ならびに第1のGaAs層の一
部をエッチングする。Next, as shown in FIG. 20, the second n-type GaAs layer of the gate electrode 6 and a part of the first GaAs layer are etched.
【0006】次に、選択的なホウ素イオン注入による電
気的な素子分離を行い、図21に示すように第1のn型
GaAs層上にゲート電極6、第2のn型GaAs上に
第2のGaAs層とオーム性接合をするオーミック電極
を順次形成する。Next, electrical element isolation is performed by selective boron ion implantation, and the gate electrode 6 is formed on the first n-type GaAs layer and the second n-type GaAs is formed on the second n-type GaAs layer as shown in FIG. An ohmic electrode is formed in sequence to form an ohmic contact with the GaAs layer.
【0007】次に抵抗素子を形成する領域の第1の絶縁
膜5をゲート電極6の形成方法と同様に異方性ドライエ
ッチング法により選択的にエッチングし、WSiN膜7
をスパッタ法により堆積した後、レジストによりパター
ニングを行い、反応性ドライエッチング法により加工す
ることにより図22に示すように抵抗素子を形成する。Next, the first insulating film 5 in the region where the resistance element is formed is selectively etched by the anisotropic dry etching method similarly to the method of forming the gate electrode 6, and the WSiN film 7 is formed.
After being deposited by sputtering, patterning is performed with a resist and processing is performed by reactive dry etching to form a resistance element as shown in FIG.
【0008】次に図23に示すように第1の絶縁膜5を
ウエットエッチング法によりエッチングを行いAuGe
Niを蒸着して、リフトオフ法により加工を行いオーミ
ック電極8を形成する。Next, as shown in FIG. 23, the first insulating film 5 is etched by wet etching to obtain AuGe.
Ni is vapor-deposited and processed by the lift-off method to form the ohmic electrode 8.
【0009】次に図24に示すように第2の絶縁膜9を
成長して平坦化を行う。次に図25に示すように第2の
絶縁膜9上に感光材10を塗布し、第1のスルーホール
12部の露光を行い、スルーホール部の露光を一括に行
い、異方性ドライエッチング法によりスルーホールを形
成する。Next, as shown in FIG. 24, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 25, the photosensitive material 10 is applied on the second insulating film 9, the first through-hole 12 is exposed, and the through-hole is collectively exposed to perform anisotropic dry etching. A through hole is formed by the method.
【0010】最後に、電解メッキパス用金属を全面にス
パッタ法により堆積した後に、レジストによるパターニ
ングを施し、選択的にメッキを行い、前記メッキをマス
クに電解メッキパス用金属を異方性エッチングによりエ
ッチングを行って配線11を形成して図26に示すよう
な半導体集積装置を製造する。Finally, after depositing a metal for an electrolytic plating pass on the entire surface by sputtering, patterning with a resist is performed and selective plating is performed. Using the plating as a mask, the metal for an electrolytic plating pass is anisotropically etched. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 26 is manufactured.
【0011】[0011]
【発明が解決しようとする課題】従来の抵抗素子を含む
半導体集積装置の製造方法では、抵抗素子を形成する場
合、抵抗素子に使用する材料の膜厚ばらつきによる単位
面積当たりの低効率のばらつきが大きく影響して、抵抗
素子の抵抗値が安定して得られない問題があった。製造
上の膜厚の許容範囲は±10%であり、その範囲で抵抗
値がばらつく問題があり、歩留りを低下させていた。In the conventional method of manufacturing a semiconductor integrated device including a resistance element, when the resistance element is formed, there is a variation in low efficiency per unit area due to a variation in the film thickness of the material used for the resistance element. There is a problem in that the resistance value of the resistance element cannot be stably obtained due to a large influence. The permissible range of the film thickness in manufacturing is ± 10%, and there is a problem that the resistance value varies in that range, which reduces the yield.
【0012】本発明は上述の点にかんがみてなされたも
ので、高精度の抵抗素子を実現するために、ゲート金属
材料、オーミック電極材料を抵抗素子の材料に使用する
ことを可能にした半導体集積装置の製造方法を提供する
ことを目的とする。The present invention has been made in view of the above points, and in order to realize a highly accurate resistance element, a semiconductor integrated circuit in which a gate metal material and an ohmic electrode material can be used as the material of the resistance element. An object is to provide a method for manufacturing a device.
【0013】[0013]
【課題を解決するための手段】上記目的を達成するた
め、本発明は半絶縁性GaAs基板上に導電層を有し前
記導電層とオーム性接合するソース電極およびドレイン
電極の2つのオーミック電極、および前記オーミック電
極に挟まれるゲート電極からなる半導体素子を形成する
工程、前記半絶縁性GaAs基板上に抵抗素子となる金
属を堆積する工程、前記抵抗素子となる金属を加工する
工程、前記金属を用いた抵抗素子の抵抗値を測定する工
程、前記抵抗素子と外部を電気的に接続する2つ以上の
スルーホールのうち異なるスルーホールを2回以上に分
けて連続的に露光を行う工程、前記抵抗素子金属上に形
成する前記スルーホールを全て同時にエッチングして形
成する工程、配線を形成する工程を有することを特徴と
する。In order to achieve the above object, the present invention has two ohmic electrodes, a source electrode and a drain electrode, which have a conductive layer on a semi-insulating GaAs substrate and form an ohmic contact with the conductive layer. And a step of forming a semiconductor element composed of a gate electrode sandwiched between the ohmic electrodes, a step of depositing a metal to become a resistance element on the semi-insulating GaAs substrate, a step of processing the metal to become the resistance element, A step of measuring a resistance value of the used resistance element, a step of continuously exposing two or more through holes different from the two or more through holes for electrically connecting the resistance element and the outside, and performing continuous exposure; The method is characterized by including a step of simultaneously etching and forming all the through holes formed on the resistance element metal and a step of forming wiring.
【0014】また、本発明は抵抗素子に使用する材料が
半導体素子のゲート電極の材料と同一であること、また
は抵抗素子に使用する材料が半導体素子のオーミック電
極の材料と同一であることを特徴とする。The present invention is also characterized in that the material used for the resistance element is the same as the material for the gate electrode of the semiconductor element, or the material used for the resistance element is the same as the material for the ohmic electrode of the semiconductor element. And
【0015】[0015]
【作用】本発明は半絶縁性基板上に設けられた金属によ
り形成された抵抗素子をその抵抗値の測定後に抵抗素子
長さを変更することにより堆積した金属の抵抗値ばらつ
きを調整可能なため、ばらつきの中心値が安定し、高精
度の抵抗素子を含む半導体集積装置を高歩留まりで実現
できる。また、本発明ではオーミック電極などの高温の
熱工程を通すと形状が変化し、抵抗値のばらつきが大き
くなる金属も抵抗素子の材料として使用できるため、抵
抗素子を形成する工程を追加することなく半導体素子と
同時に抵抗素子を形成できるため、工程の短縮化が図ら
れ安価な半導体集積装置を実現できる。The present invention makes it possible to adjust the resistance variation of the deposited metal by changing the resistance element length after measuring the resistance value of the resistance element formed of a metal provided on the semi-insulating substrate. The central value of variation is stable, and a semiconductor integrated device including a highly accurate resistance element can be realized with high yield. In addition, in the present invention, a metal whose shape changes when subjected to a high-temperature heating process such as ohmic electrode and has a large variation in resistance value can be used as the material of the resistance element, so that the step of forming the resistance element is not necessary. Since the resistance element can be formed simultaneously with the semiconductor element, the process can be shortened and an inexpensive semiconductor integrated device can be realized.
【0016】[0016]
【実施例】以下本発明による半導体集積装置の製造方法
を図面に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor integrated device according to the present invention will be described below with reference to the drawings.
【0017】図1〜7は本発明の実施例1の概略構成を
工程順に説明する断面図である。1 to 7 are sectional views for explaining a schematic structure of a first embodiment of the present invention in the order of steps.
【0018】半絶縁性GaAs基板1上に前記半絶縁性
GaAs基板1の影響を低減するためのバッファ層2、
導電層となる第1のn型GaAs層3およびオーミック
コンタクト層となる第2のn型GaAs層4を分子線エ
ピタキシャル成長法により連続的に成長する。この連続
成長は金属気相成長法を用いた場合にも同様である。次
に、図1に示すようにゲート電極部の第2のn型GaA
s層4ならびに第1のn型GaAs層3の一部をエッチ
ングしてリセスを形成する。On the semi-insulating GaAs substrate 1, a buffer layer 2 for reducing the influence of the semi-insulating GaAs substrate 1,
The first n-type GaAs layer 3 serving as a conductive layer and the second n-type GaAs layer 4 serving as an ohmic contact layer are continuously grown by a molecular beam epitaxial growth method. This continuous growth is the same when the metal vapor deposition method is used. Next, as shown in FIG. 1, the second n-type GaA of the gate electrode portion is formed.
A part of the s layer 4 and the first n-type GaAs layer 3 is etched to form a recess.
【0019】次に、選択的なホウ素イオン注入による電
気的な素子分離を行い、第1の絶縁膜5を5000Å全
面に成長して、ゲート電極部の第1の絶縁膜5を異方性
ドライエッチング法により選択的にエッチングする。さ
らに、WSi/Auを連続的にスパッタ法により堆積し
た後、レジストによりパターニングを行い異方性ドライ
エッチング法により前記WSi/Auを加工して図2に
示すようにゲート電極6を形成する。Next, electrical isolation is performed by selective boron ion implantation, the first insulating film 5 is grown on the entire surface of 5000 Å, and the first insulating film 5 in the gate electrode portion is anisotropically dried. Selectively etched by the etching method. Further, after WSi / Au is continuously deposited by sputtering, patterning is performed with a resist and the WSi / Au is processed by anisotropic dry etching to form the gate electrode 6 as shown in FIG.
【0020】次に抵抗素子を形成する領域の第1の絶縁
膜5をゲート電極6の形成方法と同様に異方性ドライエ
ッチング法により選択的にエッチングし、WSiN膜7
をスパッタ法により堆積した後レジストによりパターニ
ングを行い、反応性ドライエッチング法により加工する
ことにより図3に示すように抵抗素子を形成する。Next, the first insulating film 5 in the region where the resistance element is formed is selectively etched by the anisotropic dry etching method similarly to the method of forming the gate electrode 6, and the WSiN film 7 is formed.
Is deposited by a sputtering method, patterned by a resist, and processed by a reactive dry etching method to form a resistance element as shown in FIG.
【0021】次に図4に示すように第1の絶縁膜5をウ
エットエッチング法によりエッチングを行いAuGeN
iを蒸着して、リフトオフ法により加工を行いオーミッ
ク電極8を形成する。この時に抵抗素子の抵抗値、また
は予め用意されているTEGを用いたシート抵抗測定を
行い、抵抗素子の抵抗値を求める。求められた抵抗素子
の実測の抵抗値と、予め設計に用いられた設計の抵抗値
とを比較して抵抗値ずれ量を算出する。Next, as shown in FIG. 4, the first insulating film 5 is etched by wet etching to obtain AuGeN.
i is vapor-deposited and processed by the lift-off method to form the ohmic electrode 8. At this time, the resistance value of the resistance element or the sheet resistance using a TEG prepared in advance is measured to obtain the resistance value of the resistance element. The resistance value deviation amount is calculated by comparing the obtained actual resistance value of the resistance element with the designed resistance value used for the design in advance.
【0022】次に図5に示すように第2の絶縁膜9を成
長して平坦化を行う。次に図6に示すように第2の絶縁
膜9上に感光材10を塗布し、第1のスルーホール12
部の露光を行い、更に、第1のスルーホール12部の露
光に使用したものと異なるマスクを使用して、続けて第
2のスルーホール13部の露光を行う。第2のスルーホ
ール13部の露光の際、露光機上でオフセットをかけ、
抵抗素子の抵抗値のずれ量を第1のスルーホール12並
びに第2のスルーホール13間の距離で補正を行うこと
とする。Next, as shown in FIG. 5, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 6, a photosensitive material 10 is applied on the second insulating film 9, and the first through holes 12 are formed.
Then, the second through-hole 13 is exposed using a mask different from that used for exposing the first through-hole 12 part. When exposing the second through-hole 13 part, offset is applied on the exposure machine,
The deviation amount of the resistance value of the resistance element is corrected by the distance between the first through hole 12 and the second through hole 13.
【0023】最後に、電解メッキパス用金属を全面にス
パッタ法により堆積した後に、レジストによるパターニ
ングを施し、選択的にメッキを行い、前記メッキをマス
クに電解メッキパス用金属を異方性エッチングによりエ
ッチングを行って配線11を形成して図7に示すような
半導体集積装置を製造する。Finally, a metal for electrolytic plating pass is deposited on the entire surface by sputtering, patterning is performed with a resist, selective plating is performed, and the metal for electrolytic plating pass is etched by anisotropic etching using the plating as a mask. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 7 is manufactured.
【0024】図8〜13は本発明の実施例2の概略構成
を工程順に説明する断面図である。8 to 13 are sectional views for explaining the schematic structure of the second embodiment of the present invention in the order of steps.
【0025】半絶縁性GaAs基板1上に前記半絶縁性
GaAs基板1の影響を低減するためのバッファ層2、
導電層となる第1のn型GaAs層3およびオーミック
コンタクト層となる第2のn型GaAs層4を分子線エ
ピタキシャル成長法により連続的に成長する。この連続
成長は金属気相成長法を用いた場合にも同様である。次
に、図8に示すようにゲート電極部、並びに抵抗素子部
の第2のn型GaAs層4ならびに第1のn型GaAs
層3の一部をエッチングしてリセスを形成する。On the semi-insulating GaAs substrate 1, a buffer layer 2 for reducing the influence of the semi-insulating GaAs substrate 1,
The first n-type GaAs layer 3 serving as a conductive layer and the second n-type GaAs layer 4 serving as an ohmic contact layer are continuously grown by a molecular beam epitaxial growth method. This continuous growth is the same when the metal vapor deposition method is used. Next, as shown in FIG. 8, the second n-type GaAs layer 4 and the first n-type GaAs in the gate electrode section and the resistance element section are formed.
A portion of layer 3 is etched to form a recess.
【0026】次に、選択的なホウ素イオン注入による電
気的な素子分離を行い、第1の絶縁膜5を5000Å全
面に成長して、ゲート電極部並びに抵抗素子部の第1の
絶縁膜5を異方性ドライエッチング法により選択的にエ
ッチングする。さらに、WSi/Auを連続的にスパッ
タ法により堆積した後、レジストによりパターニングを
行い異方性ドライエッチング法により前記WSi/Au
を加工して図9に示すようにゲート電極6並びに抵抗素
子を形成する。Next, electrical element isolation is performed by selective boron ion implantation, the first insulating film 5 is grown on the entire surface of 5000 Å, and the first insulating film 5 of the gate electrode portion and the resistance element portion is formed. Selective etching is performed by anisotropic dry etching. Further, after WSi / Au is continuously deposited by a sputtering method, patterning is performed by a resist and the WSi / Au is subjected to an anisotropic dry etching method.
Are processed to form the gate electrode 6 and the resistance element as shown in FIG.
【0027】次に図10に示すように第1の絶縁膜5を
ウエットエッチング法によりエッチングを行いAuGe
Niを蒸着して、リフトオフ法により加工を行いオーミ
ック電極8を形成する。オーミック電極8の形成後に抵
抗素子の抵抗値、または予め用意されているTEGを用
いたシート抵抗測定を行い、抵抗素子の抵抗値を求め
る。求められた抵抗素子の実測の抵抗値と、予め設計に
用いられた設計の抵抗値とを比較して抵抗値ずれ量を算
出する。Next, as shown in FIG. 10, the first insulating film 5 is etched by wet etching to obtain AuGe.
Ni is vapor-deposited and processed by the lift-off method to form the ohmic electrode 8. After the ohmic electrode 8 is formed, the resistance value of the resistance element or the sheet resistance using a TEG prepared in advance is measured to obtain the resistance value of the resistance element. The resistance value deviation amount is calculated by comparing the obtained actual resistance value of the resistance element with the designed resistance value used for the design in advance.
【0028】次に図11に示すように第2の絶縁膜9を
成長して平坦化を行う。次に図12に示すように第2の
絶縁膜9上に感光材10を塗布し、第1のスルーホール
12部の露光を行い、更に、第1のスルーホール12部
の露光に使用したものと異なるマスクを使用して、続け
て第2のスルーホール13部の露光を行う。第2のスル
ーホール13部の露光の際、露光機上でオフセットをか
け、抵抗素子の抵抗値のずれ量を第1のスルーホール1
2並びに第2のスルーホール13間の距離で補正を行う
こととする。Next, as shown in FIG. 11, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 12, the photosensitive material 10 is applied on the second insulating film 9, the first through hole 12 is exposed, and the first through hole 12 is used for exposure. Then, the second through hole 13 is exposed by using a different mask. When the second through hole 13 is exposed, an offset is applied on the exposure machine so that the amount of deviation of the resistance value of the resistance element can be adjusted by the first through hole 1.
2 and the distance between the second through holes 13 are used for correction.
【0029】最後に、電解メッキパス用金属を全面にス
パッタ法により堆積した後に、レジストによるパターニ
ングを施し、選択的にメッキを行い、前記メッキをマス
クに電解メッキパス用金属を異方性エッチングによりエ
ッチングを行って配線11を形成して図13に示すよう
な半導体集積装置を製造する。Finally, a metal for electrolytic plating pass is deposited on the entire surface by sputtering, patterning is performed with a resist, selective plating is performed, and the metal for electrolytic plating pass is etched by anisotropic etching using the plating as a mask. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 13 is manufactured.
【0030】図14〜19は本発明の実施例3の概略構
成を工程順に説明する断面図である。14 to 19 are sectional views for explaining the schematic structure of the third embodiment of the present invention in the order of steps.
【0031】半絶縁性GaAs基板1上に前記半絶縁性
GaAs基板1の影響を低減するためのバッファ層2、
導電層となる第1のn型GaAs層3およびオーミック
コンタクト層となる第2のn型GaAs層4を分子線エ
ピタキシャル成長法により連続的に成長する。この連続
成長は金属気相成長法を用いた場合にも同様である。次
に、図14に示すようにゲート電極部の第2のn型Ga
As層4ならびに第1のn型GaAs層3の一部をエッ
チングしてリセスを形成する。On the semi-insulating GaAs substrate 1, a buffer layer 2 for reducing the influence of the semi-insulating GaAs substrate 1,
The first n-type GaAs layer 3 serving as a conductive layer and the second n-type GaAs layer 4 serving as an ohmic contact layer are continuously grown by a molecular beam epitaxial growth method. This continuous growth is the same when the metal vapor deposition method is used. Next, as shown in FIG. 14, the second n-type Ga of the gate electrode portion is formed.
A recess is formed by etching part of the As layer 4 and the first n-type GaAs layer 3.
【0032】次に、選択的なホウ素イオン注入による電
気的な素子分離を行い、第1の絶縁膜5を5000Å全
面に成長して、ゲート電極部の前記第1の絶縁膜5を異
方性ドライエッチング法により選択的にエッチングす
る。さらに、WSi/Auを連続的にスパッタ法により
堆積した後、レジストによりパターニングを行い異方性
ドライエッチング法により前記WSi/Auを加工して
図15に示すようにゲート電極6を形成する。Next, electrical isolation is performed by selective boron ion implantation, the first insulating film 5 is grown on the entire surface of 5000 Å, and the first insulating film 5 in the gate electrode portion is anisotropically formed. Selective etching is performed by a dry etching method. Further, after WSi / Au is continuously deposited by the sputtering method, patterning is performed with a resist and the WSi / Au is processed by the anisotropic dry etching method to form the gate electrode 6 as shown in FIG.
【0033】次に図16に示すようにオーミック電極8
形成部ならびに抵抗素子部の前記第1の絶縁膜5をウエ
ットエッチング法によりエッチングを行いAuGeNi
を蒸着して、リフトオフ法により加工を行いオーミック
電極8、抵抗素子を形成する。オーミック電極8の形成
後に抵抗素子の抵抗値、または予め用意されているTE
Gを用いたシート抵抗測定を行い、抵抗素子の抵抗値を
求める。求められた抵抗素子の実測の抵抗値と、予め設
計に用いられた設計の抵抗値とを比較して抵抗値ずれ量
を算出する。Next, as shown in FIG. 16, the ohmic electrode 8 is formed.
The first insulating film 5 in the formation portion and the resistance element portion is etched by wet etching to obtain AuGeNi.
Is vapor-deposited and processed by a lift-off method to form an ohmic electrode 8 and a resistance element. The resistance value of the resistance element after formation of the ohmic electrode 8 or TE prepared in advance
Sheet resistance measurement using G is performed to obtain the resistance value of the resistance element. The resistance value deviation amount is calculated by comparing the obtained actual resistance value of the resistance element with the designed resistance value used for the design in advance.
【0034】次に図17に示すように第2の絶縁膜9を
成長して平坦化を行う。次に図18に示すように第2の
絶縁膜9上に感光材10を塗布し、第1のスルーホール
12部の露光を行い、更に、第1のスルーホール12部
の露光に使用したものと異なるマスクを使用して、続け
て第2のスルーホール13部の露光を行う。第2のスル
ーホール13部の露光の際、露光機上でオフセットをか
け、抵抗素子の抵抗値のずれ量を第1のスルーホール1
2並びに第2のスルーホール13間の距離で補正を行う
こととする。Next, as shown in FIG. 17, a second insulating film 9 is grown and flattened. Next, as shown in FIG. 18, the photosensitive material 10 is applied on the second insulating film 9, the first through-hole 12 part is exposed, and then the first through-hole 12 part is used for exposure. Then, the second through hole 13 is exposed by using a different mask. When the second through hole 13 is exposed, an offset is applied on the exposure machine so that the amount of deviation of the resistance value of the resistance element can be adjusted by the first through hole 1.
2 and the distance between the second through holes 13 are used for correction.
【0035】最後に、電解メッキパス用金属を全面にス
パッタ法により堆積した後に、レジストによるパターニ
ングを施し、選択的にメッキを行い、前記メッキをマス
クに電解メッキパス用金属を異方性エッチングによりエ
ッチングを行って配線11を形成して図19に示すよう
な半導体集積装置を製造する。Finally, a metal for electrolytic plating pass is deposited on the entire surface by sputtering, patterning with a resist is performed, selective plating is performed, and the metal for electrolytic plating pass is etched by anisotropic etching using the plating as a mask. Then, the wiring 11 is formed and the semiconductor integrated device as shown in FIG. 19 is manufactured.
【0036】[0036]
【発明の効果】本発明は、抵抗素子を含む半導体集積装
置に関し、抵抗素子の抵抗値を測定し、抵抗値のずれ量
を予め測定し、抵抗素子の距離を変化できることから抵
抗素子に使用する材料の膜厚ばらつきを吸収できるため
に、プロセス上の膜厚ばらつき以内に高精度な抵抗素子
を実現でき、高精度な抵抗素子を有する半導体集積装置
を高歩留まりで実現する効果を有する。INDUSTRIAL APPLICABILITY The present invention relates to a semiconductor integrated device including a resistance element, which is used for the resistance element because the resistance value of the resistance element is measured, the deviation amount of the resistance value is measured in advance, and the distance between the resistance elements can be changed. Since the variation in the film thickness of the material can be absorbed, the highly accurate resistance element can be realized within the variation in the film thickness in the process, and the semiconductor integrated device having the highly accurate resistance element can be realized at a high yield.
【図1】本発明の実施例1の第1工程の概略構成を説明
する断面図である。FIG. 1 is a sectional view illustrating a schematic configuration of a first step of Example 1 of the present invention.
【図2】本発明の実施例1の第2工程の概略構成を説明
する断面図である。FIG. 2 is a sectional view illustrating a schematic configuration of a second step of Example 1 of the present invention.
【図3】本発明の実施例1の第3工程の概略構成を説明
する断面図である。FIG. 3 is a sectional view illustrating a schematic configuration of a third step of Example 1 of the present invention.
【図4】本発明の実施例1の第4工程の概略構成を説明
する断面図である。FIG. 4 is a sectional view illustrating a schematic configuration of a fourth step of Example 1 of the present invention.
【図5】本発明の実施例1の第5工程の概略構成を説明
する断面図である。FIG. 5 is a sectional view illustrating a schematic configuration of a fifth step of Example 1 of the present invention.
【図6】本発明の実施例1の第6工程の概略構成を説明
する断面図である。FIG. 6 is a sectional view illustrating a schematic configuration of a sixth step of Example 1 of the present invention.
【図7】本発明の実施例1の第7工程の概略構成を説明
する断面図である。FIG. 7 is a cross-sectional view illustrating the schematic configuration of a seventh step of Example 1 of the present invention.
【図8】本発明の実施例2の第1工程の概略構成を説明
する断面図である。FIG. 8 is a sectional view illustrating a schematic configuration of a first step of Example 2 of the present invention.
【図9】本発明の実施例2の第2工程の概略構成を説明
する断面図である。FIG. 9 is a sectional view illustrating a schematic configuration of a second step of Example 2 of the present invention.
【図10】本発明の実施例2の第3工程の概略構成を説
明する断面図である。FIG. 10 is a sectional view illustrating a schematic configuration of a third step of Example 2 of the present invention.
【図11】本発明の実施例2の第4工程の概略構成を説
明する断面図である。FIG. 11 is a cross-sectional view illustrating the schematic structure of a fourth step of Example 2 of the present invention.
【図12】本発明の実施例2の第5工程の概略構成を説
明する断面図である。FIG. 12 is a sectional view illustrating a schematic configuration of a fifth step of Example 2 of the present invention.
【図13】本発明の実施例2の第6工程の概略構成を説
明する断面図である。FIG. 13 is a sectional view illustrating a schematic configuration of a sixth step of Example 2 of the present invention.
【図14】本発明の実施例3の第1工程の概略構成を説
明する断面図である。FIG. 14 is a sectional view illustrating a schematic configuration of a first step of Example 3 of the present invention.
【図15】本発明の実施例3の第2工程の概略構成を説
明する断面図である。FIG. 15 is a sectional view illustrating a schematic configuration of a second step of Example 3 of the present invention.
【図16】本発明の実施例3の第3工程の概略構成を説
明する断面図である。FIG. 16 is a sectional view illustrating a schematic configuration of a third step of Example 3 of the present invention.
【図17】本発明の実施例3の第4工程の概略構成を説
明する断面図である。FIG. 17 is a sectional view illustrating a schematic configuration of a fourth step of Example 3 of the present invention.
【図18】本発明の実施例3の第5工程の概略構成を説
明する断面図である。FIG. 18 is a sectional view illustrating a schematic configuration of a fifth step of Example 3 of the present invention.
【図19】本発明の実施例3の第6工程の概略構成を説
明する断面図である。FIG. 19 is a sectional view illustrating a schematic configuration of a sixth step of Example 3 of the present invention.
【図20】従来の抵抗素子を含む半導体集積装置の製造
方法の第1工程を説明する断面図である。FIG. 20 is a cross-sectional view illustrating a first step of a method for manufacturing a semiconductor integrated device including a conventional resistance element.
【図21】従来の抵抗素子を含む半導体集積装置の製造
方法の第2工程を説明する断面図である。FIG. 21 is a cross-sectional view illustrating a second step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.
【図22】従来の抵抗素子を含む半導体集積装置の製造
方法の第3工程を説明する断面図である。FIG. 22 is a cross-sectional view illustrating the third step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.
【図23】従来の抵抗素子を含む半導体集積装置の製造
方法の第4工程を説明する断面図である。FIG. 23 is a cross-sectional view illustrating the fourth step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.
【図24】従来の抵抗素子を含む半導体集積装置の製造
方法の第5工程を説明する断面図である。FIG. 24 is a cross-sectional view illustrating the fifth step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.
【図25】従来の抵抗素子を含む半導体集積装置の製造
方法の第6工程を説明する断面図である。FIG. 25 is a sectional view illustrating a sixth step of the method for manufacturing a semiconductor integrated device including a conventional resistance element.
【図26】従来の抵抗素子を含む半導体集積装置の製造
方法の第7工程を説明する断面図である。FIG. 26 is a cross-sectional view illustrating the seventh step of the method for manufacturing the semiconductor integrated device including the conventional resistance element.
1 半絶縁性GaAs基板 2 バッファ層 3 第1のn型GaAs層 4 第2のn型GaAs層 5 第1の絶縁膜 6 ゲート電極 7 WSiN膜 8 オーミック電極 9 第2の絶縁膜 10 感光材 11 配線 12 第1のスルーホール 13 第2のスルーホール 1 semi-insulating GaAs substrate 2 buffer layer 3 first n-type GaAs layer 4 second n-type GaAs layer 5 first insulating film 6 gate electrode 7 WSiN film 8 ohmic electrode 9 second insulating film 10 photosensitive material 11 Wiring 12 First through hole 13 Second through hole
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/04 21/822 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 27/04 21/822
Claims (3)
前記導電層とオーム性接合するソース電極およびドレイ
ン電極の2つのオーミック電極、および前記オーミック
電極に挟まれるゲート電極からなる半導体素子を形成す
る工程、前記半絶縁性GaAs基板上に抵抗素子となる
金属を堆積する工程、前記抵抗素子となる金属を加工す
る工程、前記金属を用いた抵抗素子の抵抗値を測定する
工程、前記抵抗素子と外部を電気的に接続する2つ以上
のスルーホールのうち異なるスルーホールを2回以上に
分けて連続的に露光を行う工程、前記抵抗素子金属上に
形成する前記スルーホールを全て同時にエッチングして
形成する工程、配線を形成する工程を有することを特徴
とする半導体集積装置の製造方法。1. A semiconductor device comprising a conductive layer on a semi-insulating GaAs substrate, two ohmic electrodes, a source electrode and a drain electrode, which are in ohmic contact with the conductive layer, and a gate electrode sandwiched between the ohmic electrodes. Forming step, depositing a metal forming a resistance element on the semi-insulating GaAs substrate, processing the metal forming the resistance element, measuring the resistance value of the resistance element using the metal, the resistance Of two or more through-holes for electrically connecting the element and the outside, different through-holes are continuously exposed in two or more times, and the through-holes formed on the resistive element metal are all etched at the same time. A method of manufacturing a semiconductor integrated device, comprising: a step of forming a semiconductor integrated device and a step of forming a wiring.
子のゲート電極の材料と同一であることを特徴とする請
求項1に記載の半導体集積装置の製造方法。2. The method for manufacturing a semiconductor integrated device according to claim 1, wherein the material used for the resistance element is the same as the material for the gate electrode of the semiconductor element.
子のオーミック電極の材料と同一であることを特徴とす
る請求項1に記載の半導体集積装置の製造方法。3. The method for manufacturing a semiconductor integrated device according to claim 1, wherein the material used for the resistance element is the same as the material for the ohmic electrode of the semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7157296A JP2674618B2 (en) | 1995-06-23 | 1995-06-23 | Method for manufacturing semiconductor integrated device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7157296A JP2674618B2 (en) | 1995-06-23 | 1995-06-23 | Method for manufacturing semiconductor integrated device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH098063A true JPH098063A (en) | 1997-01-10 |
JP2674618B2 JP2674618B2 (en) | 1997-11-12 |
Family
ID=15646569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7157296A Expired - Fee Related JP2674618B2 (en) | 1995-06-23 | 1995-06-23 | Method for manufacturing semiconductor integrated device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2674618B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001168112A (en) * | 1999-12-03 | 2001-06-22 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
US6255679B1 (en) | 1998-06-29 | 2001-07-03 | Nec Corporation | Field effect transistor which can operate stably in millimeter wave band |
WO2015178050A1 (en) * | 2014-05-21 | 2015-11-26 | シャープ株式会社 | Field effect transistor |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62257770A (en) * | 1986-05-02 | 1987-11-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS63202951A (en) * | 1987-02-19 | 1988-08-22 | Toshiba Corp | Compound semiconductor device |
JPH02199865A (en) * | 1989-01-27 | 1990-08-08 | Nec Corp | Manufacture of semiconductor device |
JPH03148167A (en) * | 1989-11-02 | 1991-06-24 | Rohm Co Ltd | Semiconductor device with built-in resistor |
JPH04168763A (en) * | 1990-10-31 | 1992-06-16 | Shimadzu Corp | Manufacture of polysilicon resistor |
JPH04346467A (en) * | 1991-05-24 | 1992-12-02 | Sumitomo Electric Ind Ltd | Semiconductor device |
-
1995
- 1995-06-23 JP JP7157296A patent/JP2674618B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62257770A (en) * | 1986-05-02 | 1987-11-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS63202951A (en) * | 1987-02-19 | 1988-08-22 | Toshiba Corp | Compound semiconductor device |
JPH02199865A (en) * | 1989-01-27 | 1990-08-08 | Nec Corp | Manufacture of semiconductor device |
JPH03148167A (en) * | 1989-11-02 | 1991-06-24 | Rohm Co Ltd | Semiconductor device with built-in resistor |
JPH04168763A (en) * | 1990-10-31 | 1992-06-16 | Shimadzu Corp | Manufacture of polysilicon resistor |
JPH04346467A (en) * | 1991-05-24 | 1992-12-02 | Sumitomo Electric Ind Ltd | Semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6255679B1 (en) | 1998-06-29 | 2001-07-03 | Nec Corporation | Field effect transistor which can operate stably in millimeter wave band |
JP2001168112A (en) * | 1999-12-03 | 2001-06-22 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
WO2015178050A1 (en) * | 2014-05-21 | 2015-11-26 | シャープ株式会社 | Field effect transistor |
JPWO2015178050A1 (en) * | 2014-05-21 | 2017-04-20 | シャープ株式会社 | Field effect transistor |
US9859411B2 (en) | 2014-05-21 | 2018-01-02 | Sharp Kabushiki Kaisha | Field effect transistor |
Also Published As
Publication number | Publication date |
---|---|
JP2674618B2 (en) | 1997-11-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101164272B1 (en) | Integrated circuit resistor | |
US4948747A (en) | Method of making an integrated circuit resistor | |
JPH048943B2 (en) | ||
US3920861A (en) | Method of making a semiconductor device | |
JP2674618B2 (en) | Method for manufacturing semiconductor integrated device | |
JPH10242394A (en) | Fabrication of semiconductor device | |
KR0161198B1 (en) | Method for manufacturing resistor having high resistance by using subcollector layer of heterojunction transistor | |
JP2589393B2 (en) | GaAs Hall element | |
KR0169830B1 (en) | Method for manufacturing resistor by ion implantation on semi-insulating gaas substrate | |
JPS6337657A (en) | Power amplification transistor and manufacture thereof | |
JPH05275456A (en) | Semiconductor device and its manufacture | |
KR960002122B1 (en) | Method for making a gaas mesfet | |
KR100198456B1 (en) | Manufacturing method of low-resistor using base layer of heterojunction bipolar transistor | |
GB2064868A (en) | Schottky barrier gate field-effect transistor | |
JPS61163664A (en) | Manufacture of semiconductor device | |
JPS5931073A (en) | Manufacture of field effect transistor | |
JPS586179A (en) | Manufacture of field effect transistor | |
JPS609171A (en) | Manufacture of semiconductor device | |
CN116825739A (en) | Heterojunction bipolar transistor and formation method thereof | |
JPS6120363A (en) | Gaas ic | |
JPH11214625A (en) | Semiconductor device and manufacture thereof | |
JPH05275455A (en) | Semiconductor device and its manufacture | |
JPS6152991B2 (en) | ||
GB2051476A (en) | Field effect transistor devices | |
JPS6148957A (en) | Manufacture of mos capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970618 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070718 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080718 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090718 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100718 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100718 Year of fee payment: 13 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100718 Year of fee payment: 13 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110718 Year of fee payment: 14 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110718 Year of fee payment: 14 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120718 Year of fee payment: 15 |
|
LAPS | Cancellation because of no payment of annual fees |