JPH095770A - Semiconductor integrated device - Google Patents
Semiconductor integrated deviceInfo
- Publication number
- JPH095770A JPH095770A JP15891095A JP15891095A JPH095770A JP H095770 A JPH095770 A JP H095770A JP 15891095 A JP15891095 A JP 15891095A JP 15891095 A JP15891095 A JP 15891095A JP H095770 A JPH095770 A JP H095770A
- Authority
- JP
- Japan
- Prior art keywords
- light
- semiconductor chip
- metal
- integrated device
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、液晶表示パネルなど
の表示装置に適用されるＣＯＧ（ＣｈｉｐＯｎ Ｇｌａ
ｓｓ）実装の半導体集積装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a COG (Chip On Gla) applied to a display device such as a liquid crystal display panel.
ss) mounting semiconductor integrated device.
【０００２】[0002]
【従来の技術】ＣＯＧ実装は半導体チップをパッケージ
ングせずに、直接ガラス基板に実装するため、小型、軽
量、薄型にでき、液晶表示パネルなどの表示装置に適用
されている。図２は従来のＣＯＧ実装された半導体集積
装置の要部断面図を示す。液晶表示パネル駆動用の半導
体集積装置の半導体チップ１は、金バンプ５（金ででき
た突起電極）を有しており、この金バンプ５はガラス基
板９上に形成された透明電極７と接続される。この金バ
ンプ５で半導体チップ１がガラス基板９に透明電極７を
介して固着されるが、機械的強度が強めるために、半導
体チップ１は接着樹脂１３で固定される。液晶表示部２
０のガラス基板１０に形成された透明電極８と、半導体
チップ１が接続されたガラス基板９上に形成された透明
電極７との間に液晶１１が封止されている。半導体チッ
プ１から出力される液晶駆動信号は、導電性スペーサ１
２を介して透明電極８と電気的に接続され、液晶１１の
両端の電圧を制御することにより、光の透過を制御し、
それによって文字や数字などを表示する。2. Description of the Related Art In COG mounting, a semiconductor chip is directly mounted on a glass substrate without packaging, so that it can be made small, lightweight and thin, and is applied to a display device such as a liquid crystal display panel. FIG. 2 is a sectional view of a main part of a conventional COG-mounted semiconductor integrated device. A semiconductor chip 1 of a semiconductor integrated device for driving a liquid crystal display panel has gold bumps 5 (protruding electrodes made of gold), and the gold bumps 5 are connected to transparent electrodes 7 formed on a glass substrate 9. To be done. The semiconductor chip 1 is fixed to the glass substrate 9 via the transparent electrode 7 by the gold bumps 5, but the semiconductor chip 1 is fixed by the adhesive resin 13 in order to enhance the mechanical strength. Liquid crystal display unit 2
The liquid crystal 11 is sealed between the transparent electrode 8 formed on the glass substrate 10 of No. 0 and the transparent electrode 7 formed on the glass substrate 9 to which the semiconductor chip 1 is connected. The liquid crystal drive signal output from the semiconductor chip 1 is the conductive spacer 1
It is electrically connected to the transparent electrode 8 via 2 and controls the voltage across the liquid crystal 11 to control the transmission of light,
Characters and numbers are displayed accordingly.
【０００３】[0003]
【発明が解決しようとする課題】半導体チップ１は通常
シリコン基板にｐ形、ｎ形の不純物を拡散し、多数の微
小なトランジスタが形成されている。このトランジスタ
に光が当たるとシリコン内部に正孔と電子の荷電粒子が
発生する光起電力効果を生じ、トランジスタを誤動作さ
せる。The semiconductor chip 1 usually has a large number of minute transistors formed by diffusing p-type and n-type impurities in a silicon substrate. When the transistor is exposed to light, a photovoltaic effect occurs in which charged particles of holes and electrons are generated inside the silicon, causing the transistor to malfunction.
【０００４】これを防ぐため、ＣＯＧ実装では、半導体
チップ１が実装されたガラス基板９の裏面からの垂直光
１５を遮断するために、遮光シール１４をガラス基板９
に貼付けて、遮光対策している。しかし、ガラス基板９
の裏面に遮光シール１４を貼付けることは液晶パネルの
製造工数を増大させ、コストアップとなる。また半導体
チップ１に垂直に当たる垂直光１５に対しては遮光効果
はあるが、斜めに入った斜光１６はガラス基板９中を光
が進み、半導体チップ１に到達するため、遮光効果は低
く、半導体チップ１を誤動作させることも多い。In order to prevent this, in the COG mounting, in order to block the vertical light 15 from the back surface of the glass substrate 9 on which the semiconductor chip 1 is mounted, the light-shielding seal 14 is provided on the glass substrate 9.
It is affixed to and protects from light. However, the glass substrate 9
Affixing the light-shielding sticker 14 to the back surface of the liquid crystal panel increases the number of manufacturing steps of the liquid crystal panel and increases the cost. Further, although the vertical light 15 that strikes the semiconductor chip 1 vertically has a light-shielding effect, the obliquely incident oblique light 16 propagates through the glass substrate 9 and reaches the semiconductor chip 1, so the light-shielding effect is low, and The chip 1 often malfunctions.
【０００５】この発明の目的は、前記課題を解決するた
めに、半導体チップの能動素子領域上の表面保護膜に、
製造工程を増さずに遮光メタルを形成することで、製造
コストの増大なしに、外部からの光を遮断し、光による
誤動作を防止できる半導体集積装置を提供することであ
る。In order to solve the above problems, an object of the present invention is to provide a surface protective film on an active element region of a semiconductor chip,
It is an object of the present invention to provide a semiconductor integrated device capable of blocking light from the outside and preventing malfunction due to light by forming a light shielding metal without increasing the number of manufacturing steps, without increasing the manufacturing cost.
【０００６】[0006]
【課題を解決するための手段】前記の目的を達成するた
めに、半導体チップに形成される端子電極上にバリアメ
タルが選択的に被着され、このバリアメタル上に突起電
極が形成され、この突起電極がガラス基板上の透明電極
に固着される半導体集積装置において、半導体チップの
能動素子領域上に表面保護膜を介して光を遮断する遮光
メタルを選択的に形成する。この遮光メタルがバリアメ
タルと同一の金属膜で形成されるとよい。In order to achieve the above object, a barrier metal is selectively deposited on a terminal electrode formed on a semiconductor chip, and a protruding electrode is formed on the barrier metal. In a semiconductor integrated device in which a protruding electrode is fixed to a transparent electrode on a glass substrate, a light shielding metal for blocking light is selectively formed on an active element region of a semiconductor chip via a surface protective film. This light shielding metal may be formed of the same metal film as the barrier metal.
【０００７】半導体チップ上の表面保護膜が遮光効果を
有すると効果的である。この表面保護膜が染料を含むと
遮光効果がでる。バリアメタルが、半導体チップ上に形
成された端子電極と接する１層目の金属膜と突起電極と
接する２層目の金属膜からなる２層の金属膜で形成され
るとよい。It is effective that the surface protective film on the semiconductor chip has a light shielding effect. When the surface protective film contains a dye, a light shielding effect can be obtained. The barrier metal may be formed of a two-layer metal film including a first-layer metal film in contact with the terminal electrode formed on the semiconductor chip and a second-layer metal film in contact with the bump electrode.
【０００８】[0008]
【作用】半導体チップの能動領域上に金バンプ形成時に
必要なバリアメタルをガラス基板上の表面保護膜上に選
択的に被覆させることで、液晶表示部より斜めに入った
光に対しても遮光でき、誤動作を防止できる。また表面
保護膜に遮光性のある材料や染料を混入させることで金
バンプを形成しないボンディング方式の実装においても
遮光できる。また金バンプを形成する場合にも遮光性の
ある表面保護膜の適用で一層遮光効果を増すことができ
る。[Function] By selectively covering the surface protection film on the glass substrate with the barrier metal required for forming the gold bumps on the active area of the semiconductor chip, light can be shielded even from light obliquely entering from the liquid crystal display section. It is possible to prevent malfunction. Further, by mixing a material having a light-shielding property or a dye into the surface protective film, it is possible to shield the light even in a bonding type mounting in which a gold bump is not formed. Further, even when the gold bumps are formed, the light shielding effect can be further enhanced by applying the surface protective film having a light shielding property.
【０００９】[0009]
【実施例】図１は一実施例で、ＣＯＧ実装された半導体
チップの要部断面図を示す。シリコン基板上に能動素子
部１ａを形成した半導体チップ１上に、液晶駆動用出力
信号を取り出すアルミパッド部２が形成され、このアル
ミパッド２上を開口し、半導体チップ１上に表面保護膜
６が形成される。つぎにアルミパッド２上のバリアメタ
ル３および表面保護膜６上の遮光メタル４となる金属膜
を同時に形成する。この金属膜はアルミパッド２と接す
る１層目の金属膜としてチタンまたはクロム、金バンプ
５と接する２層目の金属膜としてタングステン、ニッケ
ルまたは銀のうち一つで構成され、それぞれをスパッタ
で、露出しているアルミパッド２上および能動素子領域
１ａの表面保護膜６上を選択的に被覆し、その後エッチ
ングでバリアメタル３および遮光メタル４に分離する。
またバリアメタル３上には金メッキで金バンプ５を形成
する。バリアメタル３を２層にするのは、アルミパッド
２とバリアメタル３との密着性およびバリアメタル３と
金バンプ５との密着性とを高めるためである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an embodiment showing a cross-sectional view of an essential part of a COG mounted semiconductor chip. An aluminum pad portion 2 for extracting a liquid crystal driving output signal is formed on a semiconductor chip 1 having an active element portion 1a formed on a silicon substrate. The aluminum pad portion 2 is opened to form a surface protective film 6 on the semiconductor chip 1. Is formed. Next, a metal film to be the barrier metal 3 on the aluminum pad 2 and the light shielding metal 4 on the surface protection film 6 is formed at the same time. This metal film is made of titanium or chromium as the first metal film in contact with the aluminum pad 2, and is made of one of tungsten, nickel or silver as the second metal film in contact with the gold bumps 5, each of which is formed by sputtering. The exposed aluminum pad 2 and the surface protection film 6 of the active element region 1a are selectively covered, and then separated into a barrier metal 3 and a light shielding metal 4 by etching.
Gold bumps 5 are formed on the barrier metal 3 by gold plating. The reason why the barrier metal 3 has two layers is to enhance the adhesion between the aluminum pad 2 and the barrier metal 3 and the adhesion between the barrier metal 3 and the gold bump 5.
【００１０】遮光メタル４により、図２で説明した、半
導体チップ１の表面に垂直に入射する垂直光１５だけで
なく、液晶表示部２０からガラス基板９に斜めに入射す
る斜光１６も半導体チップ１内に進入できず、完全に遮
光できる。また表面保護膜６に遮光性の保護膜、例えば
炭素を混入した膜や光を遮断する染料を混入した膜など
を使用することで、遮光メタル４が被覆されていないア
ルミパッド２周辺を、表面保護膜６で遮光できる。また
金バンプ５を使わずワイヤボンディング方式の実装の場
合では、前記の遮光性表面保護膜を使用することで同様
の遮光効果が得られる。Due to the light-shielding metal 4, not only the vertical light 15 vertically incident on the surface of the semiconductor chip 1 described with reference to FIG. 2 but also the oblique light 16 obliquely incident on the glass substrate 9 from the liquid crystal display section 20 is also included in the semiconductor chip 1. You can't get inside and you can completely block light. In addition, by using a light-shielding protective film as the surface protective film 6, for example, a film containing carbon or a film containing a dye that blocks light, a surface of the aluminum pad 2 not covered with the light-shielding metal 4 is covered. The protective film 6 can shield light. Further, in the case of mounting by the wire bonding method without using the gold bumps 5, the same light shielding effect can be obtained by using the above light shielding surface protective film.
【００１１】[0011]
【発明の効果】この発明により、液晶表示部から斜めに
入射した光に対しても、遮光でき、光による誤動作を防
止でき、液晶駆動用半導体集積装置の信頼性を向上でき
る。またバリアメタルとなる金属膜を遮光メタルにも利
用することで、製造工数を増加させず、従ってコストア
ップせずに高い遮光効果が得られる。また、表面保護膜
に遮光性膜を用いることで、さらに遮光効果を高めるこ
とができる。As described above, according to the present invention, it is possible to shield the light obliquely incident from the liquid crystal display portion, prevent malfunction due to light, and improve the reliability of the liquid crystal driving semiconductor integrated device. Further, by using the metal film as the barrier metal also as the light-shielding metal, a high light-shielding effect can be obtained without increasing the number of manufacturing steps and thus increasing the cost. Further, by using a light-shielding film for the surface protective film, the light-shielding effect can be further enhanced.
【００１２】また、金バンプ無しのＣＯＧ実装におい
て、表面保護膜形成で遮光材料や染料を混入した材料を
用いることで、大幅な工数増せずに、高い遮光効果が得
られる。Further, in COG mounting without gold bumps, by using a light-shielding material or a material mixed with a dye for forming the surface protective film, a high light-shielding effect can be obtained without significantly increasing the number of steps.
【図１】この発明の一実施例で、ＣＯＧ実装された半導
体チップの要部断面図FIG. 1 is a sectional view of an essential part of a COG-mounted semiconductor chip according to an embodiment of the present invention.
【図２】従来のＣＯＧ実装された半導体集積装置の要部
断面図FIG. 2 is a sectional view of an essential part of a conventional COG-mounted semiconductor integrated device.
１ 半導体チップ １ａ 能動素子領域 ２ アルミパッド ３ バリアメタル ４ 遮光メタル ５ 金バンプ ６ 表面保護膜 ７ 透明電極 ８ 透明電極 ９ ガラス基板 １０ ガラス基板 １１ 液晶 １２ 導電スペーサ １３ 接着樹脂 １４ 遮光シール １５ 垂直光 １６ 斜光 ２０ 液晶表示部 1 Semiconductor Chip 1a Active Element Area 2 Aluminum Pad 3 Barrier Metal 4 Light-shielding Metal 5 Gold Bump 6 Surface Protective Film 7 Transparent Electrode 8 Transparent Electrode 9 Glass Substrate 10 Glass Substrate 11 Liquid Crystal 12 Conductive Spacer 13 Adhesive Resin 14 Light-shielding Seal 15 Vertical Light 16 Oblique light 20 Liquid crystal display
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 Ｈ０１Ｌ 25/04 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 25/18 H01L 25/04 Z
Claims (5)
リアメタルが選択的に被着され、このバリアメタル上に
突起電極が形成され、この突起電極がガラス基板上の透
明電極に固着される半導体集積装置において、光を遮断
する遮光メタルが半導体チップの能動素子領域上に表面
保護膜を介して選択的に形成されることを特徴とする半
導体集積装置。1. A barrier metal is selectively deposited on a terminal electrode formed on a semiconductor chip, a protruding electrode is formed on the barrier metal, and the protruding electrode is fixed to a transparent electrode on a glass substrate. In the semiconductor integrated device, a light shielding metal for blocking light is selectively formed on an active element region of a semiconductor chip via a surface protective film.
膜で形成されることを特徴とする請求項１記載の半導体
集積装置。2. The semiconductor integrated device according to claim 1, wherein the barrier metal and the light shielding metal are formed of the same metal film.
とする請求項１記載の半導体集積装置。3. The semiconductor integrated device according to claim 1, wherein the surface protective film has a light shielding effect.
請求項３記載の半導体集積装置。4. The semiconductor integrated device according to claim 3, wherein the surface protective film contains a dye.
の金属膜と突起電極と接する２層目の金属膜からなる２
層の金属膜で形成されることを特徴とする請求項１記載
の半導体集積装置。5. A barrier metal comprising a first-layer metal film in contact with a terminal electrode and a second-layer metal film in contact with a bump electrode.
The semiconductor integrated device according to claim 1, wherein the semiconductor integrated device is formed of a layer metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15891095A JPH095770A (en) | 1995-06-26 | 1995-06-26 | Semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15891095A JPH095770A (en) | 1995-06-26 | 1995-06-26 | Semiconductor integrated device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH095770A true JPH095770A (en) | 1997-01-10 |
Family
ID=15682025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15891095A Pending JPH095770A (en) | 1995-06-26 | 1995-06-26 | Semiconductor integrated device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH095770A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6720656B2 (en) | 1998-12-21 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device with analysis prevention feature |
| KR100741896B1 (en) * | 2000-10-18 | 2007-07-23 | 엘지.필립스 엘시디 주식회사 | Fabrication Method for Liquid Crystal Display Panel |
-
1995
- 1995-06-26 JP JP15891095A patent/JPH095770A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6720656B2 (en) | 1998-12-21 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device with analysis prevention feature |
| KR100741896B1 (en) * | 2000-10-18 | 2007-07-23 | 엘지.필립스 엘시디 주식회사 | Fabrication Method for Liquid Crystal Display Panel |
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