JPH09508992A - 集積回路試験装置及び試験法 - Google Patents
集積回路試験装置及び試験法Info
- Publication number
- JPH09508992A JPH09508992A JP7518477A JP51847795A JPH09508992A JP H09508992 A JPH09508992 A JP H09508992A JP 7518477 A JP7518477 A JP 7518477A JP 51847795 A JP51847795 A JP 51847795A JP H09508992 A JPH09508992 A JP H09508992A
- Authority
- JP
- Japan
- Prior art keywords
- unit
- test
- integrated circuit
- pattern
- test pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.回路の少なくとも一部を機能ユニットに区分化するステップと、 1組の疑似ランダム試験パターンを選択するステップと、 疑似ランダム・パターンによって試験されるように各ユニットを設計するステ ップと、 各ユニットにメモリを設けるステップと、 各ユニットからの出力をそのメモリに結合するステップと、 試験パターンがユニットに同時に結合されるようにして集積回路上に試験モー ドを適用するステップと、 メモリからデータを読み取る機構を設けるステップと を含む集積回路の設計方法。 2.集積回路の製作の前に試験パターンによってユニットの設計を検証するステ ップを含む請求項1に記載の方法。 3.各ユニットが入力信号に対するユニットの応答を記録するシグネチャ・レジ スタを備える複数の機能ユニットと、 ユニットに対して入力信号として供給されると同じ1組の所定の試験パターン に応答する各ユニットと、 所定の試験パターンを受け取り、試験パターンをユニットに並列で結合するバ スと、 シグネチャ・レジスタの内容を読み取る試験機構と を備える集積回路。 4.試験パターンをユニットに並列に結合するバスが、集積回路に信号が供給さ れると選択されることを特徴とする請求項2に記載の集積回路。 5.シフト・レジスタの内容を端子で読み取ることができるようにシグネチャ・ レジスタが集積回路上の端子に直列に結合されている請求項4に記載の集積回路 。 6.各シグネチャ・レジスタがリニア・フィードバックを含む請求項5に記載の 集積回路。 7.試験パターンが疑似ランダムである請求項1または請求項6に記載の集積回 路。 8.集積回路の試験可能性を実現する方法であって、 各パターンが複数のビットを含む1組の疑似ランダム試験パターンを選択する ステップと、 集積回路の少なくとも一部を複数の機能ユニットに区分化するステップと、 各ユニットが各パターンのビットのうちの少なくともいくつかを受け取るよう に集積回路に試験パターンを供給するステップと、 ビットに対する各ユニットの応答を表す信号を格納するステップと、 各機能ユニットが試験パターンによって確実に試験可能にさせるステップと、 応答を表す格納された信号を検査するステップと を含む方法。 9.試験パターンを供給するステップが、少なくとも1つのアルゴリズムから試 験パターンを生成するステップを含む請求項7に記載の方法。 10.格納ステップがシグネチャ・レジスタに格納するステップを含む請求項9 に記載の方法。 11.入力試験パターンに対する応答を格納する複数の多重入力シグネチャ・レ ジスタを備える集積回路の改良型試験方法であって、 集積回路の少なくとも一部を少なくとも2つの機能ユニットに区分化し、それ ぞれの機能ユニットが異なるシグネチャ・レジスタに出力を与えるように結合す るステップと、 各ユニットを同じ1組の試験パターンによって確実に試験できるようにするス テップと、 ユニットの応答が各ユニットのそれぞれのシグネチャ・レジスタに格納される ように試験パターンの組を同時に適用するステップと、 ユニットに試験パターンを供給した後でシグネチャ・レジスタの内容を検査す るステップと を含む方法。 12.試験パターンの組が疑似ランダムである請求項11に記載の方法。 13.疑似ランダム・パターンがアルゴリズムによって生成される請求項12に 記載の方法。 14.複数の機能ユニットを有する集積回路の試験装置であって、 試験モードが選択されると、回路に供給する入力試験パターンを各ユニットに 送るバスと、 バスから入力試験パターンを受け取り、試験パターンを処理して出力信号を出 すように結合された各ユニットと、 それぞれ対応するユニットからの出力信号を受け取り、その対応するユニット に試験シグネチャを供給する各ユニットに設けた格納手段と、 格納手段に結合され、各ユニットから試験シグネチャを読み出す読み出し手段 と を備えた改良。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/175,771 US5583786A (en) | 1993-12-30 | 1993-12-30 | Apparatus and method for testing integrated circuits |
US08/175,771 | 1993-12-30 | ||
PCT/US1994/013804 WO1995019011A2 (en) | 1993-12-30 | 1994-12-02 | Apparatus and method for testing integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09508992A true JPH09508992A (ja) | 1997-09-09 |
JP3749541B2 JP3749541B2 (ja) | 2006-03-01 |
Family
ID=22641561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51847795A Expired - Fee Related JP3749541B2 (ja) | 1993-12-30 | 1994-12-02 | 集積回路試験装置及び試験法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US5583786A (ja) |
EP (1) | EP0737337B1 (ja) |
JP (1) | JP3749541B2 (ja) |
AU (1) | AU1298695A (ja) |
DE (1) | DE69430637T2 (ja) |
SG (1) | SG47061A1 (ja) |
TW (1) | TW352466B (ja) |
WO (1) | WO1995019011A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021135178A (ja) * | 2020-02-27 | 2021-09-13 | セイコーエプソン株式会社 | 半導体装置 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859962A (en) * | 1995-12-21 | 1999-01-12 | Ncr Corporation | Automated verification of digital design |
US5745500A (en) * | 1996-10-22 | 1998-04-28 | The United States Of America As Represented By The Secretary Of The Army | Built-in self testing for the identification of faulty integrated circuit chips in a multichip module |
US5790561A (en) * | 1997-01-17 | 1998-08-04 | Rockwell International Corporation | Internal testability system for microprocessor-based integrated circuit |
US5995915A (en) | 1997-01-29 | 1999-11-30 | Advanced Micro Devices, Inc. | Method and apparatus for the functional verification of digital electronic systems |
US6408410B1 (en) | 1997-06-13 | 2002-06-18 | Intel Corporation | Method and apparatus for built in self-test of buffer circuits for speed related defects |
US5978946A (en) * | 1997-10-31 | 1999-11-02 | Intel Coporation | Methods and apparatus for system testing of processors and computers using signature analysis |
US6389586B1 (en) | 1998-01-05 | 2002-05-14 | Synplicity, Inc. | Method and apparatus for invalid state detection |
US6158033A (en) * | 1998-05-08 | 2000-12-05 | S3 Incorporated | Multiple input signature testing & diagnosis for embedded blocks in integrated circuits |
US6249889B1 (en) * | 1998-10-13 | 2001-06-19 | Advantest Corp. | Method and structure for testing embedded memories |
US6557128B1 (en) * | 1999-11-12 | 2003-04-29 | Advantest Corp. | Semiconductor test system supporting multiple virtual logic testers |
US6424926B1 (en) * | 2000-03-31 | 2002-07-23 | Intel Corporation | Bus signature analyzer and behavioral functional test method |
US6754867B2 (en) | 2000-12-28 | 2004-06-22 | Intel Corporation | Method of determining non-accessible device I/O pin speed using on chip LFSR and MISR as data source and results analyzer respectively |
US6557132B2 (en) | 2001-02-22 | 2003-04-29 | International Business Machines Corporation | Method and system for determining common failure modes for integrated circuits |
US7096397B2 (en) * | 2001-09-17 | 2006-08-22 | Intel Corporation | Dft technique for avoiding contention/conflict in logic built-in self-test |
US7131046B2 (en) * | 2002-12-03 | 2006-10-31 | Verigy Ipco | System and method for testing circuitry using an externally generated signature |
US20040133831A1 (en) * | 2003-01-07 | 2004-07-08 | Emrys Williams | Semiconductor device and method and apparatus for testing such a device |
US7228474B2 (en) * | 2003-01-07 | 2007-06-05 | Sun Microsystems, Inc. | Semiconductor device and method and apparatus for testing such a device |
US7137057B2 (en) * | 2003-01-07 | 2006-11-14 | Sun Microsystems, Inc. | Method and apparatus for performing error correction code (ECC) conversion |
US7245357B2 (en) * | 2003-12-15 | 2007-07-17 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
US7353437B2 (en) * | 2004-10-29 | 2008-04-01 | Micron Technology, Inc. | System and method for testing a memory for a memory failure exhibited by a failing memory |
US7478307B1 (en) | 2005-05-19 | 2009-01-13 | Sun Microsystems, Inc. | Method for improving un-correctable errors in a computer system |
US7480847B2 (en) * | 2005-08-29 | 2009-01-20 | Sun Microsystems, Inc. | Error correction code transformation technique |
US7523342B1 (en) | 2005-10-28 | 2009-04-21 | Sun Microsystems, Inc. | Data and control integrity for transactions in a computer system |
US20070115833A1 (en) * | 2005-11-21 | 2007-05-24 | Gerald Pepper | Varying the position of test information in data units |
US9297856B2 (en) * | 2013-10-23 | 2016-03-29 | International Business Machines Corporation | Implementing MISR compression methods for test time reduction |
EP3081575A1 (en) | 2015-04-12 | 2016-10-19 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Anti-plasmodium parasite antibodies |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3643156A (en) * | 1969-06-05 | 1972-02-15 | Rca Corp | Pulse-type circuit element-testing method |
US3927371A (en) * | 1974-02-19 | 1975-12-16 | Ibm | Test system for large scale integrated circuits |
US4433413A (en) * | 1981-10-22 | 1984-02-21 | Siemens Corporation | Built-in apparatus and method for testing a microprocessor system |
US4519078A (en) * | 1982-09-29 | 1985-05-21 | Storage Technology Corporation | LSI self-test method |
US4635218A (en) * | 1983-05-09 | 1987-01-06 | Valid Logic Systems | Method for simulating system operation of static and dynamic circuit devices |
US4594711A (en) * | 1983-11-10 | 1986-06-10 | Texas Instruments Incorporated | Universal testing circuit and method |
US4597080A (en) * | 1983-11-14 | 1986-06-24 | Texas Instruments Incorporated | Architecture and method for testing VLSI processors |
GB8432533D0 (en) * | 1984-12-21 | 1985-02-06 | Plessey Co Plc | Integrated circuits |
EP0186724B1 (de) * | 1985-01-04 | 1990-12-12 | Ibm Deutschland Gmbh | Prüf- und Diagnoseeinrichtung für Digitalrechner |
US4688223A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4745355A (en) * | 1985-06-24 | 1988-05-17 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4801870A (en) * | 1985-06-24 | 1989-01-31 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
US4687988A (en) * | 1985-06-24 | 1987-08-18 | International Business Machines Corporation | Weighted random pattern testing apparatus and method |
JP2628154B2 (ja) * | 1986-12-17 | 1997-07-09 | 富士通株式会社 | 半導体集積回路 |
US4817093A (en) * | 1987-06-18 | 1989-03-28 | International Business Machines Corporation | Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure |
JP2673298B2 (ja) * | 1987-12-17 | 1997-11-05 | 三菱電機株式会社 | セルフテスト機能付半導体集積回路 |
US5084874A (en) * | 1988-09-07 | 1992-01-28 | Texas Instruments Incorporated | Enhanced test circuit |
US5027355A (en) * | 1989-04-14 | 1991-06-25 | Control Data Corporation | Logic circuit and design method for improved testability |
US5101409A (en) * | 1989-10-06 | 1992-03-31 | International Business Machines Corporation | Checkboard memory self-test |
US5138619A (en) * | 1990-02-15 | 1992-08-11 | National Semiconductor Corporation | Built-in self test for integrated circuit memory |
US5187712A (en) * | 1990-02-26 | 1993-02-16 | At&T Bell Laboratories | Pseudo-exhaustive self-test technique |
IL94115A (en) * | 1990-04-18 | 1996-06-18 | Ibm Israel | Dynamic process for creating pseudo-random test templates for pompous hardware design violence |
US5253255A (en) * | 1990-11-02 | 1993-10-12 | Intel Corporation | Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip |
US5321277A (en) * | 1990-12-31 | 1994-06-14 | Texas Instruments Incorporated | Multi-chip module testing |
US5260946A (en) * | 1991-06-03 | 1993-11-09 | Hughes Missile Systems Company | Self-testing and self-configuration in an integrated circuit |
US5331643A (en) * | 1991-09-04 | 1994-07-19 | International Business Machines Corporation | Self-testing logic with embedded arrays |
US5369648A (en) * | 1991-11-08 | 1994-11-29 | Ncr Corporation | Built-in self-test circuit |
DE69224727T2 (de) * | 1991-12-16 | 1998-11-12 | Nippon Telegraph & Telephone | Schaltung mit eingebautem Selbsttest |
US5329533A (en) * | 1991-12-26 | 1994-07-12 | At&T Bell Laboratories | Partial-scan built-in self-test technique |
US5416783A (en) * | 1993-08-09 | 1995-05-16 | Motorola, Inc. | Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processor |
-
1993
- 1993-12-30 US US08/175,771 patent/US5583786A/en not_active Expired - Lifetime
-
1994
- 1994-12-02 JP JP51847795A patent/JP3749541B2/ja not_active Expired - Fee Related
- 1994-12-02 WO PCT/US1994/013804 patent/WO1995019011A2/en active IP Right Grant
- 1994-12-02 DE DE69430637T patent/DE69430637T2/de not_active Expired - Fee Related
- 1994-12-02 SG SG498494A patent/SG47061A1/en unknown
- 1994-12-02 EP EP95904200A patent/EP0737337B1/en not_active Expired - Lifetime
- 1994-12-02 AU AU12986/95A patent/AU1298695A/en not_active Abandoned
-
1995
- 1995-11-10 TW TW084111946A patent/TW352466B/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021135178A (ja) * | 2020-02-27 | 2021-09-13 | セイコーエプソン株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
AU1298695A (en) | 1995-08-01 |
DE69430637D1 (de) | 2002-06-20 |
SG47061A1 (en) | 1998-03-20 |
WO1995019011A2 (en) | 1995-07-13 |
DE69430637T2 (de) | 2003-01-02 |
US5583786A (en) | 1996-12-10 |
TW352466B (en) | 1999-02-11 |
JP3749541B2 (ja) | 2006-03-01 |
WO1995019011A3 (en) | 1995-07-27 |
EP0737337A1 (en) | 1996-10-16 |
EP0737337A4 (en) | 1997-04-02 |
EP0737337B1 (en) | 2002-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3749541B2 (ja) | 集積回路試験装置及び試験法 | |
US11921159B2 (en) | Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems | |
US4519078A (en) | LSI self-test method | |
US7500163B2 (en) | Method and apparatus for selectively compacting test responses | |
JP4031954B2 (ja) | 集積回路の診断装置および診断方法 | |
EP1393176B1 (en) | Method and apparatus for fault tolerant and flexible test signature generator | |
US7017095B2 (en) | Functional pattern logic diagnostic method | |
Nagle et al. | Design for testability and built-in self test: A review | |
EP0849678B1 (en) | A system and method for testing electronic devices | |
CN114667455A (zh) | 用于测试电路的通用压缩器架构 | |
Huott et al. | Advanced microprocessor test strategy and methodology | |
Wang et al. | A self-test and self-diagnosis architecture for boards using boundary scans | |
JP2005017067A (ja) | 自己テスト回路内蔵の半導体集積回路およびその故障診断方法 | |
Alves et al. | A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040622 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050628 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050920 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20051108 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20051202 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091209 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101209 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |