JPH09321221A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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Publication number
JPH09321221A
JPH09321221A JP3531697A JP3531697A JPH09321221A JP H09321221 A JPH09321221 A JP H09321221A JP 3531697 A JP3531697 A JP 3531697A JP 3531697 A JP3531697 A JP 3531697A JP H09321221 A JPH09321221 A JP H09321221A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
film
type
region
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3531697A
Other languages
Japanese (ja)
Other versions
JP3054937B2 (en
Inventor
Jun Osanai
潤 小山内
Hiroaki Takasu
博昭 鷹巣
Kenji Kitamura
謙二 北村
Hirobumi Harada
博文 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP9035316A priority Critical patent/JP3054937B2/en
Publication of JPH09321221A publication Critical patent/JPH09321221A/en
Application granted granted Critical
Publication of JP3054937B2 publication Critical patent/JP3054937B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide resistors fitted for a bleeder resistor circuit part and a constant current part by making the net density difference of first conductive impurities and second conductive impurities more than specified in a circuit constituted of a first conductive polycrystalline silicon resistor and a second conductive polycrystalline silicon resistor. SOLUTION: In a silicon semiconductor substrate 101, a well area 102 whose conduction type is opposite to the substrate and opposite conduction-type diffusion layers 103 are provided. Diffusion layers 104 whose conduction type is opposite to a well are provided in the well area so as to form a MOS transistor constituted of polycrystalline silicon gate electrodes 106 and the respective diffusion layers. The polycrystalline silicon resistors 114 and 115 having the first and second conduction-type high resistance areas 107 and 109 are formed on a field oxide film 105, and high density areas 108-110 of impurities, whose conduction type is similar to that of the resistors and which can sufficiently be contacted with aluminum wirings 112, are provided on both ends of the respective resistors. These areas are doped with phosphorous being N-type impurities and the P-type resistors are stably formed. Thus, the doping amount of phosphorous is set to be more than twice.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置、特に多
結晶シリコン抵抗体を用いた抵抗回路を有する半導体装
置とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a resistance circuit using a polycrystalline silicon resistor and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】従来多結晶シリコン抵抗体を使用した抵
抗回路は数多く使用されているが、その導電型は１種類
であり、かつ不純物濃度も１種類であるものが知られて
いた。2. Description of the Related Art Conventionally, many resistance circuits using polycrystalline silicon resistors have been used, but it has been known that they have one conductivity type and one impurity concentration.

【０００３】[0003]

【発明名が解決しようとする課題】ところが、たとえば
スイッチングレギュレータ（以下ＳＷＲと略す）等の集
積回路においてそのブリーダ抵抗回路部は抵抗比精度を
保ち面積を小さくするために、通常Ｎ型の導電型でシー
ト抵抗値が５ｋΩ／□から２０ｋΩ／□程度である多結
晶シリコン抵抗で構成されるが、同抵抗体の温度に対す
る抵抗値変化は−３０００ｐｐｍ／°Ｃから−５０００
ｐｐｍ／°Ｃ程度であり、同抵抗体をＳＷＲの発振周波
数を設定する定電流部にも使用すると使用温度範囲であ
る−４０°Cから８５℃の間で、発振周波数変動を±１
０％以内におさめるのが困難であるという課題があっ
た。However, in an integrated circuit such as a switching regulator (hereinafter abbreviated as SWR), the bleeder resistance circuit section is usually of N-type conductivity type in order to maintain the resistance ratio accuracy and reduce the area. The sheet resistance value is about 5 kΩ / □ to about 20 kΩ / □, and the resistance value changes with temperature of the resistor from −3000 ppm / ° C. to −5000 ppm.
It is about ppm / ° C, and when the same resistor is used for the constant current part that sets the oscillation frequency of SWR, the oscillation frequency fluctuation is ± 1 within the operating temperature range of -40 ° C to 85 ° C.
There was a problem that it was difficult to keep it within 0%.

【０００４】本発明は上記課題を解消してブリーダ抵抗
回路部、定電流部各々に適した特性を持つ抵抗体を同時
に提供することを目的とする。It is an object of the present invention to solve the above problems and to simultaneously provide a resistor having characteristics suitable for each of the bleeder resistance circuit section and the constant current section.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体装置が上
記目的を達成するために採用した主な手段は （１）第１導電型の多結晶シリコン抵抗体および第２導
電型多結晶シリコン抵抗体とから構成される抵抗回路に
おいて、該第１導電型不純物と該第２導電型不純物のネ
ットな濃度差が２倍以上であることを特徴とする半導体
装置とした。 （２）前記第１導電型多結晶シリコン抵抗体の温度係数
と前記第２導電型多結晶シリコン抵抗体の温度係数の差
が５倍以上であり、かつどちらかの温度係数の絶対値が
１０００ｐｐｍ／°Ｃ以下であることを特徴とする半導
体装置とした。 （３）前記第１導電型多結晶シリコン抵抗体と前記第２
導電型多結晶シリコン抵抗体の膜厚はともに１０００Å
を越えない膜厚であることを特徴とする半導体装置とし
た。 （４）前記第１導電型多結晶シリコン抵抗体もしくは前
記第２導電型多結晶シリコン抵抗体のどちらかには逆導
電型の不純物を含むことを特徴とする半導体装置とし
た。 （５）半導体基板上に酸化膜を形成する工程と、前記酸
化膜上に２０００Å〜５０００Åの第１の多結晶シリコ
ン膜を形成する工程と、前記第１の多結晶シリコン膜に
１×１０19atoms/cm3以上の濃度の不純物をドーピング
する工程と、前記第１の多結晶シリコン膜をエッチング
により第１の多結晶シリコン膜領域を形成する工程と、
前記第１の多結晶シリコン膜領域の上を含む前記半導体
基板の表面に1.2×10-8〜3.4×10-7F/cm2相当の容量を
有する絶縁膜を形成する工程と、前記絶縁膜上に１００
Å〜１５００Åの第２の多結晶シリコン膜を形成する工
程と、前記第２の多結晶シリコン膜の全域ないしは第２
の多結晶シリコン膜の第１の領域に第１の導電型の不純
物を１×１０15〜５×１０19atoms/cm3ドーピングする
工程と、前記第２の多結晶シリコン膜の第２の領域に第
二の導電型の不純物を１×１０15〜５×１０19atoms/cm
3ドーピングする工程と、前記第２の多結晶シリコン膜
をエッチングにより第２の多結晶シリコン膜領域を形成
する工程と、前記第２の多結晶シリコン膜の第１の領域
の一部に１×１０19atoms/cm3以上の第１の導電型の不
純物をドーピングする工程と、前記第２の多結晶シリコ
ン膜の第２の領域の一部ないし全域に１×１０19atoms/
cm3以上の第２の導電型の不純物をドーピングする工程
と、前記絶縁膜及び第２の多結晶シリコン膜の上に中間
絶縁膜を形成する工程と、前記第１及び第２の多結晶シ
リコン及び前記半導体基板の上の前期中間絶縁膜にコン
タクト孔を設ける工程と、前記コンタクト孔に金属配線
を設ける工程とからなる半導体装置の製造方法。 （６）前記第２の多結晶シリコン膜の第１の領域の一部
への１×１０19atoms/cm 3以上の第１の導電型の不純物
ドーピングが第１の導電型のＭＯＳトランジスターの拡
散領域ドーピングと同時であり、前記第２の多結晶シリ
コン膜の第２の領域の一部ないし全域への１×１０19at
oms/cm3以上の第二の導電型の不純物ドーピングが第２
の導電型のＭＯＳトランジスターの拡散領域ドーピング
と同時であることを特徴とする半導体装置の製造方法。 （７）前記第１の多結晶シリコン膜領域の上を含む前記
半導体基板の表面への1.2×10-8〜3.4×10-7F/cm2相当
の容量を有する絶縁膜は膜厚１００〜３０００Åである
熱酸化膜であることを特徴とする半導体装置の製造方
法。 （８）前記第１の多結晶シリコン膜領域の上を含む前記
半導体基板の表面への1.2×10-8〜4×10-7F/cm2相当の
容量を有する絶縁膜は膜厚５０〜１５００Åの熱酸化膜
と膜厚５０〜２０００Åの窒化膜と膜厚１００Å以下の
熱酸化膜の積層構造であることを特徴とする半導体装置
の製造方法。The semiconductor device of the present invention is
The main means adopted to achieve the above purpose are (1) a first conductivity type polycrystalline silicon resistor and a second conductivity type.
For resistance circuit composed of electric type polycrystalline silicon resistor
At the first conductivity type impurity and the second conductivity type impurity.
The semiconductor is characterized in that the concentration difference is two times or more.
The device. (2) Temperature coefficient of the first conductivity type polycrystalline silicon resistor
And the temperature coefficient difference between the second conductivity type polycrystalline silicon resistor
Is 5 times or more, and the absolute value of either temperature coefficient is
Semiconductors characterized by 1000ppm / ° C or less
Body device. (3) The first conductive type polycrystalline silicon resistor and the second
The film thickness of the conductive type polycrystalline silicon resistor is 1000Å
A semiconductor device characterized by a film thickness not exceeding
Was. (4) The first conductivity type polycrystalline silicon resistor or before
Reverse conduction to either of the second conductivity type polycrystalline silicon resistors.
A semiconductor device characterized by containing electric type impurities
Was. (5) a step of forming an oxide film on a semiconductor substrate, and the acid
First polycrystalline silicon of 2000 Å ~ 5000 Å on the chemical film
A step of forming a silicon film and forming the first polycrystalline silicon film
1 × 1019atoms / cmThreeDoping impurities with the above concentration
And a step of etching the first polycrystalline silicon film
Forming a first polycrystalline silicon film region by
The semiconductor including above the first polycrystalline silicon film region
1.2 × 10 on the surface of the substrate-8~ 3.4 × 10-7F / cmTwoConsiderable capacity
A step of forming an insulating film having 100% on the insulating film.
Process to form the second polycrystalline silicon film of Å ~ 1500Å
And the entire area of the second polycrystalline silicon film or the second polycrystalline silicon film.
Of the first conductivity type impurity in the first region of the polycrystalline silicon film of
1 x 10Fifteen~ 5 × 1019atoms / cmThreeDope
A second step in the second region of the second polycrystalline silicon film.
Second conductivity type impurities 1 × 10Fifteen~ 5 × 1019atoms / cm
ThreeDoping step and the second polycrystalline silicon film
To form a second polycrystalline silicon film region by etching
And a first region of the second polycrystalline silicon film
1 × 10 in part of19atoms / cmThreeThe above first conductivity type
A step of doping a pure material, and the second polycrystalline silicon
1 × 10 over part or all of the second area of the membrane.19atoms /
cmThreeSteps for doping impurities of the second conductivity type described above
And an intermediate layer on the insulating film and the second polycrystalline silicon film.
A step of forming an insulating film, and the first and second polycrystalline silicon
Recon and the previous intermediate insulating film on the semiconductor substrate
The process of forming the tact hole and the metal wiring in the contact hole
A method of manufacturing a semiconductor device, the method comprising: (6) Part of the first region of the second polycrystalline silicon film
To 1 × 1019atoms / cm ThreeFirst conductivity type impurities described above
Expansion of MOS transistors of the first conductivity type by doping
At the same time as the diffused region doping, the second polycrystalline silicon
1 × 10 to part or the whole of the second area of the conjunctiva19at
oms / cmThreeThe above second conductivity type impurity doping is the second
Diffusion region doping of conductive type MOS transistor
And a method for manufacturing a semiconductor device, which is the same as the above. (7) Including the upper part of the first polycrystalline silicon film region
1.2 × 10 on the surface of semiconductor substrate-8~ 3.4 × 10-7F / cmTwoEquivalent
The insulating film having a capacitance of 100 to 3000 Å
Method of manufacturing semiconductor device characterized by being a thermal oxide film
Law. (8) Including above the first polycrystalline silicon film region
1.2 × 10 on the surface of semiconductor substrate-8~ 4 x 10-7F / cmTwoSubstantial
The insulating film having a capacity is a thermal oxide film having a film thickness of 50 to 1500 Å
And a nitride film with a film thickness of 50 to 2000Å and a film thickness of 100Å or less
Semiconductor device having a laminated structure of thermal oxide films
Manufacturing method.

【０００６】本発明の半導体装置は、抵抗回路各部の機
能に応じ導電型が異なり、さらに不純物濃度の異なる２
種ないし複数種の多結晶シリコン抵抗体を使い分けるこ
とにより安価、高機能、高精度とすることができる。In the semiconductor device of the present invention, the conductivity type is different depending on the function of each part of the resistance circuit, and the impurity concentration is different.
It is possible to achieve low cost, high functionality, and high accuracy by properly using one or a plurality of types of polycrystalline silicon resistors.

【０００７】[0007]

【発明の実施の形態】以下本発明の実施例を図面に基づ
いて説明する。図１は本発明の製造方法による半導体装
置の一実施例を示す模式的断面図である。シリコン半導
体基板１０１中に基板とは逆導電型のウェル領域１０２
が形成され、さらにシリコン基板中にはシリコン基板と
逆導電型拡散層１０３、ウェル領域中にはウェルと逆導
電型の拡散層１０４を有し、多結晶シリコンゲート電極
１０６と各拡散層から成るＭＯＳトランジスターが形成
される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing one embodiment of a semiconductor device according to the manufacturing method of the present invention. A well region 102 of a conductivity type opposite to that of the substrate is formed in the silicon semiconductor substrate 101.
And a diffusion layer 103 of opposite conductivity type to the silicon substrate in the silicon substrate, a diffusion layer 104 of opposite conductivity type to the well in the well region, and a polycrystalline silicon gate electrode 106 and each diffusion layer. A MOS transistor is formed.

【０００８】一方、フィールド酸化膜１０５上には第１
の導電型である高抵抗領域１０７を有する多結晶シリコ
ン抵抗体１１４と第２の導電型である高抵抗領域１０９
を有する多結晶シリコン抵抗体１１５が形成される。各
抵抗体の両端には抵抗体の導電型と同じではあるが、ア
ルミニウム配線１１２と十分なコンタクトを取れるよう
不純物の濃度を高めた高濃度領域１０８ないし１１０を
有する。On the other hand, a first film is formed on the field oxide film 105.
And a polycrystalline silicon resistor 114 having a high resistance region 107 of the second conductivity type and a high resistance region 109 of the second conductivity type.
Forming a polycrystalline silicon resistor 115. Both ends of each resistor have high-concentration regions 108 to 110, which have the same conductivity type as that of the resistor but have a high impurity concentration so as to make sufficient contact with the aluminum wiring 112.

【０００９】図１において、ＭＯＳトランジスターのゲ
ート電極である多結晶シリコン１０６と多結晶シリコン
抵抗体１１４、１１５の膜厚は異なり、多結晶シリコン
抵抗体の方が薄く設定されている。たとえば、ゲート電
極１０６は４０００Å、多結晶シリコン抵抗体１１４、
１１５は１０００Åに設定される。これは多結晶シリコ
ン抵抗体においては膜厚は薄い方がシート抵抗値を高く
設定でき、精度が向上するからである。In FIG. 1, the polycrystalline silicon 106, which is the gate electrode of the MOS transistor, and the polycrystalline silicon resistors 114 and 115 have different film thicknesses, and the polycrystalline silicon resistor is set thinner. For example, the gate electrode 106 is 4000 Å, the polycrystalline silicon resistor 114,
115 is set to 1000Å. This is because in a polycrystalline silicon resistor, the thinner the film thickness, the higher the sheet resistance value can be set, and the accuracy is improved.

【００１０】ここでさらに多結晶シリコン抵抗体の導電
型と不純物の濃度を変えることにより効果があることを
データーに基づき説明する。図２は膜厚１０００Åの多
結晶シリコンにイオン注入技術を用いて不純物導入する
際の不純物ドーズ量とシート抵抗値の関係を示した図で
ある。Ｐ型の不純物としてＢＦ２イオン、Ｎ型の不純物
としてリンを用いた例を示してある。ブリーダー抵抗部
の抵抗体に要求される特性として、ブリーダー抵抗回路
の消費電流は少なくかつ面積が小さいことが望まれるた
め、通常５ｋΩ／□から２０ｋΩ／□のシート抵抗値を
有する多結晶シリコン抵抗体が用いられるが、図２より
ＢＦ2イオンを用いた場合所望のシート抵抗値を達成す
るのが困難であることが分かる。従ってＮ型の多結晶シ
リコン抵抗体が用いられる。Here, it will be described based on data that the effect can be obtained by changing the conductivity type of the polycrystalline silicon resistor and the concentration of impurities. FIG. 2 is a diagram showing a relationship between an impurity dose amount and a sheet resistance value when impurities are introduced into polycrystalline silicon having a film thickness of 1000 Å by using an ion implantation technique. An example is shown in which BF2 ions are used as P-type impurities and phosphorus is used as N-type impurities. As the characteristics required for the resistor of the bleeder resistance part, it is desired that the bleeder resistance circuit consumes a small amount of current and has a small area. Therefore, a polycrystalline silicon resistor having a sheet resistance value of usually 5 kΩ / □ to 20 kΩ / □ 2 is used, it can be seen from FIG. 2 that it is difficult to achieve a desired sheet resistance value when BF 2 ions are used. Therefore, an N-type polycrystalline silicon resistor is used.

【００１１】図３は膜厚１０００Åの多結晶シリコンに
不純物としてＰ型はＢＦ２、Ｎ型はリンを用いた場合の
シート抵抗値と温度係数の関係を示した図である。Ｎ型
の多結晶シリコン抵抗体ではシート抵抗が１０ｋΩ／□
程度のとき、温度係数は約―３０００ｐｐｍ／°Ｃであ
り、たとえばＳＷＲの発振周波数を設定する定電流部に
は温度による抵抗値変化が大きいため、適用は困難とな
っている。一方Ｐ型多結晶シリコンにおいてはＮ型に比
べ非常に小さい温度係数を有し、また比較的高い抵抗値
に設定可能であり、例えばシート抵抗値が１ｋΩ／□程
度であり温度係数が絶対値で３００ｐｐｍ／°Ｃ以下で
あれば上記ＳＷＲの定電流部を構成する抵抗回路の抵抗
体として十分適用可能である。FIG. 3 is a diagram showing the relationship between the sheet resistance and the temperature coefficient when BF2 is used for the P type and phosphorus is used for the N type as impurities in polycrystalline silicon having a film thickness of 1000 liters. N-type polycrystalline silicon resistor has a sheet resistance of 10 kΩ / □
The temperature coefficient is about −3000 ppm / ° C., and the constant current part for setting the oscillation frequency of the SWR, for example, has a large change in resistance value with temperature, which makes it difficult to apply. On the other hand, P-type polycrystalline silicon has a temperature coefficient much smaller than that of N-type and can be set to a relatively high resistance value. For example, the sheet resistance value is about 1 kΩ / □ and the temperature coefficient is an absolute value. If it is 300 ppm / ° C or less, it can be sufficiently applied as a resistor of a resistor circuit that constitutes the constant current portion of the SWR.

【００１２】また製造する際に、後にＰ型となる多結晶
シリコン抵抗体に予めＮ型抵抗体領域のシート抵抗値を
設定するリンも同時に不純物導入し、後からＰ型不純物
であるＢＦ2だけを選択的にＰ型多結晶シリコン抵抗体
に導入することで効率よくシート抵抗値を上げることが
可能となる。例えばＮ型多結晶シリコン抵抗体のシート
抵抗値を１０ｋΩ／□に設定すべく、リンのドーズ量を
３×１０14atoms/cm2イオン注入法によりＮ型、Ｐ型両
域に不純物導入し、後にＰ型抵抗体領域への不純物導入
を工程簡略のためＰＭＯＳのソース、ドレイン領域形成
と同時に行い、その時のＢＦ2ドーズ量が５×１０15ato
ms/cm2であった場合、Ｐ型多結晶シリコン抵抗体のシー
ト抵抗値は約１ｋΩ／□であり温度係数−３００ｐｐｍ
／°Ｃとなる。Further, during manufacturing, phosphorus which sets the sheet resistance value of the N-type resistor region in advance is also introduced into the P-type polycrystalline silicon resistor at the same time, and only BF 2 which is a P-type impurity is later introduced. It is possible to efficiently increase the sheet resistance value by selectively introducing P into the P-type polycrystalline silicon resistor. For example, in order to set the sheet resistance value of the N-type polycrystalline silicon resistor to 10 kΩ / □, the phosphorus dose amount is 3 × 10 14 atoms / cm 2 by ion implantation, impurities are introduced into both N-type and P-type regions, and then P-type Impurities are introduced into the resistor region at the same time when the source and drain regions of the PMOS are formed to simplify the process, and the BF 2 dose at that time is 5 × 10 15 ato.
When ms / cm 2 , the sheet resistance of the P-type polycrystalline silicon resistor is about 1 kΩ / □ and the temperature coefficient is -300 ppm.
/ ° C.

【００１３】次にその製造方法を図面を用いて説明す
る。図４（ａ）はシリコン基板表面に酸化膜を形成し、
後にゲート電極及び配線となる第1の多結晶シリコンを
たとえば４０００ÅＣＶＤ法（ＣｈｅｍｉｃａｌＶａｐ
ｏｒ Ｄｅｐｏｓｉｔｉｏｎ）により酸化膜上に被着
し、イオン注入ないし不純物拡散炉により不純物元素で
あるリンを約１×１０20atoms/cm3ドープし、フォトリ
ソグラフィー技術とドライエッチング法によりゲート電
極１０６をパターニングした様子を示している。Next, the manufacturing method will be described with reference to the drawings. FIG. 4A shows that an oxide film is formed on the surface of a silicon substrate,
The first polycrystalline silicon, which will be the gate electrode and the wiring later, is formed by, for example, 4000 Å CVD method (Chemical Vap).
or Deposition) is applied on the oxide film, and phosphorus, which is an impurity element, is doped at about 1 × 10 20 atoms / cm 3 by an ion implantation or impurity diffusion furnace, and the gate electrode 106 is patterned by photolithography and dry etching. Shows.

【００１４】次に図４（ｂ）に示す様に熱酸化法によ
り、たとえば第１の多結晶シリコン上において５００Å
の膜厚となるように酸化膜１１６を形成し、次にＣＶＤ
法もしくはスパッタ法により、例えば、１０００Åの膜
厚の第２の多結晶シリコンを被着し、さらに第１の導電
型であるＮ型不純物リンをイオン注入法により所望のシ
ート抵抗値を得るべくドーピングする。例えば、シート
抵抗値を１０ｋΩ／□に設定するならば、３×１０14at
oms/cm2のドーズ量で行う。この際、第２の多結晶シリ
コン１０７は全域に渡りＮ型不純物であるリンがドープ
されている。尚、Ｎ型不純物としてリンのかわりに砒素
を用いてもかまわない。また第１の多結晶シリコン上の
絶縁膜１１６は熱酸化膜以外に高品質なキャパシター形
成を目的として、たとえば３００Åの膜厚の熱酸化膜、
５００Åの膜厚のＣＶＤ法による窒化膜、１０Å程度の
膜厚の熱酸化膜からなる積層構造である絶縁膜を用いて
もかまわない。Next, as shown in FIG. 4 (b), by thermal oxidation, for example, 500 Å on the first polycrystalline silicon.
Oxide film 116 is formed to have a film thickness of
Method or sputtering method, for example, a second polycrystalline silicon film having a film thickness of 1000 Å is deposited, and then N-type impurity phosphorus of the first conductivity type is ion-implanted to obtain a desired sheet resistance value. To do. For example, if the sheet resistance value is set to 10 kΩ / □, 3 × 10 14 at
Perform at a dose of oms / cm 2 . At this time, the second polycrystalline silicon 107 is entirely doped with phosphorus, which is an N-type impurity. Arsenic may be used instead of phosphorus as the N-type impurity. In addition to the thermal oxide film, the insulating film 116 on the first polycrystalline silicon is, for the purpose of forming a high quality capacitor, a thermal oxide film having a film thickness of, for example, 300 Å,
A 500 Å-thick nitride film formed by the CVD method may be used, and an insulating film having a laminated structure of a 10 Å-thick thermal oxide film may be used.

【００１５】次に図４（ｃ）に示す様にフォトリソグラ
フィー法により、後に第２導電型、即ちＰ型抵抗体とな
る領域上を開口するようにフォトレジスト１１７をパタ
ーニングし、Ｐ型不純物であるＢＦ2をイオン注入法に
よりたとえばドーズ量１×１０15atoms/cm2ドープす
る。 ＢＦ2イオンの代わりにボロンイオンを用いてもよ
い。この際、本領域には既にＮ型不純物であるリンがド
ープされており、逆導電型であるＰ型抵抗体を安定して
形成するために少なくともドーズ量において図４（ｂ）
におけるリンのドーズ量より２倍以上の値に設定する必
要がある。Next, as shown in FIG. 4C, the photoresist 117 is patterned by a photolithography method so as to have an opening above a region to be a second conductivity type, that is, a P-type resistor later. A certain amount of BF 2 is doped by ion implantation, for example, with a dose of 1 × 10 15 atoms / cm 2 . Boron ions may be used instead of BF 2 ions. At this time, this region is already doped with phosphorus, which is an N-type impurity, so that at least a dose amount is required in order to stably form a P-type resistor having an opposite conductivity type, as shown in FIG.
It is necessary to set the value to twice or more than the dose amount of phosphorus in the above.

【００１６】図４（ｄ）はフォトリソグラフィー法とド
ライエッチング法により第２の多結晶シリコンをパター
ニングした様子を示している。１０７は第１導電型であ
るＮ型多結晶シリコン抵抗領域であり、１０９は第２導
電型であるＰ型多結晶シリコン抵抗領域である。次に図
４（ｅ）に示す様に、フォトリソグラフィー法により第
１導電型のＭＯＳトランジスターの拡散領域１０３と第
１導電型の第２多結晶シリコン抵抗体１０７のアルミニ
ウム配線と十分なコンタクトをとるために高不純物濃度
領域１０８とするための領域上を開口するようにフォト
レジスト１１８をパターニングし、Ｎ型の不純物である
砒素をイオン注入法によりドーズ量５×１０15atoms/cm
2でドープする。次にフォトレジスト１１８を取り去っ
た後、図４（ｆ）に示す様にフォトリソグラフィー法に
より第２導電型のＭＯＳトランジスターの拡散領域１０
４と第２導電型の第２多結晶シリコン抵抗体１０９のア
ルミニウム配線と十分なコンタクトをとるために高不純
物濃度領域１１０とするための領域上を開口するように
フォトレジスト１１９をパターニングし、Ｐ型の不純物
であるＢＦ２をイオン注入法によりドーズ量５×１０15
atoms/cm2でドープする。FIG. 4D shows a state in which the second polycrystalline silicon is patterned by the photolithography method and the dry etching method. 107 is an N-type polycrystalline silicon resistance region of the first conductivity type, and 109 is a P-type polycrystalline silicon resistance region of the second conductivity type. Next, as shown in FIG. 4E, a sufficient contact is made with the diffusion region 103 of the first conductivity type MOS transistor and the aluminum wiring of the first conductivity type second polycrystalline silicon resistor 107 by photolithography. Therefore, the photoresist 118 is patterned so as to have an opening above the region for forming the high impurity concentration region 108, and arsenic, which is an N-type impurity, is dosed by the ion implantation method at a dose of 5 × 10 15 atoms / cm 3.
Dope with 2 . Next, after removing the photoresist 118, the diffusion region 10 of the second conductivity type MOS transistor is formed by photolithography as shown in FIG.
4 and the second conductivity type second polycrystalline silicon resistor 109 aluminum wiring is sufficiently patterned, the photoresist 119 is patterned so as to have an opening above a region for forming the high impurity concentration region 110, and P Type impurity of BF2 by ion implantation method with a dose of 5 × 10 15
Dope with atoms / cm 2 .

【００１７】この後、中間絶縁膜を被着し、コンタクト
孔を形成し、アルミニウム配線パターンを形成して半導
体装置が形成される。以上が本発明による半導体装置の
製造方法であるが、さらに簡略化のために図４（ｃ）に
おける第２多結晶シリコン抵抗体へのＰ型不純物導入を
省略して、代わりに図４（ｆ）においてＰ型不純物導入
を行う際、Ｐ型第２多結晶シリコン抵抗体全域へドーピ
ングするようにしても条件設定により所望の特性が得ら
れる。例えば、Ｎ型第２多結晶シリコン抵抗体へのリン
のドーズ量が３×１０14atoms/cm2であり、Ｐ型の第２
多結晶シリコン抵抗体へのＢＦ2のドーズ量を５×１０
15atoms/cm2で行うとＰ型第２多結晶シリコン抵抗体の
シート抵抗値は約１ｋΩ／□であり、温度係数は−３０
０ｐｐｍ／°Ｃ程度となり抵抗体として十分な特性を有
することができる。After that, an intermediate insulating film is deposited, contact holes are formed, and an aluminum wiring pattern is formed to form a semiconductor device. The above is the method for manufacturing a semiconductor device according to the present invention, but for the sake of simplicity, the introduction of P-type impurities into the second polycrystalline silicon resistor in FIG. When the P-type impurity is introduced in (4), desired characteristics can be obtained by setting the conditions even if the entire P-type second polycrystalline silicon resistor is doped. For example, the dose of phosphorus to the N-type second polycrystalline silicon resistor is 3 × 10 14 atoms / cm 2 , and the P-type second
The dose of BF 2 to the polycrystalline silicon resistor is 5 × 10
When performed at 15 atoms / cm 2 , the sheet resistance value of the P-type second polycrystalline silicon resistor is about 1 kΩ / □, and the temperature coefficient is −30.
It becomes about 0 ppm / ° C, and can have sufficient characteristics as a resistor.

【００１８】尚、同一導電型で不純物濃度を変えること
によりシート抵抗と温度係数を各々設定しても本発明に
比べ効率の悪いことは図２、図３より明らかである。It is clear from FIGS. 2 and 3 that even if the sheet resistance and the temperature coefficient are set by changing the impurity concentration for the same conductivity type, the efficiency is lower than that of the present invention.

【００１９】[0019]

【発明の効果】上述したように、１０００Åを越えない
膜厚の多結晶シリコン抵抗体において導電型が異なり、
また不純物濃度も異なる複数種の抵抗体を同一チップ上
に形成するという本発明の構造及びその製造方法によ
り、安価、高機能、高精度な半導体装置とすることがで
きる。As described above, in the polycrystalline silicon resistor having a film thickness not exceeding 1000 Å, the conductivity type is different,
Further, by the structure of the present invention in which a plurality of types of resistors having different impurity concentrations are formed on the same chip and the manufacturing method thereof, an inexpensive, highly functional, highly accurate semiconductor device can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体装置の一実施例を示す模式的断
面図である。FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device of the present invention.

【図２】膜厚１０００Åの多結晶シリコンにイオン注入
技術を用いて不純物導入した際の不純物ドーズ量とシー
ト抵抗値の関係を示した図。FIG. 2 is a diagram showing a relationship between an impurity dose amount and a sheet resistance value when impurities are introduced into polycrystalline silicon having a film thickness of 1000 Å by using an ion implantation technique.

【図３】膜厚１０００Åの多結晶シリコンに不純物とし
てＰ型はＢＦ2、Ｎ型はリンを用いた場合のシート抵抗
値と温度係数の関係を示した図。FIG. 3 is a diagram showing a relationship between a sheet resistance value and a temperature coefficient when BF 2 is used for P type and phosphorus is used for N type as impurities in polycrystalline silicon having a film thickness of 1000 liters.

【図４】本発明の半導体装置の製造方法を示す工程順断
面図。4A to 4C are cross-sectional views in order of the steps, showing the method for manufacturing a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

１０１ シリコン基板 １０２ シリコン基板と逆導電型であるウェル層 １０３ シリコン基板と逆導電型である拡散層 １０４ ウェル層と逆導電型である拡散層 １０５ フィールド酸化膜 １０６ 多結晶シリコンゲート電極 １０７ 第１の導電型である多結晶シリコン抵抗体 １０８ 第１の導電型である高不純物濃度領域 １０９ 第２の導電型である多結晶シリコン抵抗体 １１０ 第２の導電型である高不純物濃度領域 １１１ 層間絶縁膜 １１２ アルミニウム配線 １１３ 保護膜 １１４ 第１の導電型からなる薄膜抵抗体 １１５ 第２の導電型からなる薄膜抵抗体 １１６ 絶縁膜 １１７ フォトレジスト １１８ フォトレジスト １１９ フォトレジスト Reference Signs List 101 silicon substrate 102 well layer having a conductivity type opposite to that of a silicon substrate 103 diffusion layer having a conductivity type opposite to that of a silicon substrate 104 diffusion layer having a conductivity type opposite to that of a well layer 105 field oxide film 106 polycrystalline silicon gate electrode 107 first Conductivity type polycrystalline silicon resistor 108 First conductivity type high impurity concentration region 109 Second conductivity type polycrystalline silicon resistor 110 Second conductivity type high impurity concentration region 111 Interlayer insulating film 112 Aluminum wiring 113 Protective film 114 Thin film resistor of the first conductivity type 115 Thin film resistor of the second conductivity type 116 Insulating film 117 Photoresist 118 Photoresist 119 Photoresist

フロントページの続き (72)発明者 原田 博文 千葉県千葉市美浜区中瀬１丁目８番地 セ イコー電子工業株式会社内Front Page Continuation (72) Inventor Hirofumi Harada 1-8 Nakase, Nakase, Mihama-ku, Chiba, Chiba Seiko Electronics Co., Ltd.

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 第１導電型の多結晶シリコン抵抗体およ
び第２導電型多結晶シリコン抵抗体とから構成される抵
抗回路において、該第１導電型不純物と該第２導電型不
純物のネットな濃度差が２倍以上であることを特徴とす
る半導体装置。1. A resistance circuit composed of a first-conductivity-type polycrystalline silicon resistor and a second-conductivity-type polycrystalline silicon resistor, wherein a net of the first-conductivity-type impurity and the second-conductivity-type impurity is used. A semiconductor device having a concentration difference of two times or more. 【請求項２】 前記第１導電型多結晶シリコン抵抗体の
温度係数と前記第２導電型多結晶シリコン抵抗体の温度
係数の差が５倍以上であり、かつどちらかの温度係数の
絶対値が１０００ｐｐｍ／℃以下であることを特徴とす
る請求項１記載の半導体装置。2. The difference between the temperature coefficient of the first conductivity type polycrystalline silicon resistor and the temperature coefficient of the second conductivity type polycrystalline silicon resistor is five times or more, and the absolute value of either temperature coefficient. Is 1000 ppm / ° C. or less, the semiconductor device according to claim 1. 【請求項３】 前記第１導電型多結晶シリコン抵抗体と
前記第２導電型多結晶シリコン抵抗体の膜厚はともに１
０００Åを越えない膜厚であることを特徴とする請求項
１記載の半導体装置。3. The film thicknesses of the first-conductivity-type polycrystalline silicon resistor and the second-conductivity-type polycrystalline silicon resistor are both 1.
The semiconductor device according to claim 1, wherein the film thickness is not more than 000Å. 【請求項４】 前記第１導電型多結晶シリコン抵抗体も
しくは前記第２導電型多結晶シリコン抵抗体のどちらか
には逆導電型の不純物を含むことを特徴とする請求項１
記載の半導体装置。4. The impurity of opposite conductivity type is contained in either the first conductivity type polycrystalline silicon resistor or the second conductivity type polycrystalline silicon resistor.
13. The semiconductor device according to claim 1. 【請求項５】 半導体基板上に酸化膜を形成する工程
と、 前記酸化膜上に２０００Å〜５０００Åの第１の多結晶
シリコン膜を形成する工程と、前記第１の多結晶シリコ
ン膜に１×１０19atoms/cm3以上の濃度の不純物をドー
ピングする工程と、 前記第１の多結晶シリコン膜をエッチングにより第１の
多結晶シリコン膜領域を形成する工程と、前記第１の多
結晶シリコン膜領域の上を含む前記半導体基板の表面に
１．２×１０-8〜３．４×１０-7Ｆ/cm2相当の容量を有
する絶縁膜を形成する工程と、 前記絶縁膜上に１００Å〜１５００Åの第２の多結晶シ
リコン膜を形成する工程と、 前記第２の多結晶シリコン膜の全域ないしは第２の多結
晶シリコン膜の第１の領域に第１の導電型の不純物を１
×１０15〜５×１０19atoms/cm3ドーピングする工程
と、 前記第２の多結晶シリコン膜の第２の領域に第２の導電
型の不純物を１×１０ 15〜５×１０19atoms/cm3ドーピ
ングする工程と、 前記第２の多結晶シリコン膜をエッチングにより第２の
多結晶シリコン膜領域を形成する工程と、 前記第２の多結晶シリコン膜の第１の領域の一部に１×
１０19atoms/cm3以上の第１の導電型の不純物をドーピ
ングする工程と、前記第２の多結晶シリコン膜の第２の
領域の一部ないし全域に１×１０19atoms/cm3以上の第
２の導電型の不純物をドーピングする工程と、 前記絶縁膜及び第２の多結晶シリコン膜の上に中間絶縁
膜を形成する工程と、前記第１及び第２の多結晶シリコ
ン及び前記半導体基板の上の前期中間絶縁膜にコンタク
ト孔を設ける工程と、 前記コンタクト孔に金属配線を設ける工程とからなる半
導体装置の製造方法。5. A step of forming an oxide film on a semiconductor substrate
And a first polycrystal of 2000Å to 5000Å on the oxide film.
A step of forming a silicon film, and the first polycrystalline silicon
1 × 10 on the membrane19atoms / cmThreeDoping impurities of the above concentration
And a first step of etching the first polycrystalline silicon film by etching.
A step of forming a polycrystalline silicon film region,
On the surface of the semiconductor substrate including on the crystalline silicon film region
1.2 x 10-8~ 3.4 × 10-7F / cmTwoHas considerable capacity
A step of forming an insulating film, and a second polycrystalline silicon film having a thickness of 100Å to 1500Å on the insulating film.
A step of forming a recon film, and an entire area of the second polycrystalline silicon film or a second polycrystal film.
A first conductivity type impurity in the first region of the crystalline silicon film.
× 10Fifteen~ 5 × 1019atoms / cmThreeDoping process
And a second conductive layer on the second region of the second polycrystalline silicon film.
1 x 10 type impurities Fifteen~ 5 × 1019atoms / cmThreeDopi
And a second step of etching the second polycrystalline silicon film by etching.
Forming a polycrystalline silicon film region, and forming a 1 × region on a part of the first region of the second polycrystalline silicon film.
1019atoms / cmThreeThe impurities of the first conductivity type are
And a second step of forming the second polycrystalline silicon film.
1 × 10 over part or all of the area19atoms / cmThreeThe above
A step of doping a second conductivity type impurity, and an intermediate insulating layer on the insulating film and the second polycrystalline silicon film.
Forming a film, and the first and second polycrystalline silicon
And the previous intermediate insulating film on the semiconductor substrate.
And a step of providing metal wiring in the contact hole.
A method for manufacturing a conductor device. 【請求項６】 前記第２の多結晶シリコン膜の第１の領
域の一部への１×１０19atoms/cm3以上の第１の導電型
の不純物ドーピングが第１の導電型のＭＯＳトランジス
ターの拡散領域ドーピングと同時であり、前記第２の多
結晶シリコン膜の第２の領域の一部ないし全域への１×
１０19atoms/cm3以上の第２の導電型の不純物ドーピン
グが第２の導電型のＭＯＳトランジスターの拡散領域ド
ーピングと同時であることを特徴とする請求項５記載の
半導体装置の製造方法。6. A MOS transistor of the first conductivity type in which a part of the first region of the second polycrystalline silicon film is doped with impurities of the first conductivity type of 1 × 10 19 atoms / cm 3 or more. At the same time as the diffusion region doping of the second polycrystalline silicon film, and 1 × to a part or the whole of the second region of the second polycrystalline silicon film.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the second conductivity type impurity doping of 10 19 atoms / cm 3 or more is performed simultaneously with the diffusion region doping of the second conductivity type MOS transistor. 【請求項７】 前記第１の多結晶シリコン膜領域の上を
含む前記半導体基板の表面への1.2×10-8〜3.4×10-7F/
cm2相当の容量を有する絶縁膜は膜厚１００〜３０００
Åである熱酸化膜であることを特徴とする請求項５記載
の半導体装置の製造方法。7. A 1.2 × 10 −8 to 3.4 × 10 −7 F / to the surface of the semiconductor substrate including the upper portion of the first polycrystalline silicon film region.
An insulating film having a capacity equivalent to cm 2 has a film thickness of 100 to 3000
The method for manufacturing a semiconductor device according to claim 5, wherein the thermal oxide film is Å. 【請求項８】 前記第１の多結晶シリコン膜領域の上を
含む前記半導体基板の表面への1.2×10-8〜3.4×10-7F/
cm2相当の容量を有する絶縁膜は膜厚５０〜１５００Å
の熱酸化膜と膜厚５０〜２０００Åの窒化膜と膜厚１０
０Å以下の熱酸化膜の積層構造であることを特徴とする
請求項１記載の半導体装置の製造方法。8. 1.2 × 10 −8 to 3.4 × 10 −7 F / of the surface of the semiconductor substrate including the first polycrystalline silicon film region.
An insulating film with a capacity equivalent to cm 2 has a film thickness of 50 to 1500Å
Thermal oxide film and nitride film with a thickness of 50 to 2000Å and film thickness 10
The method of manufacturing a semiconductor device according to claim 1, wherein the method has a laminated structure of thermal oxide films having a thickness of 0 Å or less.
JP9035316A 1996-03-25 1997-02-19 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3054937B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196541A (en) * 2000-01-14 2001-07-19 Fuji Electric Co Ltd Semiconductor device and manufacturing method therefor
JP2002313927A (en) * 2001-04-10 2002-10-25 Seiko Instruments Inc Semiconductor device
JP2002313940A (en) * 2001-04-10 2002-10-25 Seiko Instruments Inc Method of manufacturing semiconductor device
JP2016516303A (en) * 2013-03-13 2016-06-02 ディー スリー セミコンダクター エルエルシー Device structure and method for temperature compensation of vertical field effect device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196541A (en) * 2000-01-14 2001-07-19 Fuji Electric Co Ltd Semiconductor device and manufacturing method therefor
JP4547753B2 (en) * 2000-01-14 2010-09-22 富士電機システムズ株式会社 Manufacturing method of semiconductor device
JP2002313927A (en) * 2001-04-10 2002-10-25 Seiko Instruments Inc Semiconductor device
JP2002313940A (en) * 2001-04-10 2002-10-25 Seiko Instruments Inc Method of manufacturing semiconductor device
JP2016516303A (en) * 2013-03-13 2016-06-02 ディー スリー セミコンダクター エルエルシー Device structure and method for temperature compensation of vertical field effect device

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