JPH09249851A - Reduction of relative permittivity of polymer thin film and formation of interlaminar insulating film - Google Patents
Reduction of relative permittivity of polymer thin film and formation of interlaminar insulating filmInfo
- Publication number
- JPH09249851A JPH09249851A JP8732896A JP8732896A JPH09249851A JP H09249851 A JPH09249851 A JP H09249851A JP 8732896 A JP8732896 A JP 8732896A JP 8732896 A JP8732896 A JP 8732896A JP H09249851 A JPH09249851 A JP H09249851A
- Authority
- JP
- Japan
- Prior art keywords
- film
- diisocyanate
- polyurea
- molecular weight
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば、半導体装
置の層間絶縁膜に用いられる高分子薄膜の低比誘電率化
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing the relative dielectric constant of a polymer thin film used as, for example, an interlayer insulating film of a semiconductor device.
【０００２】[0002]
【従来の技術】従来、半導体装置の層間絶縁膜として
は、回転塗布法によるＳＯＧ（Spin onGlass)膜やＣＶ
Ｄ法（化学蒸着法：Chemical Vapor Deposition)による
ＳｉＯ2膜が主に用いられている。これらの方法によっ
て形成された層間絶縁膜の比誘電率は約４となるが、最
近はＬＳＩの高集積化の進展により層間絶縁膜の低比誘
電率化が大きな課題とされており、比誘電率が４以下の
層間絶縁膜が要求されるようになっている。2. Description of the Related Art Conventionally, as an interlayer insulating film of a semiconductor device, an SOG (Spin on Glass) film or a CV
A SiO 2 film formed by the D method (Chemical Vapor Deposition method: Chemical Vapor Deposition) is mainly used. The relative permittivity of the interlayer insulating film formed by these methods is about 4, but recently, a reduction in the relative permittivity of the interlayer insulating film has become a major issue due to the progress of high integration of LSI, and the relative permittivity is increased. An interlayer insulating film having a rate of 4 or less is required.
【０００３】このような要求に対しては、近年、プラズ
マＣＶＤ法によって形成されたＳｉＯ2 膜にフッ素を添
加したＳｉＯＦ膜が提案されており、この膜によれば層
間絶縁膜の比誘電率を３．７〜３．２程度に抑えること
ができる。In order to meet such demands, in recent years, a SiOF film obtained by adding fluorine to a SiO 2 film formed by a plasma CVD method has been proposed. According to this film, the relative dielectric constant of an interlayer insulating film is improved. It can be suppressed to about 3.7 to 3.2.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、かかる
従来技術においては、次のような問題があった。すなわ
ち、上述のプラズマＣＶＤ法によるＳｉＯＦ膜は低比誘
電率化が達成できる反面、膜の形成方法や成膜条件によ
って膜特性が大きく異なったり、膜中のフッ素の脱離や
吸湿性が大きいといった膜の不安定性により誘電率を悪
化させてしまう問題が指摘されており、将来の低比誘電
率材料としての応用は難しい状況にある。However, such a conventional technique has the following problems. That is, while the SiOF film formed by the above-mentioned plasma CVD method can achieve a low relative dielectric constant, the film characteristics greatly differ depending on the film forming method and the film forming conditions, and the desorption and the hygroscopicity of fluorine in the film are large. It has been pointed out that the dielectric constant deteriorates due to the instability of the film, and it is difficult to apply it as a low dielectric constant material in the future.
【０００５】また、プラズマを発生させるための電源や
気体又は液体状材料の供給、反応ガスを除去するための
設備などが必要となりコスト高となる。Further, a power source for generating plasma, supply of gas or liquid material, equipment for removing reaction gas, etc. are required, resulting in high cost.
【０００６】一方、回転塗布法によるＳＯＧ膜は、有機
溶媒を除去するために４００℃近傍の温度でベークし脱
水重合反応させて形成することから、水の発生や工程数
が多いなどの課題がある。On the other hand, since the SOG film formed by the spin coating method is formed by baking at a temperature near 400 ° C. to remove the organic solvent and performing a dehydration polymerization reaction, there are problems such as generation of water and a large number of steps. is there.
【０００７】本発明は、このような従来の技術の課題を
解決するためになされたもので、簡易な工程で安定した
特性を有する高分子薄膜の低比誘電率化方法及び層間絶
縁膜の形成方法を提供することを目的とするものであ
る。The present invention has been made in order to solve the problems of the prior art as described above, and a method for lowering the relative dielectric constant of a polymer thin film having stable characteristics in a simple process and forming an interlayer insulating film. It is intended to provide a method.
【０００８】[0008]
【課題を解決するための手段】本発明者等は、前記課題
を解決すべく鋭意研究を重ねた結果、蒸着重合によって
形成した低分子量のポリ尿素膜に紫外線を照射して熱処
理することにより、ポリ尿素膜の比誘電率を低下しうる
ことを見い出し、本発明を完成するに至った。Means for Solving the Problems The inventors of the present invention have conducted extensive studies to solve the above problems, and as a result, irradiating a low molecular weight polyurea film formed by vapor deposition polymerization with ultraviolet rays to perform heat treatment, It has been found that the relative permittivity of the polyurea film can be lowered, and the present invention has been completed.
【０００９】すなわち、請求項１記載の発明は、真空中
で原料モノマーとしてのジアミンとジイソシアナートと
を蒸発させ、これらを基体上で蒸着重合させて低分子量
のポリ尿素膜を形成した後、このポリ尿素膜に紫外線の
照射と熱処理を行い、架橋反応と高分子量化することに
よりポリ尿素膜の比誘電率を低下させることを特徴とす
る高分子薄膜の低比誘電率化方法である。That is, according to the first aspect of the invention, diamine and diisocyanate as raw material monomers are evaporated in a vacuum, and these are vapor-deposited and polymerized on a substrate to form a polyurea film having a low molecular weight. A method for lowering the relative dielectric constant of a polymer thin film is characterized in that the relative dielectric constant of the polyurea film is reduced by subjecting this polyurea film to irradiation of ultraviolet rays and heat treatment to crosslink and increase the molecular weight.
【００１０】この場合、原料モノマーのジアミンとして
は、4,4′-ジアミノジフェニルエーテル、4,4′-ジアミ
ノ3,3′-ジメチルジフェニルメタン、4,4′-ジアミノジ
フェニルメタン4,4′-ジアミノジフェニルサルファイド
等を用いることができ、もう一方の原料モノマーのジイ
ソシアナートとしては、4,4′-ジイソシアン酸メチレン
ジフェニル、4,4′-ジイソシアン酸3,3′-ジメチルジフ
ェニル等を用いることができる。In this case, as the starting material diamine, 4,4'-diaminodiphenyl ether, 4,4'-diamino 3,3'-dimethyldiphenylmethane, 4,4'-diaminodiphenylmethane 4,4'-diaminodiphenyl sulfide is used. Etc. can be used, and as the other raw material monomer diisocyanate, methylenediphenyl 4,4′-diisocyanate, 3,3′-dimethyldiphenyl 4,4′-diisocyanate, etc. can be used.
【００１１】特に、請求項２記載のように、ジアミンと
して、4、4'-ジアミノジフェニルメタン（ＭＤＡ）を用
い、ジイソシアナートとして、4、4'-ジフェニルメタンジ
イソシアナート（ＭＤＩ）を用いると効果的である。Particularly, when 4,4'-diaminodiphenylmethane (MDA) is used as the diamine and 4,4'-diphenylmethane diisocyanate (MDI) is used as the diisocyanate, the effect is obtained. Target.
【００１２】低比誘電率化のため照射する紫外線の波長
としては、ｉ線（３６５ｎｍ）やＫｒＦエキシマレーザ
ー（２４８ｎｍ）、ＡｒＦエキシマレーザー（１９３ｎ
ｍ）等の選択された波長のものを用いることができる。The wavelength of ultraviolet rays to be irradiated for lowering the relative dielectric constant is i-line (365 nm), KrF excimer laser (248 nm), ArF excimer laser (193n).
m) or the like having a selected wavelength can be used.
【００１３】また、熱処理の条件は、温度が２００℃程
度、時間は３０分程度で行う。この場合、処理雰囲気
は、大気又は真空中のどちらでもよい。The heat treatment is carried out at a temperature of about 200 ° C. and a time of about 30 minutes. In this case, the processing atmosphere may be air or vacuum.
【００１４】一方、請求項３記載の発明は、真空中で原
料モノマーとしてのジアミンとジイソシアナートとを蒸
発させ、これらを金属配線が形成された半導体基板上で
蒸着重合させて低分子量のポリ尿素膜を形成した後、こ
のポリ尿素膜に紫外線の照射と熱処理を行い、架橋反応
と高分子量化することにより低比誘電率の高分子薄膜を
形成することを特徴とする層間絶縁膜の形成方法であ
る。On the other hand, the invention of claim 3 evaporates diamine as a raw material monomer and diisocyanate in a vacuum, and vaporizes and polymerizes them on a semiconductor substrate on which metal wiring is formed to form a low molecular weight polyamine. After forming a urea film, this polyurea film is irradiated with ultraviolet rays and heat-treated to form a polymer thin film having a low relative dielectric constant by crosslinking reaction and increasing the molecular weight, thereby forming an interlayer insulating film. Is the way.
【００１５】この場合、請求項４記載のように、請求項
３記載の発明において、ジアミンとして、4、4'-ジアミ
ノジフェニルメタン（ＭＤＡ)を用い、ジイソシアナー
トとして、4、4'-ジフェニルメタンジイソシアナート
（ＭＤＩ)を用いることも効果的である。In this case, as described in claim 4, in the invention described in claim 3, 4,4'-diaminodiphenylmethane (MDA) is used as the diamine and 4,4'-diphenylmethanediamine is used as the diisocyanate. It is also effective to use isocyanate (MDI).
【００１６】かかる構成を有する請求項１又は２記載の
発明の場合、真空中で原料モノマーとしてのジアミン
（例えば、4、4'-ジアミノジフェニルメタン）とジイソシ
アナート（例えば、4、4'-ジフェニルメタンジイソシアナ
ート）とを蒸発させ、これらを基体上で蒸着重合させて
低分子量のポリ尿素膜を形成する。このポリ尿素膜はオ
リゴマー状の膜であり、比誘電率は約４である。そし
て、このポリ尿素膜に紫外線の照射と熱処理を行うと、
未反応末端基の反応による高分子量化と同時に尿素結合
部分が架橋反応することで尿素結合部分が変化し、比誘
電率が３前後にまで低下する。In the case of the invention according to claim 1 or 2, which has such a constitution, a diamine (for example, 4,4'-diaminodiphenylmethane) as a raw material monomer and a diisocyanate (for example, 4,4'-diphenylmethane) are used in a vacuum. Diisocyanate) and these are vapor-deposited and polymerized on the substrate to form a low molecular weight polyurea film. This polyurea film is an oligomer film and has a relative dielectric constant of about 4. Then, when the polyurea film is irradiated with ultraviolet rays and heat-treated,
At the same time as the molecular weight increases due to the reaction of the unreacted terminal groups, the urea binding portion undergoes a cross-linking reaction, whereby the urea binding portion changes and the relative dielectric constant decreases to around 3.
【００１７】そして、請求項３又は４記載の発明のよう
に、真空中で原料モノマーとしてのジアミン（例えば、
4、4'-ジアミノジフェニルメタン）とジイソシアナート
（例えば、4、4'-ジフェニルメタンジイソシアナート）と
を蒸発させ、これらを金属配線が形成された半導体基板
上で蒸着重合させて低分子量のポリ尿素膜を形成した
後、このポリ尿素膜に紫外線の照射と熱処理を行い、架
橋反応と高分子量化することによって高分子薄膜を形成
すれば、現在用いられているＳＯＧ膜やＳｉＯ2 膜より
低い比誘電率（３前後）の層間絶縁膜が得られる。Then, as in the invention according to claim 3 or 4, a diamine as a raw material monomer (for example,
4,4'-diaminodiphenylmethane) and diisocyanate (for example, 4,4'-diphenylmethane diisocyanate) are evaporated, and these are vapor-deposited and polymerized on the semiconductor substrate on which the metal wiring is formed to form a low molecular weight poly After the urea film is formed, this polyurea film is irradiated with ultraviolet rays and heat-treated to form a polymer thin film by a crosslinking reaction and a high molecular weight, so that it is lower than the SOG film or SiO 2 film currently used. An interlayer insulating film having a relative dielectric constant (about 3) can be obtained.
【００１８】このように、本発明によれば、回転塗布法
によるＳＯＧ膜のベーク工程は必要とせず、水が発生す
ることもない。さらに、プラズマＣＶＤ法によるＳｉＯ
Ｆ膜のように膜の不安定性による特性の悪化の問題は発
生せず、装置設備も簡単なもので十分である。As described above, according to the present invention, the baking process of the SOG film by the spin coating method is not necessary and water is not generated. Furthermore, SiO by plasma CVD method
Unlike the F film, the problem of deterioration of characteristics due to film instability does not occur, and simple equipment is sufficient.
【００１９】[0019]
【発明の実施の形態】以下、本発明の好ましい実施の形
態を図面を参照して詳細に説明する。図１は、本発明を
実施するためのポリ尿素膜形成装置の一例の概略構成を
示すものである。Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a schematic configuration of an example of a polyurea film forming apparatus for carrying out the present invention.
【００２０】図１に示すように、この装置においては、
第１及び第２の処理室１、２が設けられ、これら第１及
び第２の処理室１、２は、ゲートバルブ３を介して連結
されている。なお、第１及び第２の処理室１、２は、図
示しない真空ポンプ等の真空排気系に連結されている。As shown in FIG. 1, in this device,
First and second processing chambers 1 and 2 are provided, and these first and second processing chambers 1 and 2 are connected via a gate valve 3. The first and second processing chambers 1 and 2 are connected to a vacuum exhaust system such as a vacuum pump (not shown).
【００２１】第１の処理室１内には、処理すべき基板４
が基板ホルダー５によって保持される。この基板ホルダ
ー５は、第１の処理室１の外部に貫通して配置される搬
送アーム６の先端部に取り付けられている。この搬送ア
ーム６は、搬送モータ７の回転に伴って水平方向に移動
自在となるように構成されている。すなわち、搬送モー
タ７のシャフト８にネジ部が形成される一方、搬送アー
ム６の先端部にもネジ部が形成され、これらの噛み合い
によって搬送アーム６が矢印方向に移動して第２の処理
室２に入り込むように構成される。A substrate 4 to be processed is provided in the first processing chamber 1.
Is held by the substrate holder 5. The substrate holder 5 is attached to the tip of a transfer arm 6 that is arranged so as to penetrate the outside of the first processing chamber 1. The transfer arm 6 is configured to be movable in the horizontal direction as the transfer motor 7 rotates. That is, a screw portion is formed on the shaft 8 of the transfer motor 7, and a screw portion is also formed on the distal end portion of the transfer arm 6, and the transfer arm 6 moves in the direction of the arrow due to the meshing of these parts. It is configured to enter 2.
【００２２】また、第１の処理室１の下方には、エレク
トロンビーム加熱源９が配置される。このエレクトロン
ビーム加熱源９の上部には、蒸発材料１０であるアルミ
ニウムが載置される。そして、基板４とエレクトロンビ
ーム加熱源９との間には、シャッター１１が設けられ、
このシャッター１１の近傍には、基板４上に形成される
薄膜の膜厚を検出するための膜厚モニター１２が設けら
れている。An electron beam heating source 9 is arranged below the first processing chamber 1. Aluminum, which is the evaporation material 10, is placed on the electron beam heating source 9. A shutter 11 is provided between the substrate 4 and the electron beam heating source 9,
A film thickness monitor 12 for detecting the film thickness of the thin film formed on the substrate 4 is provided near the shutter 11.
【００２３】一方、第２の処理室２の下方には、２種類
のモノマーの蒸発源１３Ａ、１３Ｂが配置される。各蒸
発源１３Ａ、１３Ｂのハウジング１４Ａ、１４Ｂ内に
は、それぞれ蒸発用容器１５Ａ、１５Ｂが設けられる。
そして、各蒸発用容器１５Ａ、１５Ｂの内部には、モノ
マーＡ、Ｂがそれぞれ注入され、さらに、各蒸発用容器
１５Ａ、１５Ｂの近傍には、各モノマーＡ、Ｂを加熱す
るためのヒータ１６Ａ、１６Ｂが設けられる。また、各
蒸発源１３Ａ、１３Ｂの間には、モノマーＡ、Ｂ同士の
蒸気の混合を防止するための仕切板１７が配置される。
一方、蒸発源１３Ａ、１３Ｂの上方には、シャッター１
８が設けられ、このシャッター１８の近傍には、上述の
膜厚モニター１２が設けられている。On the other hand, below the second processing chamber 2, evaporation sources 13A and 13B of two kinds of monomers are arranged. Evaporation containers 15A and 15B are provided in the housings 14A and 14B of the evaporation sources 13A and 13B, respectively.
The monomers A and B are respectively injected into the evaporation containers 15A and 15B, and the heaters 16A for heating the monomers A and B are provided in the vicinity of the evaporation containers 15A and 15B. 16B is provided. Further, a partition plate 17 for preventing the vapors of the monomers A and B from mixing with each other is arranged between the evaporation sources 13A and 13B.
On the other hand, the shutter 1 is provided above the evaporation sources 13A and 13B.
8 is provided, and the film thickness monitor 12 is provided near the shutter 18.
【００２４】この装置を用いて基板４上にポリ尿素膜を
形成する場合には、ゲートバルブ３を開け、モーター７
を回転させて基板４を処理室２に搬送する。そして、シ
ャッター１８を閉じた状態で第２の処理室２内の圧力を
所定の値に設定し、膜圧モニター１２、１２で各原料モ
ノマーＡ、Ｂの蒸発量を測定しながらヒーター１６Ａ、
１６Ｂによって各原料モノマーＡ、Ｂを所定の温度に加
熱する。When a polyurea film is formed on the substrate 4 using this apparatus, the gate valve 3 is opened and the motor 7
Is rotated to transfer the substrate 4 to the processing chamber 2. Then, with the shutter 18 closed, the pressure in the second processing chamber 2 is set to a predetermined value, and the heater 16A, while measuring the evaporation amount of each raw material monomer A, B by the film pressure monitors 12, 12.
The raw material monomers A and B are heated to a predetermined temperature by 16B.
【００２５】次いで、各原料モノマーＡ、Ｂが所定の温
度に達して所要の蒸発量が得られた後に、シャッター１
８を開き、所定の析出速度で基板４上にポリ尿素膜を蒸
着し、堆積させた後にシャッター１８を閉じ、基板４上
でポリ尿素の重合反応を起こさせてポリ尿素膜を形成す
る。Next, after the respective raw material monomers A and B have reached a predetermined temperature to obtain a required evaporation amount, the shutter 1
8 is opened, a polyurea film is vapor-deposited on the substrate 4 at a predetermined deposition rate, and after the deposition, the shutter 18 is closed to cause a polymerization reaction of polyurea on the substrate 4 to form a polyurea film.
【００２６】その後、第２の処理室２から基板４を取り
出し、２３０ｎｍ〜５００ｎｍの波長の紫外線をポリ尿
素膜の全面に対して所定時間照射するとともに熱処理を
行い、架橋反応と高分子量化することによりポリ尿素膜
の比誘電率を低下させる。この場合、熱処理の条件は、
温度が２００℃程度、時間は３０分程度で行う。また、
処理雰囲気は、大気又は真空中のどちらでもよい。After that, the substrate 4 is taken out from the second processing chamber 2, and ultraviolet rays having a wavelength of 230 nm to 500 nm are applied to the entire surface of the polyurea film for a predetermined time and heat treatment is performed to crosslink and increase the molecular weight. Thereby lowering the relative dielectric constant of the polyurea film. In this case, the heat treatment conditions are
The temperature is about 200 ° C. and the time is about 30 minutes. Also,
The processing atmosphere may be air or vacuum.
【００２７】図２(ａ)〜(ｅ)は、本発明に係るポリ尿素
膜の蒸着重合法により半導体装置の層間絶縁膜を形成す
る工程の一例を示すものである。まず、図２(ａ)に示す
ように、半導体基板２０と、この半導体基板２０表面に
形成され、所定の位置に窓開けがされたシリコン熱酸化
膜２１と、その上に成膜され、パターニングが施された
第１層目の配線２２とを有する例えばＳｉからなる基板
３１を用意する。2A to 2E show an example of a process of forming an interlayer insulating film of a semiconductor device by a vapor deposition polymerization method of a polyurea film according to the present invention. First, as shown in FIG. 2A, a semiconductor substrate 20, a silicon thermal oxide film 21 formed on the surface of the semiconductor substrate 20 and having a window opened in a predetermined position, and a film formed thereon and patterned. A substrate 31 made of, for example, Si having the first-layer wiring 22 subjected to the above is prepared.
【００２８】この基板３１の表面に、上述の蒸着重合法
によってポリ尿素膜を所望の厚みに全面成膜して層間絶
縁膜２３を形成した後、この層間絶縁膜２３に紫外線２
４の照射と熱処理を行い(図２(ｂ))、架橋反応と高分子
量化を行う。On the surface of the substrate 31, a polyurea film is formed over the entire surface to a desired thickness by the vapor deposition polymerization method to form an interlayer insulating film 23, and then the ultraviolet ray 2 is applied to the interlayer insulating film 23.
Irradiation and heat treatment of No. 4 are performed (FIG. 2B) to carry out a crosslinking reaction and a high molecular weight.
【００２９】次いで、その層間絶縁膜２３の表面に所定
のパターニングが施されたレジスト膜２５を形成し(図
２(ｃ))、ドライエッチングを行ってレジスト膜２５の
窓開け部分に露出した層間絶縁膜２３を除去する(図２
(ｄ))。そして、上述のレジスト膜２５を除去した後、
配線薄膜を全面成膜し、パターニングを施して第２層目
の配線２６を形成する。すると、層間絶縁膜２３が除去
された窓開け部分２７で、第１層目の配線２２と第２層
目の配線２６とが電気的に接続され、その結果、多層配
線を有する半導体装置３５を得ることができる(図２
(ｅ))。Next, a resist film 25 having a predetermined pattern is formed on the surface of the interlayer insulating film 23 (FIG. 2C), and dry etching is performed to expose the interlayer exposed in the window opening portion of the resist film 25. The insulating film 23 is removed (FIG. 2
(d)). Then, after removing the resist film 25 described above,
A wiring thin film is formed on the entire surface and patterned to form the second-layer wiring 26. Then, the wiring 22 of the first layer and the wiring 26 of the second layer are electrically connected at the window opening portion 27 where the interlayer insulating film 23 is removed, and as a result, the semiconductor device 35 having the multilayer wiring is formed. Can be obtained (Fig. 2
(e)).
【００３０】本実施の形態によれば、低比誘電率化した
ポリ尿素膜によって層間絶縁膜２３を構成しているの
で、第１層目の配線２２と第２層目の配線２６との間で
形成されるコンデンサーの容量が小さくなり、半導体装
置３５の動作速度を向上させることが可能になる。According to the present embodiment, since the inter-layer insulation film 23 is composed of the polyurea film having a low relative dielectric constant, the inter-layer insulation film 23 is formed between the first layer wiring 22 and the second layer wiring 26. The capacitance of the capacitor formed in 1 becomes small, and the operation speed of the semiconductor device 35 can be improved.
【００３１】[0031]
【実施例】以下、本発明の具体的な実施例を比較例とと
もに説明する。図１に示す装置を用いて基板４上にポリ
尿素膜を形成した。まず、基板ホルダー５に、長さ７６
ｍｍ×幅２６ｍｍ×厚み１．０ｍｍの例えばコーニング
＃７０５９からなる基板４を取り付け、処理室１におい
て、蒸発材料１であるアルミニウムを７のエレクトロン
ビーム（Ｅ／Ｂ）加熱により蒸発させ、膜厚モニター１
２で蒸発速度を制御しながら基板４上に１０００オング
ストロームとなるように蒸着して下部電極を形成する。
この場合、ゲートバルブ３は閉じておき、基板４の温度
は２０℃に保ち、蒸着中の第１の処理室１内の圧力を３
×１-3 Ｐａ とした。EXAMPLES Hereinafter, specific examples of the present invention will be described together with comparative examples. A polyurea film was formed on the substrate 4 using the apparatus shown in FIG. First, in the substrate holder 5, the length 76
A substrate 4 made of, for example, Corning # 7059 having a size of mm × width 26 mm × thickness 1.0 mm is attached, and aluminum as the evaporation material 1 is evaporated by electron beam (E / B) heating of 7 in the processing chamber 1 to monitor the film thickness. 1
The lower electrode is formed on the substrate 4 by vapor deposition so that the thickness is 1000 Å while controlling the evaporation rate at 2.
In this case, the gate valve 3 is closed, the temperature of the substrate 4 is kept at 20 ° C., and the pressure in the first processing chamber 1 during the deposition is set to 3 °.
It was set to × 1 −3 Pa.
【００３２】次に、ゲートバルブ３を開け、モーター７
を回転させて基板４を処理室２に搬送し、基板４上にポ
リ尿素膜を蒸着する。この場合、ポリ尿素膜を形成する
ための原料モノマーとしては、4、4'-ジアミノジフェニ
ルメタン（ＭＤＡ）と4、4'-ジフェニルメタンジイソシ
アナート（ＭＤＩ）を用い、高真空中（３×１０-3Ｐ
ａ）においてＭＤＡは１００．０±０．１℃で、ＭＤＩ
については７０．５±０．１℃の温度で蒸発させ膜厚モ
ニター６により各モノマーの蒸発速度を制御し基板４上
にポリ尿素膜を形成した。なお、本実施例の場合、ＭＤ
ＡとＭＤＩの組成比が化学量論比で１：１となるように
制御した。Next, the gate valve 3 is opened and the motor 7
Is rotated to convey the substrate 4 to the processing chamber 2, and a polyurea film is deposited on the substrate 4. In this case, 4,4'-diaminodiphenylmethane (MDA) and 4,4'-diphenylmethane diisocyanate (MDI) were used as raw material monomers for forming the polyurea film, and they were used in a high vacuum (3 × 10 − 3 P
In a) MDA is 100.0 ± 0.1 ° C and MDI
In regard to the above, the polyurea film was formed on the substrate 4 by evaporating at a temperature of 70.5 ± 0.1 ° C. and controlling the evaporation rate of each monomer by the film thickness monitor 6. In the case of this embodiment, MD
The composition ratio of A and MDI was controlled so that the stoichiometric ratio was 1: 1.
【００３３】その後、基板４を装置から取り出し、２３
０ｎｍ〜５００ｎｍの波長の紫外線をポリ尿素膜の全面
に対して照射するとともに熱処理を行い、架橋反応と高
分子量化を行った。この場合、紫外線の照射時間は３０
分とし、熱処理の温度は２００℃とした。Then, the substrate 4 is taken out of the apparatus, and 23
The entire surface of the polyurea film was irradiated with ultraviolet rays having a wavelength of 0 nm to 500 nm, and heat treatment was performed to carry out a crosslinking reaction and a high molecular weight. In this case, the UV irradiation time is 30
And the heat treatment temperature was 200 ° C.
【００３４】紫外線の照射と熱処理後、基板４を再度処
理室１内に挿入し、上述の下部電極の場合と同様の条件
でアルミニウムを蒸着して上部電極を形成し、比誘電率
測定用の素子を作成した。この素子についてポリ尿素膜
の比誘電率を測定したところ、３．０８であった。この
場合、比誘電率の値は、横河ヒューレットパッカード社
製のマルチ・フリケンシＬＣＲメータ（モデル４２７５
Ａ）を使用して静電容量Ｃを測定し、計算によって求め
た。After the ultraviolet irradiation and the heat treatment, the substrate 4 is again inserted into the processing chamber 1, and aluminum is vapor-deposited under the same conditions as in the case of the lower electrode described above to form the upper electrode. A device was created. The relative permittivity of the polyurea film of this device was measured and found to be 3.08. In this case, the value of the relative permittivity is the multi-frequency LCR meter (model 4275) manufactured by Yokogawa Hewlett-Packard Company.
The capacitance C was measured using A) and calculated.
【００３５】一方、比較例として、実施例と同様の方法
によって上部電極及びポリ尿素膜を形成し、紫外線の照
射と熱処理をせずにポリ尿素膜上に下部電極を形成し
て、比誘電率測定用の素子を作成した。この素子につい
て実施例と同様の方法によりポリ尿素膜の比誘電率を測
定したところ、４．０前後であった。On the other hand, as a comparative example, the upper electrode and the polyurea film were formed by the same method as that of the example, and the lower electrode was formed on the polyurea film without irradiation of ultraviolet rays and heat treatment to obtain a relative dielectric constant. A device for measurement was prepared. When the relative permittivity of the polyurea film of this device was measured by the same method as in the example, it was about 4.0.
【００３６】このように、紫外線を照射したポリ尿素膜
は、照射時間３０分で誘電率が３．０８と紫外線未照射
及び非熱処理膜の４より低い値となった。このことか
ら、紫外線の照射と熱処理をすることでポリ尿素膜の比
誘電率を低下させることができること明らかになった。As described above, the polyurea film irradiated with ultraviolet rays had a dielectric constant of 3.08 at an irradiation time of 30 minutes, which was lower than that of the unirradiated ultraviolet rays film and the non-heat-treated film. From this, it was clarified that the relative permittivity of the polyurea film can be lowered by irradiating with ultraviolet rays and performing heat treatment.
【００３７】[0037]
【発明の効果】以上述べたように本発明によれば、真空
中で高分子薄膜を形成するため、溶媒を必要とすること
なく基板上に均一な膜が形成でき、また、紫外線の照射
と熱処理によって比誘電率を低くすることができる。し
たがって、本発明を用いて多層配線の層間絶縁膜を形成
すれば、半導体装置の動作速度を向上させることが可能
になる。As described above, according to the present invention, since a polymer thin film is formed in a vacuum, a uniform film can be formed on a substrate without the need for a solvent, and the irradiation of ultraviolet rays can be performed. The heat treatment can lower the relative dielectric constant. Therefore, if the interlayer insulating film of the multi-layer wiring is formed using the present invention, the operation speed of the semiconductor device can be improved.
【００３８】加えて、蒸着重合によるポリ尿素膜は、既
存のレジスト材料の同様にパターンを作成することがで
き、また、段差被覆性も優れていることなどから半導体
装置の層間絶縁膜として最適である。In addition, the polyurea film formed by vapor deposition polymerization is suitable as an interlayer insulating film of a semiconductor device because it can form a pattern like existing resist materials and has excellent step coverage. is there.
【００３９】一方、本発明によれば、回転塗布法による
ＳＯＧ膜のベーク工程を必要とせず、しかも水の発生が
ないので、工程の簡素化を図ることができる。さらに、
プラズマＣＶＤ法によるＳｉＯＦ膜の様に膜の不安定性
による特性の悪化や装置の複雑化に起因するコストアッ
プの問題を解消することができる。On the other hand, according to the present invention, the step of baking the SOG film by the spin coating method is not required and no water is generated, so that the step can be simplified. further,
It is possible to solve the problem of cost increase due to the deterioration of characteristics due to the instability of the film and the increase in complexity of the device like the SiOF film formed by the plasma CVD method.
【図１】本発明を実施するためのポリ尿素膜形成装置の
一例の概略構成図FIG. 1 is a schematic configuration diagram of an example of a polyurea film forming apparatus for carrying out the present invention.
【図２】本発明に係るポリ尿素膜の蒸着重合法により半
導体装置の層間絶縁膜を形成する工程の一例を示す工程
図FIG. 2 is a process chart showing an example of a process of forming an interlayer insulating film of a semiconductor device by a vapor deposition polymerization method of a polyurea film according to the present invention.
１…第１の処理室、２…第２の処理室、３…ゲートバル
ブ、４…基板、５…基板ホルダー、１２…膜厚モニタ
ー、１３Ａ、１３Ｂ…蒸発源、１５Ａ、１５Ｂ…蒸発用
容器、１６Ａ、１６Ｂ…ヒーター、１８…シャッター、
２０…半導体基板、２１…シリコン熱酸化膜、２２…配
線、２３…層間絶縁膜、２４…紫外線、２５…レジスト
膜、２６…配線、３１…基板、３５…半導体装置、Ａ、
Ｂ…原料モノマーDESCRIPTION OF SYMBOLS 1 ... 1st process chamber, 2 ... 2nd process chamber, 3 ... Gate valve, 4 ... Substrate, 5 ... Substrate holder, 12 ... Film thickness monitor, 13A, 13B ... Evaporation source, 15A, 15B ... Evaporation container , 16A, 16B ... Heater, 18 ... Shutter,
20 ... Semiconductor substrate, 21 ... Silicon thermal oxide film, 22 ... Wiring, 23 ... Interlayer insulating film, 24 ... UV, 25 ... Resist film, 26 ... Wiring, 31 ... Substrate, 35 ... Semiconductor device, A,
B ... Raw material monomer
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｇ０３Ｆ 7/11 Ｈ０１Ｌ 21/95 (72)発明者 浮島 禎之 茨城県つくば市東光台５−９−７ 日本真 空技術株式会社筑波超材料研究所内Continuation of front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location G03F 7/11 H01L 21/95 (72) Inventor Sadayuki Ukishima 5-9-7 Tokodai, Tsukuba, Ibaraki Japan Shin Sky Technology Co., Ltd., Tsukuba Institute for Super Materials
Claims (4)
ジイソシアナートとを蒸発させ、これらを基体上で蒸着
重合させて低分子量のポリ尿素膜を形成した後、このポ
リ尿素膜に紫外線の照射と熱処理を行い、架橋反応と高
分子量化することによりポリ尿素膜の比誘電率を低下さ
せることを特徴とする高分子薄膜の低比誘電率化方法。1. A low molecular weight polyurea film is formed by evaporating diamine and diisocyanate as raw material monomers in a vacuum and vapor-depositing and polymerizing these on a substrate, and then the polyurea film is irradiated with ultraviolet rays. And a heat treatment to reduce the relative permittivity of the polyurea film by cross-linking and increasing the molecular weight of the polyurea film.
メタン（ＭＤＡ）を用い、ジイソシアナートとして、4、
4'-ジフェニルメタンジイソシアナート（ＭＤＩ）を用
いることを特徴とする請求項１記載の高分子薄膜の低比
誘電率化方法。2. Use of 4,4′-diaminodiphenylmethane (MDA) as the diamine and 4,4′-diaminodiphenylmethane (MDA) as the diisocyanate.
4. The method for reducing the relative permittivity of a polymer thin film according to claim 1, wherein 4'-diphenylmethane diisocyanate (MDI) is used.
ジイソシアナートとを蒸発させ、これらを金属配線が形
成された半導体基板上で蒸着重合させて低分子量のポリ
尿素膜を形成した後、このポリ尿素膜に紫外線の照射と
熱処理を行い、架橋反応と高分子量化することにより低
比誘電率の高分子薄膜を形成することを特徴とする層間
絶縁膜の形成方法。3. A low molecular weight polyurea film is formed by evaporating diamine and diisocyanate as raw material monomers in a vacuum and vapor-depositing and polymerizing these on a semiconductor substrate on which metal wiring is formed. A method for forming an interlayer insulating film, which comprises forming a polymer thin film having a low relative dielectric constant by subjecting a polyurea film to irradiation of ultraviolet rays and heat treatment to cause a crosslinking reaction and a high molecular weight.
メタン（ＭＤＡ）を用い、ジイソシアナートとして、4、
4'-ジフェニルメタンジイソシアナート（ＭＤＩ）を用
いることを特徴とする請求項３記載の層間絶縁膜の形成
方法。4. A diamine is 4,4′-diaminodiphenylmethane (MDA), and a diisocyanate is 4,
The method for forming an interlayer insulating film according to claim 3, wherein 4'-diphenylmethane diisocyanate (MDI) is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8732896A JPH09249851A (en) | 1996-03-15 | 1996-03-15 | Reduction of relative permittivity of polymer thin film and formation of interlaminar insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8732896A JPH09249851A (en) | 1996-03-15 | 1996-03-15 | Reduction of relative permittivity of polymer thin film and formation of interlaminar insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09249851A true JPH09249851A (en) | 1997-09-22 |
Family
ID=13911814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8732896A Pending JPH09249851A (en) | 1996-03-15 | 1996-03-15 | Reduction of relative permittivity of polymer thin film and formation of interlaminar insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09249851A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007111092A1 (en) | 2006-03-24 | 2007-10-04 | Konica Minolta Medical & Graphic, Inc. | Transparent barrier sheet and method for producing transparent barrier sheet |
| WO2007111076A1 (en) | 2006-03-24 | 2007-10-04 | Konica Minolta Medical & Graphic, Inc. | Transparent barrier sheet and method for producing transparent barrier sheet |
| JP2009188642A (en) * | 2008-02-05 | 2009-08-20 | Nippon Kinzoku Co Ltd | Diaphragm for speaker, and manufacturing method therefor |
| JP2015048411A (en) * | 2013-09-02 | 2015-03-16 | 三井化学株式会社 | Vapor deposition polymerization material, polyurethane urea film, laminate and vapor deposition polymerization method |
| CN108630530A (en) * | 2017-03-15 | 2018-10-09 | 东京毅力科创株式会社 | The manufacturing method and vacuum treatment installation of semiconductor device |
-
1996
- 1996-03-15 JP JP8732896A patent/JPH09249851A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007111092A1 (en) | 2006-03-24 | 2007-10-04 | Konica Minolta Medical & Graphic, Inc. | Transparent barrier sheet and method for producing transparent barrier sheet |
| WO2007111076A1 (en) | 2006-03-24 | 2007-10-04 | Konica Minolta Medical & Graphic, Inc. | Transparent barrier sheet and method for producing transparent barrier sheet |
| JP2009188642A (en) * | 2008-02-05 | 2009-08-20 | Nippon Kinzoku Co Ltd | Diaphragm for speaker, and manufacturing method therefor |
| JP2015048411A (en) * | 2013-09-02 | 2015-03-16 | 三井化学株式会社 | Vapor deposition polymerization material, polyurethane urea film, laminate and vapor deposition polymerization method |
| CN108630530A (en) * | 2017-03-15 | 2018-10-09 | 东京毅力科创株式会社 | The manufacturing method and vacuum treatment installation of semiconductor device |
| CN108630530B (en) * | 2017-03-15 | 2023-02-28 | 东京毅力科创株式会社 | Method for manufacturing semiconductor device and vacuum processing apparatus |
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