JPH0922922A - Interconnection structure to pt electrode on sic - Google Patents

Interconnection structure to pt electrode on sic

Info

Publication number
JPH0922922A
JPH0922922A JP7168736A JP16873695A JPH0922922A JP H0922922 A JPH0922922 A JP H0922922A JP 7168736 A JP7168736 A JP 7168736A JP 16873695 A JP16873695 A JP 16873695A JP H0922922 A JPH0922922 A JP H0922922A
Authority
JP
Japan
Prior art keywords
electrode
layer
sic
wiring
ptsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7168736A
Other languages
Japanese (ja)
Inventor
Eiji Kamiyama
栄治 神山
Kazuhiro Fusegawa
和宏 府瀬川
Teruzo Ito
輝三 伊藤
Yasuyoshi Tomiyama
能省 富山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIKYU KANKYO SANGYO GIJUTSU
CHIKYU KANKYO SANGYO GIJUTSU KENKYU KIKO
Mitsubishi Materials Corp
Original Assignee
CHIKYU KANKYO SANGYO GIJUTSU
CHIKYU KANKYO SANGYO GIJUTSU KENKYU KIKO
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIKYU KANKYO SANGYO GIJUTSU, CHIKYU KANKYO SANGYO GIJUTSU KENKYU KIKO, Mitsubishi Materials Corp filed Critical CHIKYU KANKYO SANGYO GIJUTSU
Priority to JP7168736A priority Critical patent/JPH0922922A/en
Publication of JPH0922922A publication Critical patent/JPH0922922A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate the release of a Pt electrode from SiC without deteriorating the resistivity of the electrode when an interconnection material having heat resistance is provided at the electrode and used in a high-temperature environment. SOLUTION: The structure for interconnecting a Pt electrode 12 formed on SiC 11 is provided. An Au layer 13 and a nitride layer 14 like TiNx are sequentially formed in this order on the electrode 12, and an interconnection material 15 made of a high melting point metal like Mo, W or its silicide is connected to the layer 14.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は１５０℃以上８００℃以
下の高温下で動作する耐熱型集積回路の配線構造に関す
る。更に詳しくはＳｉＣ上に設けられたＰｔ電極への配
線構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a heat-resistant integrated circuit which operates at a high temperature of 150 ° C. to 800 ° C. More specifically, it relates to a wiring structure to a Pt electrode provided on SiC.

【０００２】[0002]

【従来の技術】従来、この種の耐熱性のある電極構造と
して、ｐ型ＳｉＣと、このＳｉＣ上のＰｔ電極と、これ
らの間に設けられ空乏領域を有するｐ型ＳｉＣのドープ
層とにより構成された抵抗性電極構造（ohmic contact
structure）が開示されている（米国特許第５，３２
３，０２２号）。この抵抗性電極構造では、ドープ層が
ｐ型ＳｉＣとＰｔ電極との間で抵抗性挙動（ohmic beha
vior）を示すに十分なｐ型のドーパント濃度を有する。
この抵抗性電極構造を高温環境下で使用すると、ＳｉＣ
とＰｔの間でＰｔＳｉxの生成反応が生じるけれども、
この反応で生じたＰｔＳｉxは電極の抵抗性を悪化させ
ない特長がある。このＰｔ電極に耐熱性のある配線材を
配線する場合に、配線材としてＭｏやＷのような高融点
金属又はそのケイ化物（silicide）が考えられる。2. Description of the Related Art Conventionally, as this kind of heat-resistant electrode structure, a p-type SiC, a Pt electrode on this SiC, and a p-type SiC doped layer having a depletion region provided between them are used. Resistive electrode structure (ohmic contact
structure) is disclosed (US Pat. No. 5,32).
3,022). In this resistive electrode structure, the doped layer has a resistive behavior between the p-type SiC and the Pt electrode.
vior) with a sufficient p-type dopant concentration.
When this resistive electrode structure is used in a high temperature environment, SiC
Although a PtSi x formation reaction occurs between Pt and Pt,
The PtSi x produced in the reaction has an advantage that does not deteriorate the resistance of the electrode. When wiring a wiring material having heat resistance to the Pt electrode, a refractory metal such as Mo or W or a silicide thereof can be considered as the wiring material.

【０００３】[0003]

【発明が解決しようとする課題】しかし、これらの配線
材をＰｔ電極に配線した場合には、高温環境下で使用す
ると、配線材成分とＰｔが反応してＰｔ電極中に配線材
成分が固溶し、更に高温環境下で使用し続けると、配線
材成分がＳｉＣとＰｔ電極の界面まで達し、電極の抵抗
性を悪化させるか、或いは電極がＳｉＣから剥離し易く
なる不具合がある。However, when these wiring materials are wired to the Pt electrode and used in a high temperature environment, the wiring material component reacts with Pt and the wiring material component is solidified in the Pt electrode. When melted and continued to be used in a high temperature environment, there is a problem that the wiring material component reaches the interface between the SiC and the Pt electrode to deteriorate the resistance of the electrode, or the electrode is easily separated from the SiC.

【０００４】例えば、ｐ型ＳｉＣ上に形成されたＰｔ電
極に配線材として高融点金属のＭｏを用いて配線する
と、Ｍｏ／Ｐｔ／ＳｉＣの構造となる。この構造が高温
環境下に曝される初期の段階では、各界面において、Ｍ
ｏ／｛Ｍｏ，Ｐｔ｝／｛ＰｔＳｉx＋Ｃ｝／ＳｉＣを生
じて４層構造となる。この段階ではＳｉＣとＰｔ電極の
界面ではＰｔＳｉxが存在するため、Ｐｔ電極の電気的
特性は損なわれない。しかし長期にわたって高温環境下
に曝されると、ＭｏはＳｉＣとＰｔ電極の界面まで到達
する。ＰｔＳｉx中のＳｉはＭｏとケイ化物を作った方
が熱力学的に安定なため、界面のＰｔＳｉx／ＳｉＣの
構造は破壊され、電気的特性が劣化する。この現象は他
の高融点金属、例えばＷ、Ｔｉ、Ｃｏ、Ｎｉ、Ｔａなど
も同様に生じる。[0004] For example, when wiring of Pt electrode formed on p-type SiC using Mo which is a refractory metal as a wiring material, a structure of Mo / Pt / SiC is obtained. At the initial stage when this structure is exposed to a high temperature environment, at each interface, M
o / {Mo, Pt} occurs a / {PtSi x + C} / SiC becomes a four-layer structure. Since at this stage the presence of PtSi x at the interface between SiC and Pt electrodes, the electrical properties of the Pt electrode is not impaired. However, when exposed to a high temperature environment for a long period of time, Mo reaches the interface between the SiC and Pt electrodes. Since Si in PtSi x is thermodynamically stable when Si is formed with Mo, the PtSi x / SiC structure at the interface is destroyed and the electrical characteristics deteriorate. This phenomenon similarly occurs with other refractory metals, such as W, Ti, Co, Ni, and Ta.

【０００５】また、ｐ型ＳｉＣ上に形成されたＰｔ電極
に配線材として高融点金属のケイ化物、例えばＷＳｉx
を用いて配線する場合には、膜のもつストレスを減少さ
せるために余剰のＳｉを一般的に含ませて、ＷＳｉ2+x
／Ｐｔ／ＳｉＣの構造にする。この場合、高温環境下に
曝される初期段階でＷＳｉ中の余剰ＳｉがＰｔと反応し
て失われ、配線材のＷＳｉ膜は膜のもつストレスにより
剥離し易くなる。これを回避するためにＷＳｉを被着す
る前のＰｔ／ＳｉＣの状態で熱処理してＰｔＳｉx／Ｓ
ｉＣにしている。しかしこの場合でもＷＳｉ膜の剥がれ
を生じない代わりに長期にわたって高温環境下に曝した
場合に、ＷとＰｔの相互拡散により上述したＭｏと同様
に電気的特性が劣化する。Further, a silicide of a refractory metal such as WSi x is used as a wiring material for a Pt electrode formed on p-type SiC.
In the case of wiring using WSi 2 + x , excess Si is generally included in order to reduce the stress of the film.
/ Pt / SiC structure. In this case, excess Si in WSi reacts with Pt and is lost in the initial stage of exposure to a high temperature environment, and the WSi film of the wiring material is easily peeled off due to the stress of the film. In order to avoid this, heat treatment is performed in the state of Pt / SiC before deposition of WSi to obtain PtSi x / S.
iC. However, even in this case, when the WSi film is not peeled off and is exposed to a high temperature environment for a long period of time, the electrical characteristics are deteriorated due to the mutual diffusion of W and Pt, as with Mo described above.

【０００６】これらの点を解消するために、上記配線材
（例えばＷＳｉx）とＰｔ電極の間にＴｉＮxのようなバ
リアメタル層を介在させて、ＷＳｉx／ＴｉＮx／Ｐｔ／
ＳｉＣの構造にすることにより、９００℃の温度下でも
ＷＳｉxとＰｔ間の反応を抑制するようにすることが試
みられた。しかしこの場合でも５５０℃程度の温度でＰ
ｔ電極が｛Ｐｔ，ＰｔＳｉx｝になって、ＷＳｉx／Ｔｉ
Ｎx／｛Ｐｔ，ＰｔＳｉx｝／ＳｉＣの構造に変化し、Ｐ
ｔの存在がＴｉＮxのバリア機能を低下させる不具合が
あった。本発明の目的は、Ｐｔ電極に耐熱性のある配線
材を設けて高温環境下で使用したときに、Ｐｔ電極の抵
抗性を悪化させず、かつＰｔ電極がＳｉＣから剥離しな
いＳｉＣ上のＰｔ電極への配線構造を提供することにあ
る。In order to solve these problems, a barrier metal layer such as TiN x is interposed between the wiring material (for example, WSi x ) and the Pt electrode, and WSi x / TiN x / Pt /
An attempt was made to suppress the reaction between WSi x and Pt even at a temperature of 900 ° C. by adopting a structure of SiC. However, even in this case, at a temperature of about 550 ° C, P
The t electrode becomes {Pt, PtSi x }, and WSi x / Ti
Change to a structure of N x / {Pt, PtSi x } / SiC, P
There is a problem that the presence of t deteriorates the barrier function of TiN x . An object of the present invention is to provide a Pt electrode with a heat-resistant wiring material and not to deteriorate the resistance of the Pt electrode and to prevent the Pt electrode from peeling off from the SiC when used in a high temperature environment. To provide a wiring structure to the.

【０００７】[0007]

【課題を解決するための手段】請求項１に係る発明は、
図１に示すようにＳｉＣ１１上に形成されたＰｔ電極１
２に配線する構造の改良であって、このＰｔ電極１２上
にＡｕ層１３と窒化物層１４とがこの順に形成され、こ
の窒化物層１４に高融点金属又はそのケイ化物からなる
配線材１５が接続されたことを特徴とする。このＳｉＣ
１１はｐ型ＳｉＣ及びｎ型ＳｉＣを含むが、ｐ型ＳｉＣ
としては、α−ＳｉＣ、β−ＳｉＣのいずれでもよい。
窒化物層１４としては、ＴｉＮx，ＴａＮx，ＺｒＮx，
ＶＮx又はＨｆＮxの層が挙げられる。また高融点金属と
しては、融点が９５０℃以上のＭｏ、Ｗ、Ｔｉ、Ｃｏ、
Ｎｉ、Ｔａなどが挙げられ、高融点金属のケイ化物とし
ては、共晶温度が９５０℃以上のケイ化モリブデン、ケ
イ化タングステン、ケイ化チタン、ケイ化コバルト、ケ
イ化ニッケル、ケイ化タンタル等が例示される。Ｐｔ電
極１２の厚さは０．００１〜１μｍであることが、Ａｕ
層１３の厚さは０．１〜５μｍであることが、窒化物層
１４の厚さは０．０５〜０．３μｍであることが、また
配線材１５の厚さは０．１〜２μｍであることがそれぞ
れ好ましい。The invention according to claim 1 is
As shown in FIG. 1, a Pt electrode 1 formed on SiC 11
2 is an improvement in the structure for wiring, in which an Au layer 13 and a nitride layer 14 are formed in this order on the Pt electrode 12, and a wiring material 15 made of a refractory metal or a silicide thereof is formed on the nitride layer 14. Is connected. This SiC
11 includes p-type SiC and n-type SiC, but p-type SiC
It may be either α-SiC or β-SiC.
As the nitride layer 14, TiN x , TaN x , ZrN x ,
VN x or HfN x layers can be mentioned. Further, as the high melting point metal, Mo, W, Ti, Co having a melting point of 950 ° C. or higher,
Ni, Ta and the like are mentioned, and examples of the silicide of the refractory metal include molybdenum silicide, eutectic temperature of 950 ° C. or higher, tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, tantalum silicide and the like. It is illustrated. The Pt electrode 12 has a thickness of 0.001 to 1 μm.
The layer 13 has a thickness of 0.1 to 5 μm, the nitride layer 14 has a thickness of 0.05 to 0.3 μm, and the wiring member 15 has a thickness of 0.1 to 2 μm. It is preferable that each is present.

【０００８】請求項２に係る発明は、この窒化物層１４
がＴｉＮx層であることを特徴とする。よりバリア性が
高いからである。The invention according to claim 2 relates to the nitride layer 14
Is a TiN x layer. This is because the barrier property is higher.

【０００９】請求項３に係る発明は、この高融点金属が
Ｍｏ又はＷであることを特徴とする。より耐熱性が高い
ためである 請求項４に係る発明は、この高融点金属のケイ化物がＭ
ｏＳｉx又はＷＳｉxであることを特徴とする。やはり耐
熱性が高いためである。The invention according to claim 3 is characterized in that the refractory metal is Mo or W. This is because the heat resistance is higher, and in the invention according to claim 4, the silicide of the refractory metal is M
oSi x or WSi x . After all, it has high heat resistance.

【００１０】請求項５に係る発明は、図３に示すように
ＳｉＣ２１上に形成されたＰｔ電極２２に配線する構造
の改良であって、このＰｔ電極２２上にＡｕ層２３が形
成され、このＡｕ層２３にＡｕからなるボンディングワ
イヤからなる配線材２５が接続されたことを特徴とす
る。このＳｉＣ２１も請求項１のＳｉＣ１１と同様にｐ
型ＳｉＣ及びｎ型ＳｉＣを含み、ｐ型ＳｉＣとしては、
α−ＳｉＣ、β−ＳｉＣのいずれでもよい。またＰｔ電
極２２の厚さは０．００１〜１μｍであることが、また
Ａｕ層２３の厚さは１〜５μｍであることがそれぞれ好
ましい。配線材であるボンディングワイヤ２６のワイヤ
径は０．０２５〜１ｍｍφであることが好ましい。The invention according to claim 5 is an improvement of the structure of wiring to the Pt electrode 22 formed on the SiC 21 as shown in FIG. 3, in which the Au layer 23 is formed on the Pt electrode 22. A wiring member 25 made of a bonding wire made of Au is connected to the Au layer 23. This SiC21 also has the same p value as the SiC11 of claim 1.
Including p-type SiC and n-type SiC,
Either α-SiC or β-SiC may be used. The Pt electrode 22 preferably has a thickness of 0.001 to 1 μm, and the Au layer 23 preferably has a thickness of 1 to 5 μm. The wire diameter of the bonding wire 26, which is a wiring material, is preferably 0.025 to 1 mmφ.

【００１１】請求項６に係る発明は、上記Ａｕ層１３又
はＡｕ層２３に含まれるＰｔが１０ａｔ％以下であるこ
とを特徴とする。Ａｕ層中のＰｔの含有量を１０ａｔ％
以下にすることにより、余剰のＰｔがＡｕ層に固溶さ
れ、結果として配線材１５又は２５の接合又は接続不良
が防止される。請求項７に係る発明は、上記Ａｕ層１３
又はＡｕ層２３に含まれるＣが０．０８ａｔ％以下であ
ることを特徴とする。Ａｕ層中のＣの含有量をＣのＡｕ
への固溶限界である０．０８ａｔ％以下にすることによ
り、余剰のＣが上部の配線材１５又は２５に拡散するこ
とを防ぎ、請求項６の発明と同様の効果を奏する。The invention according to claim 6 is characterized in that Pt contained in the Au layer 13 or the Au layer 23 is 10 at% or less. The content of Pt in the Au layer is 10 at%
With the following, excess Pt is solid-dissolved in the Au layer, and as a result, defective joining or connection of the wiring material 15 or 25 is prevented. The invention according to claim 7 provides the Au layer 13
Alternatively, C contained in the Au layer 23 is 0.08 at% or less. The content of C in the Au layer is changed to Au of C.
By setting the solid solution limit to 0.08 at% or less, the excessive C is prevented from diffusing into the upper wiring member 15 or 25, and the same effect as the invention of claim 6 is achieved.

【００１２】請求項８に係る発明は、図２及び図４に示
すようにＰｔ電極１２又は２２がＰｔＳｉx層１２ａ又
は２２ａを介してＳｉＣ１１又は２２上に形成されたこ
とを特徴とする。このＰｔＳｉx層はその形成方法に応
じて０．００５〜２μｍの厚さに形成される。The invention according to claim 8 is characterized in that, as shown in FIGS. 2 and 4, the Pt electrode 12 or 22 is formed on the SiC 11 or 22 via the PtSi x layer 12a or 22a. This PtSi x layer is formed to a thickness of 0.005 to 2 μm depending on the forming method.

【００１３】[0013]

【作用】ＳｉＣ上のＰｔ電極と耐熱性のある配線材との
間にＡｕ層を介在させることにより、高温使用環境下に
おいても、Ａｕ層を構成するＡｕが不活性な元素である
ため、Ａｕ層がバリア層として作用し、配線材がＳｉＣ
とＰｔ電極の界面まで到達せず、その界面に形成される
ＰｔＳｉxを分解せず、界面を安定に保つ。またＳｉＣ
上にＰｔ電極を形成したときに生じた余剰の反応生成物
であるＰｔやＣがＡｕ層に固溶されるために、ＳｉＣと
Ｐｔ電極の界面におけるＰｔＳｉx／ＳｉＣの構造が安
定化し、電気的特性も劣化しない。By interposing the Au layer between the Pt electrode on SiC and the heat-resistant wiring material, Au constituting the Au layer is an inactive element even under a high temperature use environment. Layer acts as a barrier layer and the wiring material is SiC
Does not reach the interface between the Pt electrode and the Pt electrode, does not decompose PtSi x formed at the interface, and keeps the interface stable. Also SiC
Excessive reaction products Pt and C generated when the Pt electrode is formed on the Au layer are solid-solved in the Au layer, so that the structure of PtSi x / SiC at the interface between the SiC and the Pt electrode is stabilized, and the PtSi x / SiC structure is stabilized. Characteristics do not deteriorate.

【００１４】図１及び図２に示すように、Ａｕ層１３上
に更に窒化物層１４を積層して配線材１５を接合すれ
ば、よりバリア性が高まり、配線材１５の配線不良が解
消される。図３及び図４に示すように、Ａｕ層２３の厚
さを１μｍ程度にすれば、窒化物層を設けることなく、
Ａｕからなるボンディングワイヤ２５を直接接続するこ
とができる。図示しないが、ＳｉＣ上のＰｔ電極に直接
Ａｕからなる配線材を配線することもできる。As shown in FIGS. 1 and 2, if a nitride layer 14 is further laminated on the Au layer 13 and the wiring material 15 is bonded thereto, the barrier property is further enhanced and the wiring failure of the wiring material 15 is eliminated. It As shown in FIGS. 3 and 4, if the thickness of the Au layer 23 is about 1 μm, the nitride layer is not provided,
The bonding wire 25 made of Au can be directly connected. Although not shown, a wiring material made of Au can be directly wired to the Pt electrode on SiC.

【００１５】[0015]

【実施例】次に、本発明の実施例を比較例とともに説明
する。 ＜実施例１＞図１に示すように、先ずキャリア濃度が６
×１０14／ｃｍ3のｐ型３Ｃ−ＳｉＣ基板１１上に０．
５μｍ厚のＳｉＯ2からなる絶縁膜１６を形成し、所定
の部分をエッチングした後、ＳｉＣ基板１１上に直接
０．０１μｍ厚のＰｔ電極１２を形成した。次いでこの
Ｐｔ電極１２上に同様に絶縁膜１６を形成し、所定の部
分をエッチングした後、Ｐｔ電極１２上に０．３μｍ厚
のＡｕ層１３を形成した。次にこのＡｕ層１３上に同様
に絶縁膜１６を形成し、所定の部分をエッチングした
後、Ａｕ層１３上に０．１５μｍ厚の窒化チタン（Ｔｉ
Ｎx）層１４を形成した。更にこのＴｉＮx層１４上に同
様に絶縁膜１６を形成し、所定の部分をエッチングした
後、ＴｉＮx層１４上に０．５μｍ厚のＭｏからなる配
線材１５を形成した。Ｐｔ電極１２はターゲットとして
Ｐｔを用いて、Ａｕ層１３はターゲットとしてＡｕを用
いて、それぞれアルゴン１００％の不活性ガス中でスパ
ッタリングを行うことにより形成した。ＴｉＮx層１４
はターゲットとしてＴｉを用いてアルゴンに窒素を５０
％混合したガス中で反応性スパッタリングを行うことに
より成膜した。Ｍｏからなる配線材１５はターゲットと
してＭｏを用いて、アルゴン１００％の不活性ガス中で
スパッタリングを行うことにより形成した。Next, examples of the present invention will be described together with comparative examples. Example 1 First, as shown in FIG. 1, the carrier concentration was 6
On the p-type 3C-SiC substrate 11 of × 10 14 / cm 3 , 0.
An insulating film 16 made of SiO 2 having a thickness of 5 μm was formed, a predetermined portion was etched, and then a Pt electrode 12 having a thickness of 0.01 μm was formed directly on the SiC substrate 11. Next, an insulating film 16 was similarly formed on the Pt electrode 12 and a predetermined portion was etched, and then an Au layer 13 having a thickness of 0.3 μm was formed on the Pt electrode 12. Next, an insulating film 16 is similarly formed on the Au layer 13 and a predetermined portion is etched, and then a titanium nitride (Ti) having a thickness of 0.15 μm (Ti) is formed on the Au layer 13.
The N x ) layer 14 was formed. Further, an insulating film 16 was similarly formed on the TiN x layer 14 and a predetermined portion was etched, and then a wiring member 15 made of Mo and having a thickness of 0.5 μm was formed on the TiN x layer 14. The Pt electrode 12 was formed by using Pt as a target and the Au layer 13 by using Au as a target and performing sputtering in an inert gas of 100% argon. TiN x layer 14
Uses argon as a target and 50 times as much nitrogen as argon.
% To form a film by performing reactive sputtering in a mixed gas. The wiring member 15 made of Mo was formed by using Mo as a target and performing sputtering in an inert gas of 100% argon.

【００１６】＜実施例２＞図２に示すように、実施例１
と同一の構成のＳｉＣ基板１１上に実施例１と同様にし
てＰｔ電極１２を形成した後、アルゴン１００％の不活
性ガス雰囲気下、９００℃で３０分間熱処理することに
より、ＳｉＣ基板１１とＰｔ電極１２の界面に０．０１
μｍ厚のＰｔＳｉx層１２ａを形成した。以下、実施例
１と同様にしてＰｔ電極１２上にＡｕ層１３及びＴｉＮ
x層１４をこの順に形成し、ＴｉＮx層１４上に０．５μ
ｍ厚のＷＳｉxからなる配線材１５を形成した。この配
線材１５はターゲットとしてＷＳｉx化合物を用いて、
アルゴン１００％の不活性ガス中でスパッタリングを行
うことにより形成した。<Embodiment 2> As shown in FIG.
After the Pt electrode 12 was formed on the SiC substrate 11 having the same structure as in Example 1 in the same manner as in Example 1, the Pt electrode 12 was heat-treated at 900 ° C. for 30 minutes in an inert gas atmosphere of 100% argon to remove the Pt electrode 12 from the Pt electrode. 0.01 at the interface of electrode 12
A PtSi x layer 12a having a thickness of μm was formed. Thereafter, in the same manner as in Example 1, the Au layer 13 and TiN were formed on the Pt electrode 12.
The x layer 14 is formed in this order, and 0.5 μ is formed on the TiN x layer 14.
A wiring member 15 made of mSi WSi x was formed. This wiring member 15 uses a WSi x compound as a target,
It was formed by performing sputtering in an inert gas containing 100% argon.

【００１７】＜実施例３＞図３に示すように、実施例１
と同一の構成のＳｉＣ基板２１上に実施例１と同様にし
てＰｔ電極２２を形成した後、Ｐｔ電極２２上に実施例
１と同様に絶縁膜２６を形成し、所定の部分をエッチン
グした後、Ｐｔ電極２２上に１μｍ厚のＡｕ層２３を形
成した。次にこのＡｕ層２３上にＡｕからなるボンディ
ングワイヤ２５を超音波法でボンディングすることによ
り、接続した。符号２６はＳｉＯ2からなる絶縁膜であ
る。<Embodiment 3> As shown in FIG.
After the Pt electrode 22 is formed on the SiC substrate 21 having the same structure as in the first embodiment, the insulating film 26 is formed on the Pt electrode 22 in the same manner as in the first embodiment, and a predetermined portion is etched. An Au layer 23 having a thickness of 1 μm was formed on the Pt electrode 22. Next, a bonding wire 25 made of Au was bonded on the Au layer 23 by ultrasonic wave method to connect. Reference numeral 26 is an insulating film made of SiO 2 .

【００１８】＜実施例４＞図４に示すように、実施例１
と同一の構成のＳｉＣ基板２１上にＰｔ層を形成した
後、アルゴン１００％の不活性ガス雰囲気下、９００℃
で３０分間熱処理することにより０．０１μｍ厚のＰｔ
Ｓｉx層２２ａを形成した。以下、実施例３と同様にし
て、Ｐｔ電極２２上に１μｍ厚のＡｕ層２３を形成し
た。次にこのＡｕ層２３上にＡｕからなるボンディング
ワイヤ２５を超音波法でボンディングすることにより、
接続した。Ａｕ層２３中のＰｔ及びＣの含有量はそれぞ
れ０．０１ａｔ％以下であった。<Embodiment 4> As shown in FIG.
After forming a Pt layer on the SiC substrate 21 having the same structure as the above, 900 ° C. in an inert gas atmosphere of 100% argon.
0.01 μm thick Pt by heat treatment for 30 minutes
The Si x layer 22a was formed. Hereinafter, in the same manner as in Example 3, the Au layer 23 having a thickness of 1 μm was formed on the Pt electrode 22. Next, a bonding wire 25 made of Au is bonded on the Au layer 23 by an ultrasonic method,
Connected The Pt and C contents in the Au layer 23 were each 0.01 at% or less.

【００１９】＜実施例５＞最初に成膜するＰｔの膜厚を
変えることでＡｕ層２３中のＰｔの含有量を５ａｔ％に
した以外は、実施例４と同様にしてＡｕからなるボンデ
ィングワイヤ２５を接続した。<Embodiment 5> A bonding wire made of Au was prepared in the same manner as in Embodiment 4 except that the Pt content in the Au layer 23 was changed to 5 at% by changing the film thickness of Pt to be formed first. 25 were connected.

【００２０】＜実施例６＞最初に形成するＰｔの層厚を
変えることでＡｕ層２３中のＰｔの含有量を１０ａｔ％
にした以外は、実施例４と同様にしてＡｕからなるボン
ディングワイヤ２５を接続した。 ＜比較例１＞最初に形成するＰｔの層厚を変えることで
Ａｕ層２３中のＰｔの含有量を１５ａｔ％にした以外
は、実施例４と同様にしてＡｕからなるボンディングワ
イヤ２５を接続した。 ＜比較例２＞最初に形成するＰｔの層厚を変えることで
Ａｕ層２３中のＰｔの含有量を３０ａｔ％にした以外
は、実施例４と同様にしてＡｕからなるボンディングワ
イヤ２５を接続した。<Embodiment 6> The Pt content in the Au layer 23 was changed to 10 at% by changing the thickness of the Pt layer formed first.
The bonding wire 25 made of Au was connected in the same manner as in Example 4 except that the above was adopted. Comparative Example 1 A bonding wire 25 made of Au was connected in the same manner as in Example 4 except that the Pt content in the Au layer 23 was changed to 15 at% by changing the thickness of the Pt layer formed first. . Comparative Example 2 A bonding wire 25 made of Au was connected in the same manner as in Example 4 except that the Pt content in the Au layer 23 was changed to 30 at% by changing the thickness of the Pt layer formed first. .

【００２１】＜比較試験と評価＞実施例４〜６及び比較
例１、２の配線構造について、７００℃で１００時間熱
処理し、ボンディングワイヤの接続不良率及び抵抗値の
増加率をそれぞれ測定した。接続不良率はボンディング
したＡｕワイヤ２５に引張り試験機のフックを掛けて
０．２５ｍｍ／秒の速度で引上げたときに、Ａｕワイヤ
が付いたまま配線材が電極から剥離する割合を調べるこ
とにより求めた。また抵抗値の増加率はＳｉＣ基板上に
互いに孤立した図４に示すＰｔＳｉx層２２ａ、Ｐｔ電
極２２及びＡｕ層２３からなる配線構造を２つ形成し、
その２つの配線間の抵抗値を上記熱処理の前及び後に測
定してその変化から算出した。なおこの測定値には配
線構造（ＰｔＳｉx層２２ａ〜Ａｕ層２３）内の抵抗に
加えて、ＳｉＣ基板２１と電極（ＰｔＳｉx層２２
ａ）との間の接触抵抗及びＳｉＣ基板２１自体の抵抗
が含まれるけれども、配線構造の面積を十分に大きく
し、かつ２つの配線間の距離を十分に短くすることで上
記及びの抵抗を無視した。ボンディングワイヤの接
続不良率及び抵抗値の増加率の各測定結果を表１に示
す。<Comparative Test and Evaluation> The wiring structures of Examples 4 to 6 and Comparative Examples 1 and 2 were heat-treated at 700 ° C. for 100 hours, and the connection failure rate of the bonding wire and the increase rate of the resistance value were measured. The connection failure rate is obtained by checking the rate at which the wiring material peels from the electrode with the Au wire attached when the bonded Au wire 25 is hooked by a tensile tester and pulled up at a speed of 0.25 mm / sec. It was In addition, the rate of increase of the resistance value is obtained by forming two wiring structures each including a PtSi x layer 22a, a Pt electrode 22 and an Au layer 23 shown in FIG.
The resistance value between the two wirings was measured before and after the heat treatment and calculated from the change. In addition to the resistance in the wiring structure (PtSi x layer 22 a to Au layer 23), this measured value includes the SiC substrate 21 and the electrode (PtSi x layer 22).
Although the contact resistance with a) and the resistance of the SiC substrate 21 itself are included, the above resistance is ignored by sufficiently increasing the area of the wiring structure and sufficiently reducing the distance between the two wirings. did. Table 1 shows the respective measurement results of the connection failure rate of the bonding wire and the increase rate of the resistance value.

【００２２】[0022]

【表１】 [Table 1]

【００２３】表１から明らかなように、Ａｕ層中にＰｔ
を１５ａｔ％又は３０ａｔ％含む比較例１及び２では、
ボンディングワイヤの接続不良率が３８〜５５％と極め
て高く、また抵抗値の増加率も３７〜７８０％と極めて
高かったのに対して、Ａｕ層中にＰｔを１０ａｔ％以下
含み、又はＣを０．０８ａｔ％以下含む実施例４〜６で
は、ボンディングワイヤの接続不良率は１％未満と極め
て低く、また抵抗値の増加率も８％未満と極めて低かっ
た。実施例４〜６の結果が優れているのは、これらの配
線構造を７００℃の高温環境下で１００時間熱処理した
ときに、Ａｕ層の下層において未反応で残存していたＰ
ｔがＡｕ層に固溶して電極構造を安定化するためと考え
られる。As is clear from Table 1, Pt is contained in the Au layer.
In Comparative Examples 1 and 2 containing 15 at% or 30 at%,
The bonding failure rate of the bonding wire was extremely high at 38 to 55%, and the increase rate of the resistance value was also extremely high at 37 to 780%, while Pt was contained at 10 at% or less in the Au layer, or C was 0. In Examples 4 to 6 containing 0.08 at% or less, the connection failure rate of the bonding wire was extremely low, less than 1%, and the increase rate of the resistance value was also extremely low, less than 8%. The results of Examples 4 to 6 are excellent because when these wiring structures were heat-treated in a high temperature environment of 700 ° C. for 100 hours, P remained unreacted in the lower layer of the Au layer.
It is considered that t is a solid solution in the Au layer to stabilize the electrode structure.

【００２４】＜実施例８＞図４に示すように、実施例１
と同一の構成のＳｉＣ基板２１上に実施例１と同様にし
て０．０３μｍ厚のＰｔ電極２２を形成した後、１％Ｈ
2／９９％Ｎ2ガス中、９００℃で３０分間熱処理して、
ＰｔＳｉx層２２ａを形成した。次いでこのＰｔＳｉx層
２２ａ上に０．２μｍ厚のＡｕ層２３を形成した。この
状態で１％Ｈ2／９９％Ｎ2ガス中、７００℃で１０時間
熱処理した後、表面分析法であるオージェ分析法により
電極の表面から深さ方向の組成を調べた。その結果を図
５に示す。図５において、横軸はアルゴンガスのスパッ
タリング時間を、縦軸はオージェ電子により検出される
各元素の信号強度をそれぞれ示す。図５のＡ部から明ら
かなように、ＰｔＳｉx層２２ａは長時間の高温環境下
においても安定してＳｉＣに接して形成されていること
が判明した。<Embodiment 8> As shown in FIG.
A Pt electrode 22 having a thickness of 0.03 μm was formed on the SiC substrate 21 having the same structure as in Example 1 in the same manner as in Example 1, and then 1% H
Heat treatment at 900 ° C for 30 minutes in 2 /99% N 2 gas,
The PtSi x layer 22a was formed. Then forming an Au layer 23 of 0.2μm thickness on the PtSi x layer 22a. In this state, heat treatment was performed at 700 ° C. for 10 hours in 1% H 2 /99% N 2 gas, and then the composition in the depth direction from the surface of the electrode was examined by Auger analysis, which is a surface analysis method. The result is shown in FIG. In FIG. 5, the horizontal axis represents the sputtering time of argon gas, and the vertical axis represents the signal intensity of each element detected by Auger electrons. As is clear from the portion A of FIG. 5, it was found that the PtSi x layer 22a was stably formed in contact with SiC even in a high temperature environment for a long time.

【００２５】[0025]

【発明の効果】以上述べたように、本発明によれば、Ｓ
ｉＣ上のＰｔ電極と耐熱性のある配線材との間にＡｕ層
を介在させることにより、高温使用環境下においても、
Ａｕ層がバリア層として作用し、配線材がＳｉＣとＰｔ
電極の界面まで到達せず、その界面に形成されるＰｔＳ
ｉxを分解せず、界面を安定に保つことができ、Ｐｔ電
極がＳｉＣから剥離しない。またＳｉＣ上にＰｔ電極を
形成したときに生じた余剰の反応生成物であるＰｔやＣ
がＡｕ層に固溶されるために、ＳｉＣとＰｔ電極の界面
におけるＰｔＳｉx／ＳｉＣの構造が安定化し、長時間
使用しても抵抗値は変化せず、電気的特性も劣化しな
い。As described above, according to the present invention, S
By interposing the Au layer between the Pt electrode on the iC and the heat resistant wiring material,
The Au layer acts as a barrier layer, and the wiring material is SiC and Pt.
PtS that does not reach the interface of the electrode and is formed at that interface
The interface can be kept stable without decomposing i x , and the Pt electrode does not peel off from the SiC. In addition, Pt and C which are excess reaction products generated when the Pt electrode is formed on SiC.
There to be dissolved in the Au layer, and structure stabilization of PtSi x / SiC at the interface between SiC and Pt electrodes, even when used for a long time without the change in resistance, even not deteriorated electrical characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明実施例１のＳｉＣ上のＰｔ電極への配線
構造の拡大断面図。FIG. 1 is an enlarged cross-sectional view of a wiring structure to a Pt electrode on SiC according to a first embodiment of the present invention.

【図２】本発明実施例２のＳｉＣ上のＰｔ電極への配線
構造の拡大断面図。FIG. 2 is an enlarged sectional view of a wiring structure to a Pt electrode on SiC according to a second embodiment of the present invention.

【図３】本発明実施例３のＳｉＣ上のＰｔ電極への配線
構造の拡大断面図。FIG. 3 is an enlarged sectional view of a wiring structure to a Pt electrode on SiC according to a third embodiment of the present invention.

【図４】本発明実施例４のＳｉＣ上のＰｔ電極への配線
構造の拡大断面図。FIG. 4 is an enlarged sectional view of a wiring structure to a Pt electrode on SiC according to a fourth embodiment of the present invention.

【図５】本発明実施例８の熱処理後の耐熱電極サンプル
のオージェ分析結果を示す図。FIG. 5 is a diagram showing Auger analysis results of heat-resistant electrode samples after heat treatment of Example 8 of the present invention.

【符号の説明】[Explanation of symbols]

１１，２１ ＳｉＣ １２，２２ Ｐｔ電極 １２ａ，２２ａ ＰｔＳｉx層 １３，２３ Ａｕ層 １４ 窒化物層 １５，２５ 配線材11,21 SiC 12,22 Pt electrodes 12a, 22a PtSi x layer 13,23 Au layer 14 Nitride layer 15,25 Wiring material

───────────────────────────────────────────────────── フロントページの続き (72)発明者 伊藤 輝三 埼玉県大宮市北袋町１丁目297番地 三菱 マテリアル株式会社総合研究所内 (72)発明者 富山 能省 埼玉県大宮市北袋町１丁目297番地 三菱 マテリアル株式会社総合研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Teruzo Ito 1-297 Kitabukuro-cho, Omiya City, Saitama Prefecture Mitsubishi Materials Corp. Research Institute (72) Inventor Noyama Toyama 1-297 Kitabukuro-cho, Omiya City, Saitama Prefecture Mitsubishi Materials Corporation, Research Institute

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 ＳｉＣ(11)上に形成されたＰｔ電極(12)
に配線する構造において、 前記Ｐｔ電極(12)上にＡｕ層(13)と窒化物層(14)とがこ
の順に形成され、前記窒化物層(14)に高融点金属又はそ
のケイ化物からなる配線材(15)が接続されたことを特徴
とするＳｉＣ上のＰｔ電極への配線構造。1. A Pt electrode (12) formed on SiC (11)
In the structure of wiring, the Au layer (13) and the nitride layer (14) are formed in this order on the Pt electrode (12), and the nitride layer (14) is made of a refractory metal or its silicide. A wiring structure to a Pt electrode on SiC, characterized in that a wiring member (15) is connected. 【請求項２】 窒化物層(14)がＴｉＮx層である請求項
１記載のＳｉＣ上のＰｔ電極への配線構造。2. The wiring structure to a Pt electrode on SiC according to claim 1, wherein the nitride layer (14) is a TiN x layer. 【請求項３】 高融点金属がＭｏ又はＷである請求項１
又は２記載のＳｉＣ上のＰｔ電極への配線構造。3. The refractory metal is Mo or W.
Alternatively, the wiring structure to the Pt electrode on SiC according to 2. 【請求項４】 高融点金属のケイ化物がＭｏＳｉx又は
ＷＳｉxである請求項１又は２記載のＳｉＣ上のＰｔ電
極への配線構造。4. The wiring structure for a Pt electrode on SiC according to claim 1, wherein the refractory metal silicide is MoSi x or WSi x . 【請求項５】 ＳｉＣ(21)上に形成されたＰｔ電極(22)
に配線する構造において、 前記Ｐｔ電極(22)上にＡｕ層(23)が形成され、前記Ａｕ
層(23)にＡｕからなるボンディングワイヤからなる配線
材(25)が接続されたことを特徴とするＳｉＣ上のＰｔ電
極への配線構造。5. A Pt electrode (22) formed on SiC (21)
In the structure in which the Au layer (23) is formed on the Pt electrode (22),
A wiring structure to a Pt electrode on SiC, characterized in that a wiring material (25) made of a bonding wire made of Au is connected to the layer (23). 【請求項６】 Ａｕ層(13,23)に含まれるＰｔが１０ａ
ｔ％以下である請求項１ないし５いずれか記載のＳｉＣ
上のＰｔ電極への配線構造。6. The Pt contained in the Au layer (13, 23) is 10a.
The SiC according to any one of claims 1 to 5, which is at most t%.
Wiring structure to the upper Pt electrode. 【請求項７】 Ａｕ層(13,23)に含まれるＣが０．０８
ａｔ％以下である請求項１ないし６いずれか記載のＳｉ
Ｃ上のＰｔ電極への配線構造。7. The C contained in the Au layer (13,23) is 0.08.
7. The Si according to claim 1, which is at% or less.
Wiring structure to Pt electrode on C. 【請求項８】 Ｐｔ電極(12,22)がＰｔＳｉx層(12a,22
a)を介してＳｉＣ(11,21)上に形成された請求項１ない
し７いずれか記載のＳｉＣ上のＰｔ電極への配線構造。8. The Pt electrode (12, 22) is a PtSi x layer (12a, 22).
The wiring structure to a Pt electrode on SiC according to claim 1, which is formed on SiC (11, 21) via a).
JP7168736A 1995-07-04 1995-07-04 Interconnection structure to pt electrode on sic Withdrawn JPH0922922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7168736A JPH0922922A (en) 1995-07-04 1995-07-04 Interconnection structure to pt electrode on sic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7168736A JPH0922922A (en) 1995-07-04 1995-07-04 Interconnection structure to pt electrode on sic

Publications (1)

Publication Number Publication Date
JPH0922922A true JPH0922922A (en) 1997-01-21

Family

ID=15873472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7168736A Withdrawn JPH0922922A (en) 1995-07-04 1995-07-04 Interconnection structure to pt electrode on sic

Country Status (1)

Country Link
JP (1) JPH0922922A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093598B2 (en) 2006-03-22 2012-01-10 Mitsubishi Electric Corporation Power semiconductor device
JP2013093574A (en) * 2011-10-26 2013-05-16 General Electric Co <Ge> Method and system for transient voltage suppressor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093598B2 (en) 2006-03-22 2012-01-10 Mitsubishi Electric Corporation Power semiconductor device
JP2012151498A (en) * 2006-03-22 2012-08-09 Mitsubishi Electric Corp Power semiconductor device
DE112007000697B4 (en) 2006-03-22 2013-11-07 Mitsubishi Electric Corp. Power semiconductor device
JP2013093574A (en) * 2011-10-26 2013-05-16 General Electric Co <Ge> Method and system for transient voltage suppressor

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