JPH09181068A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing methodInfo
- Publication number
- JPH09181068A JPH09181068A JP35008595A JP35008595A JPH09181068A JP H09181068 A JPH09181068 A JP H09181068A JP 35008595 A JP35008595 A JP 35008595A JP 35008595 A JP35008595 A JP 35008595A JP H09181068 A JPH09181068 A JP H09181068A
- Authority
- JP
- Japan
- Prior art keywords
- film
- atmosphere
- oxide film
- oxidation
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に選択酸化（いわゆるＬＯＣＯＳ（Local
Oxidation of Silicon））素子分離構造を有する半導体
製造の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to selective oxidation (so-called LOCOS (Local
Oxidation of Silicon)) The present invention relates to a method of manufacturing a semiconductor having an element isolation structure.
【０００２】[0002]
【従来の技術】半導体集積回路（ＬＳＩ）の微細化に伴
って、素子分離方法が重要な製造技術の課題の一つにな
っている。従来の素子分離領域の形成方法としては、Ｌ
ＯＣＯＳ法が一般的に広く知られている。しかしなが
ら、このＬＯＣＯＳ法によると、フィールド酸化膜がシ
リコン窒化膜に入り込んで成長し、いわゆるバーズビー
クが形成されるので、ＬＳＩの高集積化にとって大きな
障害となっている。2. Description of the Related Art With the miniaturization of semiconductor integrated circuits (LSIs), the element isolation method has become one of the important issues in the manufacturing technology. As a conventional method for forming an element isolation region, L
The OCOS method is generally widely known. However, according to the LOCOS method, the field oxide film enters the silicon nitride film and grows to form a so-called bird's beak, which is a major obstacle to high integration of the LSI.
【０００３】これを改善するために従来のＬＯＣＯＳ法
を改良したＬＯＣＯＳ法がいくつか提案されている。そ
の１つは、パッド膜としてのシリコン酸化膜と耐酸化マ
スクとしてのシリコン窒化膜との間にバッファ層として
の多結晶シリコン膜を形成し、シリコン窒化膜を所望の
形状にパターニングしてから選択酸化を行う方法（いわ
ゆるポリ・バッファーＬＯＣＯＳ法）である。この方法
は、例えば特開昭５６−７０６４４号公報、特開昭６３
−３０２５３６号公報、あるいは特開平４−３５７８３
８号公報に記載されている。In order to improve this, some LOCOS methods, which are improved conventional LOCOS methods, have been proposed. One of them is to form a polycrystalline silicon film as a buffer layer between a silicon oxide film as a pad film and a silicon nitride film as an anti-oxidation mask, pattern the silicon nitride film into a desired shape, and then select it. This is a method of performing oxidation (so-called poly-buffer LOCOS method). This method is disclosed, for example, in JP-A-56-70644 and JP-A-63.
-302536, or Japanese Patent Laid-Open No. 4-35783.
No. 8 publication.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上述した従来
のポリ・バッファーＬＯＣＯＳ法において、半導体集積
回路の高集積化に伴い、以下のような問題点が生じてい
た。つまり、半導体素子の微細化により素子分離幅が縮
小されると、フィールド酸化膜の形成時の熱処理による
応力に起因して、バッファ層の多結晶シリコン膜がグレ
イン成長し、ボイドが発生する。その後シリコン窒化膜
を熱燐酸のウェットエッチングにより除去したときに、
熱燐酸がボイド部分に入り込み、ボイド部分のシリコン
酸化膜を薄膜化させ、その結果シリコン半導体基板にピ
ンホールが形成される現象（マイクロトレンチ現象）が
生じ、半導体装置の信頼性を低下させるという問題が起
こっていた。However, in the above-mentioned conventional poly-buffer LOCOS method, the following problems have occurred with the high integration of semiconductor integrated circuits. That is, when the element isolation width is reduced due to the miniaturization of the semiconductor element, the polycrystalline silicon film of the buffer layer is grain-grown due to the stress due to the heat treatment during the formation of the field oxide film, and a void is generated. After that, when the silicon nitride film was removed by wet etching with hot phosphoric acid,
The problem that hot phosphoric acid enters the void portion and thins the silicon oxide film in the void portion, resulting in the phenomenon that pinholes are formed in the silicon semiconductor substrate (micro-trench phenomenon), which lowers the reliability of the semiconductor device. Was happening.
【０００５】本発明は、上述した問題を解決するために
なされたもので、ポリ・バッファーＬＯＣＯＳ法におけ
るマイクロトレンチ現象を抑制することが可能な半導体
装置の製造方法を提供することを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing the micro-trench phenomenon in the poly-buffer LOCOS method.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置の製造方法は、選択酸化素子分
離構造によって素子間分離がなされる半導体装置の製造
方法において、半導体基板にシリコン酸化膜と多結晶シ
リコン膜とシリコン窒化膜を順次形成する工程と、前記
シリコン窒化膜をパターニングする工程と、第１の雰囲
気中において前記半導体基板に第１の熱処理を施した
後、前記第１の雰囲気とは異なる第２の雰囲気中におい
て前記半導体基板に第２の熱処理を施す工程とを有す
る。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a semiconductor device manufacturing method in which elements are isolated by a selective oxidation element isolation structure. A step of sequentially forming an oxide film, a polycrystalline silicon film, and a silicon nitride film; a step of patterning the silicon nitride film; and a first heat treatment of the semiconductor substrate in a first atmosphere, and then the first heat treatment. And a step of performing a second heat treatment on the semiconductor substrate in a second atmosphere different from the above atmosphere.
【０００７】また、本発明では、前記第１の熱処理をド
ライ酸化雰囲気又はオゾン雰囲気で行い、前記第２の熱
処理を水蒸気酸化雰囲気で行うことが好ましい。Further, in the present invention, it is preferable that the first heat treatment is performed in a dry oxidizing atmosphere or an ozone atmosphere, and the second heat treatment is performed in a steam oxidizing atmosphere.
【０００８】本発明の一態様では、ポリ・バッファーＬ
ＯＣＯＳ法においては、通常の酸化拡散炉を用いてフィ
ールド酸化膜を形成する際に、まずドライ酸化雰囲気
（又はオゾン雰囲気）で熱処理を行い、素子分離領域に
ドライ酸化膜を形成した後、同一酸化拡散炉内で水蒸気
酸化雰囲気に切り換えることにより、所定の膜厚の素子
分離用のシリコン酸化膜であるフィールド酸化膜を形成
する。In one aspect of the invention, poly buffer L
In the OCOS method, when a field oxide film is formed using an ordinary oxidation diffusion furnace, heat treatment is first performed in a dry oxidation atmosphere (or ozone atmosphere) to form a dry oxide film in an element isolation region, and then the same oxidation is performed. By switching to the steam oxidation atmosphere in the diffusion furnace, a field oxide film, which is a silicon oxide film for element isolation, having a predetermined film thickness is formed.
【０００９】本発明によれば、フィールド酸化膜形成時
の水蒸気酸化の前に一定以上のドライ酸化雰囲気（又は
オゾン雰囲気）での熱処理工程を設け、一定の膜厚のド
ライ酸化膜を素子分離領域に形成しておくことにより、
バッファ層の多結晶シリコン膜に付加される急激な応力
の発生を防ぐことができる。その結果、多結晶シリコン
のグレイン成長が抑制でき、ボイドが発生しなくなるの
でマイクロトレンチの発生を抑制することができる。ま
た、通常の汎用型の酸化拡散炉を用いるので、コストが
増大することがない。According to the present invention, a heat treatment step in a dry oxidation atmosphere (or an ozone atmosphere) above a certain level is provided before steam oxidation during formation of a field oxide film, and a dry oxide film with a certain thickness is formed in an element isolation region. By forming in
It is possible to prevent the sudden generation of stress applied to the polycrystalline silicon film of the buffer layer. As a result, grain growth of polycrystalline silicon can be suppressed, and voids can be prevented from occurring, so that generation of micro-trench can be suppressed. Further, since a general general-purpose oxidation diffusion furnace is used, the cost does not increase.
【００１０】[0010]
【発明の実施の形態】以下、本発明の一実施形態を図面
を参照しながら説明する。An embodiment of the present invention will be described below with reference to the drawings.
【００１１】本発明者は、上記課題について研究実験を
重ねた結果、マイクロトレンチは、フィールド酸化膜形
成時の水蒸気酸化の前のドライ酸化時間に依存して発生
することを見い出した。図１に、ドライ酸化と水蒸気酸
化とを組み合わせて、一定の温度（例えば１０００℃）
で一定の膜厚（４５００Å程度）のフィールド酸化膜を
形成したときのマイクロトレンチ発生状況を示す。図１
から明らかなように、マイクロトレンチはドライ酸化時
間が長いほど抑制される傾向にあり、ドライ酸化時間が
３０分間を超えると、マイクロトレンチは発生しなくな
る。As a result of repeated research and experiments on the above problems, the present inventor has found that micro-trench occurs depending on the dry oxidation time before steam oxidation at the time of forming a field oxide film. Fig. 1 shows a combination of dry oxidation and steam oxidation at a constant temperature (for example, 1000 ° C).
Shows a micro-trench generation state when a field oxide film having a constant film thickness (about 4500 Å) is formed. FIG.
As is clear from the above, the micro-trench tends to be suppressed as the dry oxidation time becomes longer, and the micro-trench does not occur when the dry oxidation time exceeds 30 minutes.
【００１２】図２は、本発明の半導体装置の製造方法の
一実施形態を工程順に示す模式断面図である。FIG. 2 is a schematic sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention in the order of steps.
【００１３】まず、図２（ａ）に示すように、シリコン
半導体基板１上に９００℃のドライ酸化で膜厚１５０Å
程度の薄いシリコン酸化（ＳｉＯ2 ）膜２を形成する。
続いて減圧ＣＶＤ法により多結晶シリコン膜３を５００
Å程度、シリコン窒化（Ｓｉ3 Ｎ4 ）膜４を２５００Å
程度順次堆積する。First, as shown in FIG. 2A, a film thickness of 150 Å is formed on a silicon semiconductor substrate 1 by dry oxidation at 900 ° C.
A thin silicon oxide (SiO 2 ) film 2 is formed.
Then, the polycrystalline silicon film 3 is formed into 500 by the low pressure CVD method.
Å About 2500 Å of silicon nitride (Si 3 N 4 ) film 4
Deposition is carried out sequentially.
【００１４】次に、図２（ｂ）に示すように、素子活性
領域とすべき領域にシリコン窒化膜４を残すように、こ
のシリコン窒化膜４をパターニングする。Next, as shown in FIG. 2B, the silicon nitride film 4 is patterned so as to leave the silicon nitride film 4 in a region to be an element active region.
【００１５】次に、酸化拡散炉を用いて、ドライ酸化雰
囲気中において、温度１０００℃程度、６０分間の熱処
理をシリコン半導体基板１に施す。この熱処理により、
図２（ｃ）に示すように素子分離領域（シリコン窒化膜
４で被覆されていない領域）の多結晶シリコン３が膜厚
５００Å程度のドライ酸化膜６となる。Next, the silicon semiconductor substrate 1 is subjected to a heat treatment at a temperature of about 1000 ° C. for 60 minutes in a dry oxidizing atmosphere using an oxidation diffusion furnace. By this heat treatment,
As shown in FIG. 2C, the polycrystalline silicon 3 in the element isolation region (region not covered with the silicon nitride film 4) becomes a dry oxide film 6 having a film thickness of about 500Å.
【００１６】次いで、前記酸化拡散炉内の雰囲気を水蒸
気酸化雰囲気に切り換え、酸化速度を上げて、温度１０
００℃で７０分間以上の酸化処理をシリコン半導体基板
１に施す。これにより、シリコン窒化膜４で被覆されて
いない領域には、図２（ｄ）に示すような膜厚４０００
Å以上の厚いフィールド酸化（ＳｉＯ2 ）膜５が形成さ
れる。Next, the atmosphere in the oxidation diffusion furnace is switched to the steam oxidation atmosphere, the oxidation rate is increased, and the temperature is adjusted to 10
Oxidation treatment is performed on the silicon semiconductor substrate 1 at 00 ° C. for 70 minutes or more. As a result, in a region not covered with the silicon nitride film 4, a film thickness 4000 as shown in FIG.
A field oxide (SiO 2 ) film 5 thicker than Å is formed.
【００１７】次に、図２（ｅ）に示すように、熱燐酸を
用いたウェットエッチングによりシリコン窒化膜４を除
去し、その後ドライエッチングを行い、多結晶シリコン
膜３を除去する。Next, as shown in FIG. 2E, the silicon nitride film 4 is removed by wet etching using hot phosphoric acid, and then dry etching is performed to remove the polycrystalline silicon film 3.
【００１８】以上説明した実施形態では、多結晶シリコ
ン３のグレイン成長が抑制でき、ボイドが発生しなくな
るので、シリコン半導体基板１にマイクロトレンチは発
生しない。また、通常の汎用型の酸化拡散炉でフィール
ド酸化膜５を形成するため、コストが増大することもな
い。In the embodiment described above, the grain growth of the polycrystalline silicon 3 can be suppressed, and voids do not occur. Therefore, micro trenches do not occur in the silicon semiconductor substrate 1. In addition, since the field oxide film 5 is formed in a normal general-purpose oxidation diffusion furnace, the cost does not increase.
【００１９】本実施形態では、膜厚５００Å程度のドラ
イ酸化膜６を形成するためにドライ酸化雰囲気中で熱処
理を施したが、オゾン（Ｏ3 ）雰囲気中で熱処理を施し
て酸化膜を形成しても同様の結果を得ることができる。In this embodiment, the heat treatment is performed in the dry oxidation atmosphere to form the dry oxide film 6 having a film thickness of about 500 Å. However, the heat treatment is performed in the ozone (O 3 ) atmosphere to form the oxide film. However, the same result can be obtained.
【００２０】[0020]
【発明の効果】以上説明したように本発明によれば、フ
ィールド酸化膜形成時の水蒸気酸化の前にドライ酸化雰
囲気又はオゾン雰囲気での熱処理工程を設けることによ
り、バッファ層の多結晶シリコン膜に付加される急激な
応力の発生を防ぐことができる。その結果、多結晶シリ
コンのグレイン成長が抑制でき、ボイドが発生しなくな
るので、シリコン半導体基板へのピンホールの形成（マ
イクロトレンチ現象）を抑制することができる。また、
通常の汎用型の酸化拡散炉でフィールド酸化膜を形成す
るため、本方法の導入によるコストの増大は発生しな
い。As described above, according to the present invention, the polycrystalline silicon film of the buffer layer is formed by providing the heat treatment step in the dry oxidizing atmosphere or the ozone atmosphere before the steam oxidation at the time of forming the field oxide film. It is possible to prevent the generation of a sudden stress applied. As a result, grain growth of polycrystalline silicon can be suppressed, and voids do not occur, so that formation of pinholes (micro-trench phenomenon) in the silicon semiconductor substrate can be suppressed. Also,
Since the field oxide film is formed in a usual general-purpose type oxidation diffusion furnace, the cost increase due to the introduction of this method does not occur.
【図１】本発明におけるフィールド酸化膜形成時の水蒸
気酸化の前のドライ酸化時間に対するマイクロトレンチ
発生状況を示すグラフである。FIG. 1 is a graph showing a micro-trench generation state with respect to a dry oxidation time before steam oxidation in forming a field oxide film in the present invention.
【図２】本発明の一実施形態の半導体装置の製造方法を
工程順に示す断面図である。2A to 2D are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
１ シリコン半導体基板 ２ シリコン酸化膜 ３ 多結晶シリコン膜 ４ シリコン窒化膜 ５ フィールド酸化膜 ６ ドライ酸化膜 1 silicon semiconductor substrate 2 silicon oxide film 3 polycrystalline silicon film 4 silicon nitride film 5 field oxide film 6 dry oxide film
Claims (2)
離がなされる半導体装置の製造方法において、 半導体基板にシリコン酸化膜と多結晶シリコン膜とシリ
コン窒化膜を順次形成する工程と、 前記シリコン窒化膜をパターニングする工程と、 第１の雰囲気中において前記半導体基板に第１の熱処理
を施した後、前記第１の雰囲気とは異なる第２の雰囲気
中において前記半導体基板に第２の熱処理を施す工程と
を有することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which elements are isolated by a selective oxidation element isolation structure, a step of sequentially forming a silicon oxide film, a polycrystalline silicon film, and a silicon nitride film on a semiconductor substrate, the silicon nitride film. And a step of subjecting the semiconductor substrate to a first heat treatment in a first atmosphere, and then subjecting the semiconductor substrate to a second heat treatment in a second atmosphere different from the first atmosphere. A method of manufacturing a semiconductor device, comprising:
はオゾン雰囲気で行い、前記第２の熱処理を水蒸気酸化
雰囲気で行うことを特徴とする請求項１に記載の半導体
装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the first heat treatment is performed in a dry oxidizing atmosphere or an ozone atmosphere, and the second heat treatment is performed in a steam oxidizing atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35008595A JPH09181068A (en) | 1995-12-22 | 1995-12-22 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35008595A JPH09181068A (en) | 1995-12-22 | 1995-12-22 | Semiconductor device manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09181068A true JPH09181068A (en) | 1997-07-11 |
Family
ID=18408140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35008595A Withdrawn JPH09181068A (en) | 1995-12-22 | 1995-12-22 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09181068A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110162709A1 (en) * | 2008-09-15 | 2011-07-07 | Gebr. Schmid Gmbh & Co. | Method for the treatment of substrates, substrate and treatment device for carrying out said method |
-
1995
- 1995-12-22 JP JP35008595A patent/JPH09181068A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110162709A1 (en) * | 2008-09-15 | 2011-07-07 | Gebr. Schmid Gmbh & Co. | Method for the treatment of substrates, substrate and treatment device for carrying out said method |
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