JPH09134844A - Manufacture of chip type laminated ceramic capacitor - Google Patents
Manufacture of chip type laminated ceramic capacitorInfo
- Publication number
- JPH09134844A JPH09134844A JP7292368A JP29236895A JPH09134844A JP H09134844 A JPH09134844 A JP H09134844A JP 7292368 A JP7292368 A JP 7292368A JP 29236895 A JP29236895 A JP 29236895A JP H09134844 A JPH09134844 A JP H09134844A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- layers
- layer
- external electrodes
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000007747 plating Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 23
- 239000004020 conductor Substances 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract description 4
- 230000008646 thermal stress Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000006071 cream Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002003 electrode paste Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は広く電子機器回路等
に使用されるチップ形積層セラミックコンデンサの製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip type monolithic ceramic capacitor widely used in electronic equipment circuits and the like.
【０００２】[0002]
【従来の技術】近年、電子機器用部品のコンデンサ素子
としてチップ形積層セラミックコンデンサが多く使用さ
れている。しかしながら近年のビデオ業界などの電子機
器分野ではコンパクト化のための高密度化が進み、さら
に生産性向上の目的から高速実装が急速に進んでおり実
装率向上のため部品の寸法精度の向上の必要性について
述べる。2. Description of the Related Art In recent years, chip type monolithic ceramic capacitors have been widely used as capacitor elements for electronic equipment parts. However, in recent years, in the electronic equipment field such as the video industry, the density is increasing for compactness, and high-speed mounting is rapidly progressing for the purpose of improving productivity, and it is necessary to improve the dimensional accuracy of parts to improve the mounting rate. Describe sex.
【０００３】まずチップ部品の実装の第１例はチップ部
品をバラでパーツフィーダに入れ、整列させてから吸着
ノズル等で吸い上げて回路基板の所定の位置にセットす
る方法と、第２例はチップ部品の形状に合わせた筒状の
ケース（以下マガジンケースと呼ぶ）に入れ、マガジン
ケースの下方から棒で１個／ピッチずつ押し上げてから
装着部側の吸着ノズルピンで吸い上げて回路基板の所定
の位置にセットする方法と、第３例としてテープにチッ
プ部品を１ピッチずつ送る送りホルダーと、このピッチ
に合わせたチップ部品の入る有底形のホールを有しこの
中にチップ部品を入れ、上部を別のテープでカバーした
もので実装時には上部のカバーテープをめくり、露出し
たチップ部品を吸着ノズルで吸い上げて回路基板の所定
の位置にセットする方法がある。First, the first example of mounting the chip parts is to put the chip parts into the parts feeder in pieces, align them, and then pick them up with a suction nozzle or the like to set them at a predetermined position on the circuit board. Put it in a cylindrical case (hereinafter referred to as magazine case) that matches the shape of the part, push up one by one with a stick from the bottom of the magazine case / pitch, and then suck up with the suction nozzle pin on the mounting part side to a predetermined position on the circuit board Method, and as a third example, there is a feed holder that feeds the chip parts to the tape one pitch at a time, and a bottomed hole into which the chip parts that match this pitch are inserted. When mounting with another tape, flip the cover tape on the top, suck up the exposed chip parts with a suction nozzle and set it at a predetermined position on the circuit board. There is a method.
【０００４】これらはいずれも高速で行われるためチッ
プ部品の外形が起因しての実装トラブルが生じ易く大き
く実装効率に影響する。以下チップ部品外形が及ぼす影
響を説明する。Since all of these operations are performed at high speed, mounting troubles are likely to occur due to the outer shape of the chip component, which greatly affects the mounting efficiency. The influence of the outer shape of the chip component will be described below.
【０００５】図１３は第１例で述べたチップ部品１をバ
ラで実装する時のトラブルであり、チップ部品１がパー
ツフィーダ２上で斜めになり、ロックされて供給が停止
したり、又は図１４に示すように位置決め治具３で斜め
に供給されたままチップ部品１が保持されて斜め実装が
発生するものであった。FIG. 13 shows a trouble when the chip parts 1 described in the first example are mounted separately, and the chip parts 1 are inclined on the parts feeder 2 and are locked and the supply is stopped, or As shown in FIG. 14, the chip component 1 was held while being obliquely supplied by the positioning jig 3, and oblique mounting occurred.
【０００６】図１５はマガジン方式での実装トラブルで
あり、チップ部品１どうしがマガジンケース４内でロッ
クされ押し棒５で押し出すことができず供給停止とな
る。FIG. 15 shows a mounting problem in the magazine system, in which the chip components 1 are locked in the magazine case 4 and cannot be pushed out by the push rod 5, and the supply is stopped.
【０００７】図１６はテープ方式での実装トラブルであ
り、テープ６の収納凹部７内でチップ部品１が傾斜して
収納凹部７内にロックされて吸着による取出しができな
かったり、テープ６から斜め吸着されて取出され図１４
に示すように位置決め時において斜め実装防止のため
に、この斜めになったチップ部品１が除去されるための
機械稼動率低下があるといった問題があった。FIG. 16 shows a mounting problem with the tape method. The chip component 1 is tilted in the storage recess 7 of the tape 6 and locked in the storage recess 7 so that it cannot be taken out by suction. Adsorbed and taken out Fig. 14
As shown in FIG. 5, there is a problem in that, in order to prevent oblique mounting during positioning, the machine operation rate is reduced due to removal of the oblique chip component 1.
【０００８】一方、図１７に示すように回路基板８に取
付けるチップ部品１の外形の影響については、チップ部
品１の回路基板８に取付ける方法として一般的に、チッ
プ部品１の装着される部分にチップ部品１の各電極巾に
応じた銅等の金属板から成る端子部９が用意されてい
る。この端子部９の板面にクリーム半田をスクリーン印
刷等で半田付け部を形成しておく。この上にチップ部品
１の各端子部が合うように装着した後、赤外線ヒータ等
を用いて加熱してクリーム半田を溶融してチップ部品１
を所定の位置に取付ける。On the other hand, as shown in FIG. 17, regarding the influence of the outer shape of the chip component 1 mounted on the circuit board 8, as a method of mounting the chip component 1 on the circuit board 8, generally, a portion to which the chip component 1 is mounted is mounted. A terminal portion 9 made of a metal plate such as copper corresponding to each electrode width of the chip component 1 is prepared. A soldering portion is formed on the plate surface of the terminal portion 9 by screen printing or the like with cream solder. After mounting the chip parts 1 so that the respective terminal parts are matched with each other, the chip parts 1 are heated by using an infrared heater or the like to melt the cream solder.
Install in place.
【０００９】又、別の方法として予め回路基板８に用意
された両端子部９の間にチップ部品１を固定する接着剤
１０を塗布しておき、この上にチップ部品１を装着した
後接着剤１０を熱硬化させてチップ部品１を固定し、噴
流式半田槽等を用いて半田付を行い回路基板８上にチッ
プ部品１を取付ける。As another method, an adhesive 10 for fixing the chip component 1 is applied between the terminal portions 9 prepared on the circuit board 8 in advance, and the chip component 1 is mounted and then adhered. The chip component 1 is fixed by thermally curing the agent 10, and soldering is performed using a jet solder bath or the like to mount the chip component 1 on the circuit board 8.
【００１０】前者をリフロー半田付法、後者をフロー半
田付法と呼んでいるが、前者の場合チップ部品１の形状
が及ぼす影響として、チップ部品１の外部電極部１１の
角が丸い場合や左右の厚み等がアンバランスである場
合、半田に接している面のアンバランスから半田溶融速
度とチップ部品１の表面の半田メッキ溶融速度に差が生
じて片側の端子の張力でもう片側のチップ端子は離れ、
場合によっては片側端子上にチップ部品１が立つツーム
ストン現象が生じる。The former is called the reflow soldering method and the latter is called the flow soldering method. In the former case, the influence of the shape of the chip component 1 is that the corners of the external electrode portion 11 of the chip component 1 are rounded or left and right. When the thickness of the chip is unbalanced, there is a difference between the solder melting speed and the solder plating melting speed on the surface of the chip component 1 due to the imbalance of the surface in contact with the solder, and the tension of one terminal causes the chip terminal on the other Away,
In some cases, a tombstone phenomenon occurs in which the chip component 1 stands on one terminal.
【００１１】又、後者の場合チップ部品１の外部電極部
１１の厚さが大きく、外部電極部１１の角が丸い場合、
回路基板８の端子部に接触する面積が小さくなり欠落す
る場合がある。In the latter case, when the thickness of the external electrode portion 11 of the chip part 1 is large and the corners of the external electrode portion 11 are round,
The area of the circuit board 8 in contact with the terminals may be reduced and may be missing.
【００１２】以下に従来のチップ形積層セラミックコン
デンサと、その製造方法について説明する。The conventional chip type monolithic ceramic capacitor and its manufacturing method will be described below.
【００１３】図１８は従来の積層セラミックコンデンサ
の内部構造を示すものである。図１８において、１２，
１３，１４，１５，１６はセラミック誘電体であり、１
７，１８，１９，２０はセラミック誘電体１２〜１６の
内部に交互に対極して設けられた内部電極であり、２１
は外部電極であり、それぞれ内部電極１７，１８，１
９，２０と接続されていて、２２はニッケルメッキ、２
３はハンダメッキを施している。FIG. 18 shows the internal structure of a conventional monolithic ceramic capacitor. In FIG. 18, 12,
13, 14, 15, 16 are ceramic dielectrics, 1
Reference numerals 7, 18, 19, and 20 denote internal electrodes provided inside the ceramic dielectrics 12 to 16 so as to alternately face each other.
Are external electrodes, and internal electrodes 17, 18, 1 respectively
9 and 20, 22 is nickel plated, 2
3 is solder plated.
【００１４】一般にチップ形積層セラミックコンデンサ
の製造方法は、図１９に示すようにチタン酸バリウム、
酸化チタン等のセラミック誘電体材料に各種添加物を加
え微粉末化した粉末に有機バインダを加えて極く薄いシ
ート状に成形する。このシートにパラジウム等の導電ペ
ーストを印刷して、内部電極１７〜２０を形成する。こ
の内部電極１７〜２０の形成された薄いセラミックシー
トを少なくとも２層以上交互に重ねて積層成形し所定の
寸法に切断した後焼成する。Generally, a method of manufacturing a chip type monolithic ceramic capacitor is as follows, as shown in FIG.
Various additives are added to a ceramic dielectric material such as titanium oxide, and an organic binder is added to a finely pulverized powder to form an extremely thin sheet. A conductive paste such as palladium is printed on this sheet to form the internal electrodes 17 to 20. At least two layers of the thin ceramic sheets on which the internal electrodes 17 to 20 are formed are alternately laminated and molded, cut into a predetermined size, and then fired.
【００１５】焼成後素体の角を取り、端面電極部を完全
に露出させるためにバレル研磨機等を用いて面取りを行
った後、コンデンサ素体の内部電極１７〜２０を並列に
接続すると共に外部への接続端子として、外部電極２１
を設けたものである。この外部電極２１を形成する工法
は焼成後のチップ形積層セラミックコンデンサをパーツ
フィーダ等で整列させた後、順次保持金具でチップ形積
層セラミックコンデンサ素体の中央部を保持する。After firing, the corners of the element body are removed, and chamfering is performed using a barrel grinder or the like to completely expose the end face electrode portions, and then the internal electrodes 17 to 20 of the capacitor element body are connected in parallel. As an external connection terminal, the external electrode 21
Is provided. In the method of forming the external electrodes 21, the chip-type monolithic ceramic capacitors after firing are aligned with a parts feeder or the like, and then the central portion of the chip-type monolithic ceramic capacitor element body is sequentially held by holding metal fittings.
【００１６】一方外部電極ペーストはローラ又は平板上
に一定量厚さを均一に平らかにした塗工部を設けてお
く。保持したチップ部品の端子部を外部電極塗工部に順
次押し当て塗布する。対極する端子部も同様にして外部
電極を塗布した後、乾燥させてから保持具から外す。乾
燥後のチップ部品を８００℃前後の温度で焼付た後、ニ
ッケルメッキ、ハンダメッキ処理を施して外部電極部が
形成される。その後、特性検査、外観検査、包装を行っ
て出荷される。On the other hand, the external electrode paste is provided on a roller or a flat plate with a coating portion having a uniform flattened thickness. The terminal portions of the held chip component are sequentially pressed against the external electrode coating portion to apply. Similarly, the terminal portion opposite to the electrode is coated with the external electrode, dried, and then removed from the holder. After the dried chip component is baked at a temperature of around 800 ° C., nickel plating and solder plating are applied to form external electrode portions. After that, characteristics inspection, visual inspection, and packaging are performed before shipment.
【００１７】[0017]
【発明が解決しようとする課題】しかしながら従来の外
部電極の形成方法では次のような品質上の問題点を有し
ていた。However, the conventional method of forming an external electrode has the following quality problems.
【００１８】まず、外部電極形成方法が銀等を塗布する
工法によるものが主であるため、外形寸法のバラツキが
大きく、そのため、自動実装する場合の高速化、実装率
向上の妨げとなっている。例えば図１８の外部電極部２
１の外形が部分により丸く盛り上り、実装時の位置決め
が定まらず実装不良問題が発生する。First, since the external electrodes are formed mainly by the method of applying silver or the like, there is a large variation in the outer dimensions, which hinders the speeding up of the automatic mounting and the improvement of the mounting rate. . For example, the external electrode section 2 of FIG.
The outer shape of No. 1 is rounded up by a part, and the positioning at the time of mounting is not fixed, which causes a mounting defect problem.
【００１９】次に外部電極が内部電極とは異なった金
属、例えば銀とパラジウムを使用する場合、接合面での
接続不具合による電気的性能不良や物理的定数（熱膨脹
係数等）の差異による温度ストレスによるクラック不良
等の問題が生じ易い。Next, when the external electrode uses a metal different from that of the internal electrode, for example, silver and palladium, temperature stress due to poor electrical performance due to connection failure at the joint surface and difference in physical constants (coefficient of thermal expansion, etc.) Problems such as crack defects are likely to occur.
【００２０】本発明は上記の従来の問題点を解決するも
ので、外部電極の寸法精度を向上させると同時に内部電
極とその引出電極である外部電極の接合を完全なものと
することを目的とする。The present invention solves the above-mentioned conventional problems, and an object thereof is to improve the dimensional accuracy of the external electrode and, at the same time, to complete the bonding between the internal electrode and the external electrode which is the extraction electrode thereof. To do.
【００２１】[0021]
【課題を解決するための手段】上記課題を解決するため
に本発明は、キャリアフィルム上に定間隔で複数の外部
電極を形成し、この外部電極間に無効層となる誘電体層
を形成して外部電極付無効層を形成し、同じくキャリア
フィルム上に内部電極を形成し、この外部電極付有効層
を形成した誘電体シートを複数枚積層し、この最上面に
外部電極付無効層を形成した誘電体シートをそれぞれ積
層した後に所望の大きさに切断してグリーンチップを作
成し、このグリーンチップを焼成して後に面取りを行
い、上記グリーンチップの両端面に形成された外部電極
上にメッキ層の形成を行う方法である。In order to solve the above-mentioned problems, the present invention forms a plurality of external electrodes at regular intervals on a carrier film, and forms a dielectric layer as an ineffective layer between the external electrodes. To form an ineffective layer with an external electrode, also form an internal electrode on the carrier film, and stack a plurality of dielectric sheets on which the effective layer with an external electrode is formed, and form an ineffective layer with an external electrode on the uppermost surface. After stacking each of the above dielectric sheets, cut into a desired size to create a green chip, fire this green chip and then chamfer it, and plate on the external electrodes formed on both end faces of the green chip. This is a method of forming a layer.
【００２２】この方法によれば、積層するシートの形成
時に内部電極形成と同時に内部電極の引出端子電極であ
る外部電極部を形成して積層したもので完成品の全体面
がフラットなチップ形積層セラミックコンデンサが得ら
れる。According to this method, when the sheets to be laminated are formed, the external electrodes which are the lead-out terminal electrodes of the internal electrodes are formed and laminated at the same time when the internal electrodes are formed. A ceramic capacitor is obtained.
【００２３】[0023]
【発明の実施の形態】本発明の請求項１に記載の発明
は、キャリアフィルム上に定間隔で複数の外部電極を形
成し、この外部電極間に無効層となる誘電体層を形成し
て外部電極付無効層を形成し、同じくキャリアフィルム
上に内部電極を形成し、この内部電極上に誘電体層を形
成して外部電極付有効層を形成し、この外部電極付有効
層を形成した誘電体シートを複数枚積層し、この最上面
と最下面に外部電極付無効層を形成した誘電体シートを
それぞれ積層した後に所望の大きさに切断してグリーン
チップを作成し、このグリーンチップを焼成して後に面
取りを行い、上記グリーンチップの両端面に形成された
外部電極上にメッキ層の形成を行う方法であり、積層す
るシートの形成時に内部電極の形成と同時に内部電極の
引出端子電極である外部電極を形成して積層するため、
全体がフラットなチップ形積層セラミックコンデンサと
することができる。BEST MODE FOR CARRYING OUT THE INVENTION According to the first aspect of the present invention, a plurality of external electrodes are formed on a carrier film at regular intervals, and a dielectric layer serving as an ineffective layer is formed between the external electrodes. An ineffective layer with an external electrode is formed, an internal electrode is also formed on a carrier film, a dielectric layer is formed on this internal electrode to form an effective layer with an external electrode, and this effective layer with an external electrode is formed. A plurality of dielectric sheets are laminated, and a dielectric sheet having an ineffective layer with an external electrode formed on each of the uppermost and lowermost surfaces is laminated respectively, and then cut into a desired size to prepare a green chip. This is a method in which after firing and chamfering, a plating layer is formed on the external electrodes formed on both end faces of the green chip. Is To laminate to form a part electrode,
It is possible to make a chip type monolithic ceramic capacitor which is entirely flat.
【００２４】以下、本発明の実施の形態について図面を
用いて説明する。図１は本発明のチップ形積層セラミッ
クコンデンサの製造方法により得たチップ形積層セラミ
ックコンデンサの断面図であり、３０，３１，３２，３
３，３４はセラミック誘電体であり、３５，３６，３
７，３８はセラミック誘電体３０〜３４の内部に交互に
対極して設けられた内部電極であり、３９は外部電極で
あり、それぞれ内部電極３５，３６，３７，３８と接続
されており、４０はこの外部電極３９上に形成されたニ
ッケルメッキである。Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a chip type monolithic ceramic capacitor obtained by the method for manufacturing a chip type monolithic ceramic capacitor of the present invention.
3, 34 are ceramic dielectrics, 35, 36, 3
Reference numerals 7 and 38 denote internal electrodes provided inside the ceramic dielectrics 30 to 34 so as to be alternately opposite to each other. Reference numeral 39 denotes external electrodes, which are connected to the internal electrodes 35, 36, 37 and 38, respectively. Is nickel plating formed on the external electrode 39.
【００２５】このようなチップ形積層セラミックコンデ
ンサは、図２のような工程によって製造される。すなわ
ち、外部電極は無効層形成として外部電極部を形成した
上に無効層部を形成し、次に外部電極付有効層形成とし
て内部電極部を形成した上に有効層部を形成し、さらに
外部電極部を形成して行い、この外部電極付有効層を複
数積層し、これを所定の寸法に切断してグリーンチップ
とし、このグリーンチップを焼成した後面取りを行い、
両端部の外部電極上にニッケルメッキを施して特性検
査、外観検査を行って良品、不良品の判別後、包装を行
い出荷することになる。Such a chip type monolithic ceramic capacitor is manufactured by the process shown in FIG. That is, the external electrode is formed by forming an external electrode portion as an ineffective layer formation, then forming an ineffective layer portion, then forming an effective electrode portion by forming an internal electrode portion as an effective layer formation with an external electrode, and further forming an external layer. The electrode portion is formed, a plurality of the effective layers with external electrodes are laminated, the green chip is cut into a predetermined size, and the green chip is fired and then chamfered.
Nickel plating is applied to the external electrodes at both ends, and characteristic inspection and appearance inspection are performed to determine whether the product is a good product or a defective product, and then the product is packaged and shipped.
【００２６】次に本発明の製造方法の具体例を説明す
る。図３、図４はチップ形積層セラミックコンデンサの
外部電極付無効層形成の断面図であり、４１はプラスチ
ックフィルム等のキャリアフィルムであり、４２は外部
電極３９となる導電ペーストであり、４３は誘電体部で
あり無効のセラミック誘電体３０を形成する。すなわ
ち、図３に示すようにキャリアフィルム４１上に一定の
間隔をもって導電ペースト４２を印刷し、次に図４に示
すように導電ペースト４２間を埋めるように誘電体部４
３を印刷する。Next, a specific example of the manufacturing method of the present invention will be described. 3 and 4 are cross-sectional views of formation of an ineffective layer with external electrodes of a chip type monolithic ceramic capacitor, 41 is a carrier film such as a plastic film, 42 is a conductive paste to be the external electrodes 39, and 43 is a dielectric. Form an ineffective ceramic dielectric 30 that is a body. That is, as shown in FIG. 3, the conductive paste 42 is printed on the carrier film 41 at regular intervals, and then, as shown in FIG.
Print 3.
【００２７】図５〜図７は外部電極付内部電極と誘電体
層を形成した有効層シートの断面図であり、４４は導電
体層で内部電極３５〜３８および外部電極３９となる。
４５は誘電体部で有効層としてのセラミック誘電体３２
〜３４となり、４６は外部電極３９となる導電体層であ
る。まず、図５に示すようにキャリアフィルム４１上に
導電体層４４を形成し、この上に図６に示すように誘電
体ペーストを印刷等により外部電極３９となる部分を除
いて形成した有効層の誘電体部４５を形成し、次に図７
に示すように誘電体部４５のギャップ部に導電体層４６
を印刷により形成して面一な有効層シートを作成する。5 to 7 are cross-sectional views of an effective layer sheet in which internal electrodes with external electrodes and a dielectric layer are formed. Reference numeral 44 denotes a conductor layer which serves as the internal electrodes 35 to 38 and the external electrode 39.
Reference numeral 45 denotes a dielectric part, which is a ceramic dielectric 32 as an effective layer.
˜34, and 46 is a conductor layer that becomes the external electrode 39. First, as shown in FIG. 5, a conductive layer 44 is formed on a carrier film 41, and as shown in FIG. 6, an effective layer formed by removing a portion of the dielectric paste by printing or the like to be an external electrode 39. Forming the dielectric part 45 of FIG.
As shown in FIG.
Is formed by printing to form a flat effective layer sheet.
【００２８】次にこれらの形成されたシートを積層する
方法について説明する。図８は図３、図４で形成した無
効層用シートを重ねて圧着の後、キャリアフィルムを剥
がしたものであり、所定の厚さになるまで同様に行い無
効層部を形成した断面図である。Next, a method for laminating these formed sheets will be described. FIG. 8 is a cross-sectional view in which the ineffective layer sheets formed in FIGS. 3 and 4 are stacked, pressure-bonded and then the carrier film is peeled off, and the ineffective layer portion is formed in the same manner until a predetermined thickness is obtained. is there.
【００２９】図９は無効層部の上に図７で形成した有効
層シートの形成面を所定の位置に重ね合わせて圧着の
後、キャリアフィルム４１を剥がして転写を行う。さら
に同様にして有効層シートを重ね合わせる。この時この
シートは対向する電極を形成するように所定の寸法だけ
ずらせて層を形成する。さらに同様にして有効層シート
を重ね合わせて有効層部を形成したものに図４で形成し
た無効層シートの形成面を所定の位置に重ね合わせて圧
着の後、キャリアフィルム４１を剥がして転写を行い、
同様の手順で所定の厚みになるまで行い積層セラミック
コンデンサを形成した断面図である。In FIG. 9, the formation surface of the effective layer sheet formed in FIG. 7 is superposed on the ineffective layer portion at a predetermined position, and after pressure bonding, the carrier film 41 is peeled off to perform transfer. Further, the effective layer sheets are stacked in the same manner. At this time, this sheet is shifted by a predetermined dimension to form a layer so as to form the opposing electrodes. Similarly, the surface of the ineffective layer sheet formed in FIG. 4 is superposed at a predetermined position on the effective layer portion formed by superimposing the effective layer sheets, and the carrier film 41 is peeled off and transferred. Done,
FIG. 4 is a cross-sectional view of a laminated ceramic capacitor formed by performing the same procedure until a predetermined thickness is obtained.
【００３０】次に積層以後の工程について説明する。図
１０は図９の積層形成された積層セラミックコンデンサ
を刃物等で切断する位置を点線で示したものであり、複
数個同時形成されたものを単品に切り出した断面図であ
る。これらの単品として切り出されたチップ形積層チッ
プコンデンサを１３００℃前後で焼成を行った後、メッ
キ処理を施してチップ形積層セラミックコンデンサを造
る。このようにして外部電極３９をシート形成時に内部
電極３５〜３８と同時に形成することができる。Next, the steps after stacking will be described. FIG. 10 is a cross-sectional view showing a position where the laminated monolithic ceramic capacitor shown in FIG. 9 is cut with a blade or the like, and a plurality of simultaneously formed ones are cut out as a single product. The chip-type multilayer chip capacitors cut out as these single pieces are fired at around 1300 ° C., and then plated to produce chip-type multilayer ceramic capacitors. In this way, the external electrodes 39 can be formed simultaneously with the internal electrodes 35 to 38 when forming the sheet.
【００３１】なお、図１１、図１２のように部分的に外
部電極３９を形成しても良い。積層の方法は加熱転写の
方法でも良く、又は転写以外の印刷で積層形成する方法
でも良い。The external electrode 39 may be partially formed as shown in FIGS. The stacking method may be a heat transfer method, or a stacking method by printing other than transfer.
【００３２】[0032]
【発明の効果】以上のように本発明は内部電極と同時に
外部電極を形成することにより、チップ形積層セラミッ
クコンデンサの外形寸法精度が従来の規格で±０．２ｍ
ｍ（ＡＩＥＪ規格）のところ、±０．０５ｍｍの精度迄
引き上げることができ、高い実装率と高速実装が可能と
なった。さらに外部電極塗布形成工程を無くすことか
ら、生産工数の低減効果も大きなものとなる。さらには
内部電極と外部電極の接続の不安定さから生じる熱的、
機械的における種々の問題を無くす効果が期待できる。As described above, according to the present invention, by forming the external electrodes at the same time as the internal electrodes, the external dimension accuracy of the chip type multilayer ceramic capacitor is ± 0.2 m according to the conventional standard.
With respect to m (AIEJ standard), it was possible to raise the accuracy to ± 0.05 mm, which enabled high mounting rate and high-speed mounting. Furthermore, since the external electrode coating and forming step is eliminated, the effect of reducing the number of production steps becomes great. Furthermore, thermal caused by the instability of the connection between the internal electrode and the external electrode,
The effect of eliminating various mechanical problems can be expected.
【図１】本発明の実施の形態におけるチップ形積層セラ
ミックコンデンサの断面図FIG. 1 is a sectional view of a chip type monolithic ceramic capacitor according to an embodiment of the present invention.
【図２】同製造方法の工程図FIG. 2 is a process diagram of the manufacturing method.
【図３】同製造方法におけるキャリアフィルム上に外部
電極としての導電ペーストを印刷した状態を示す断面図FIG. 3 is a cross-sectional view showing a state in which a conductive paste as an external electrode is printed on a carrier film in the manufacturing method.
【図４】同誘電体部を形成した状態の断面図FIG. 4 is a cross-sectional view of a state in which the dielectric portion is formed.
【図５】同じくキャリアフィルム上に内部電極と外部電
極を形成した状態の断面図FIG. 5 is a cross-sectional view of a state in which an internal electrode and an external electrode are similarly formed on a carrier film.
【図６】同誘電体部を形成した状態の断面図FIG. 6 is a cross-sectional view showing a state in which the dielectric portion is formed.
【図７】同誘電体部間のギャップに導電体層を形成した
状態の断面図FIG. 7 is a cross-sectional view showing a state in which a conductor layer is formed in the gap between the dielectric parts.
【図８】図４に示すものを積層しキャリアフィルムを剥
がした状態の断面図FIG. 8 is a cross-sectional view of the state shown in FIG. 4 laminated and the carrier film peeled off.
【図９】全シートを積層した状態の断面図FIG. 9 is a sectional view showing a state in which all sheets are stacked.
【図１０】同積層したものを個々のチップ形積層セラミ
ックコンデンサに切断する状態を示す断面図FIG. 10 is a cross-sectional view showing a state in which the same laminate is cut into individual chip-type monolithic ceramic capacitors.
【図１１】本発明の他の実施の形態によるチップ形積層
セラミックコンデンサの断面図FIG. 11 is a sectional view of a chip type monolithic ceramic capacitor according to another embodiment of the present invention.
【図１２】同他の実施の形態によるチップ形積層セラミ
ックコンデンサの断面図FIG. 12 is a sectional view of a chip type monolithic ceramic capacitor according to another embodiment.
【図１３】一般的なチップ部品のパーツフィーダによる
不都合を説明する説明図FIG. 13 is an explanatory diagram for explaining an inconvenience caused by a parts feeder for a general chip part.
【図１４】同じく実装時の位置決めの不都合な場合の説
明図FIG. 14 is an explanatory diagram of a case where positioning is inconvenient during mounting.
【図１５】同じくマガジンケースに実装したときの説明
図FIG. 15 is an explanatory diagram when the same is mounted on a magazine case.
【図１６】同じくテープ包装した状態の説明図FIG. 16 is an explanatory view of the same tape packaging state.
【図１７】チップ部品の回路基板への実装を示す説明図FIG. 17 is an explanatory diagram showing mounting of chip components on a circuit board.
【図１８】従来のチップ形積層セラミックコンデンサの
断面図FIG. 18 is a sectional view of a conventional chip type monolithic ceramic capacitor.
【図１９】従来の製造工程を示す工程図FIG. 19 is a process diagram showing a conventional manufacturing process.
３０〜３４ セラミック誘電体 ３５〜３８ 内部電極 ３９ 外部電極 ４０ ニッケルメッキ ４１ キャリアフィルム ４２ 導電ペースト ４３ 誘電体部 ４４ 導電体層 ４５ 誘電体部 ４６ 導電体層 30-34 Ceramic Dielectric 35-38 Internal Electrode 39 External Electrode 40 Nickel Plating 41 Carrier Film 42 Conductive Paste 43 Dielectric Part 44 Conductor Layer 45 Dielectric Part 46 Conductor Layer
Claims (1)
部電極を形成し、この外部電極間に無効層となる誘電体
層を形成して外部電極付無効層を形成し、同じくキャリ
アフィルム上に内部電極を形成し、この内部電極上に誘
電体層を形成して外部電極付有効層を形成し、この外部
電極付有効層を形成した誘電体シートを複数枚積層し、
この最上面と最下面に外部電極付無効層を形成した誘電
体シートをそれぞれ積層した後に所望の大きさに切断し
てグリーンチップを作成し、このグリーンチップを焼成
して後に面取りを行い、上記グリーンチップの両端面に
形成された外部電極上にメッキ層の形成を行うチップ形
積層セラミックコンデンサの製造方法。1. A plurality of external electrodes are formed on a carrier film at regular intervals, a dielectric layer serving as an ineffective layer is formed between the external electrodes to form an ineffective layer with external electrodes, and also on the carrier film. An internal electrode is formed, a dielectric layer is formed on the internal electrode to form an effective layer with an external electrode, and a plurality of dielectric sheets with the effective layer with an external electrode are laminated,
After stacking the dielectric sheets with the external electrode ineffective layer formed on the uppermost surface and the lowermost surface, respectively, to cut into a desired size to create a green chip, the green chip is fired and then chamfered, A method of manufacturing a chip type multilayer ceramic capacitor, wherein a plating layer is formed on external electrodes formed on both end surfaces of a green chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7292368A JPH09134844A (en) | 1995-11-10 | 1995-11-10 | Manufacture of chip type laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7292368A JPH09134844A (en) | 1995-11-10 | 1995-11-10 | Manufacture of chip type laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09134844A true JPH09134844A (en) | 1997-05-20 |
Family
ID=17780903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7292368A Pending JPH09134844A (en) | 1995-11-10 | 1995-11-10 | Manufacture of chip type laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09134844A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100596602B1 (en) * | 2005-03-30 | 2006-07-04 | 삼성전기주식회사 | Multi-layer ceramic capacitor and production method thereof |
| KR100663942B1 (en) * | 2005-03-24 | 2007-01-02 | 삼성전기주식회사 | Multi-layer Ceramic Capacitor and Production Method Thereof |
| KR100663941B1 (en) * | 2005-03-30 | 2007-01-02 | 삼성전기주식회사 | Array type Multi-layer Ceramic Capacitor and Production Method Thereof |
| JP2012038917A (en) * | 2010-08-06 | 2012-02-23 | Murata Mfg Co Ltd | Ceramic electronic component and method for manufacturing the same |
-
1995
- 1995-11-10 JP JP7292368A patent/JPH09134844A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100663942B1 (en) * | 2005-03-24 | 2007-01-02 | 삼성전기주식회사 | Multi-layer Ceramic Capacitor and Production Method Thereof |
| US7593215B2 (en) | 2005-03-24 | 2009-09-22 | Samsung Electro-Mechanics Co., Ltd. | Multi-layer ceramic capacitor and production method thereof |
| US8004822B2 (en) | 2005-03-24 | 2011-08-23 | Samsung Electro-Mechanics Co., Ltd. | Multi-layer ceramic capacitor and production method thereof |
| KR100596602B1 (en) * | 2005-03-30 | 2006-07-04 | 삼성전기주식회사 | Multi-layer ceramic capacitor and production method thereof |
| KR100663941B1 (en) * | 2005-03-30 | 2007-01-02 | 삼성전기주식회사 | Array type Multi-layer Ceramic Capacitor and Production Method Thereof |
| JP2012038917A (en) * | 2010-08-06 | 2012-02-23 | Murata Mfg Co Ltd | Ceramic electronic component and method for manufacturing the same |
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