JPH09120971A - Flat semiconductor device - Google Patents
Flat semiconductor deviceInfo
- Publication number
- JPH09120971A JPH09120971A JP28004695A JP28004695A JPH09120971A JP H09120971 A JPH09120971 A JP H09120971A JP 28004695 A JP28004695 A JP 28004695A JP 28004695 A JP28004695 A JP 28004695A JP H09120971 A JPH09120971 A JP H09120971A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- plate
- insulating ring
- brazed
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、両面冷却型の平型
パッケージに封入されたパワートランジスターやサイリ
スタ等高耐圧、大電流容量の半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage and large current capacity semiconductor element such as a power transistor or a thyristor enclosed in a double-sided cooling type flat package.
【０００２】[0002]
【従来の技術】車両駆動用や産業用インバータ・コンバ
ータなどの電力変換用の高耐圧の大電流容量の半導体素
子（以下電力用半導体素子と称する）として、ゲートタ
ーンオフサイリスタ（ＧＴＯサイリスタ）を始めとする
サイリスタや、バイポーラトランジスタ、絶縁ゲートバ
イポーラトランジスタ（ＩＧＢＴ）等が使われている。
電力用半導体素子は、高耐圧を保持するため、通常セラ
ミックスを絶縁体とし、上下に銅電極を有する密閉され
た平型パッケージに収容し用いられている。通常、電力
用サイリスタでは、素子エレメントが丸形であるため、
そのエレメントを収容するパッケージの外形形状も丸で
ある。一方、ＩＧＢＴでは、大容量化のために、角型の
チップを複数個同一パッケージに収容した角型のパッケ
ージが採用されている。これらの素子において、半導体
素子の高耐圧化、大容量化と共に、パッケージの外形も
大きくなってきている。2. Description of the Related Art A gate turn-off thyristor (GTO thyristor) is used as a semiconductor element having a high withstand voltage and a large current capacity (hereinafter referred to as a power semiconductor element) for power conversion such as a vehicle drive and an industrial inverter / converter. A thyristor, a bipolar transistor, an insulated gate bipolar transistor (IGBT), etc. are used.
In order to maintain a high breakdown voltage, a power semiconductor element is usually used by being housed in a sealed flat package having ceramics as an insulator and copper electrodes on the top and bottom. Normally, in a power thyristor, since the element element is round,
The outer shape of the package that houses the element is also round. On the other hand, the IGBT employs a rectangular package in which a plurality of rectangular chips are housed in the same package in order to increase the capacity. In these devices, as the semiconductor devices have higher breakdown voltage and larger capacity, the outer shape of the package is also increasing.
【０００３】図２に従来の半導体バッケージ１０の断面
図を示す。但し、パッケージの構成をより分かり易くす
るため、最終組立前の様子を示した。電力用半導体素子
のパッケージ１０の下部銅電極８は、セラミックスと熱
膨張係数が近似するコバール（Ｆｅ−２９％Ｎｉ−１７
％Ｃｏ）やＦｅ−４２％Ｎｉ合金等の絞り構造を有する
下部絞り板７を介して、セラミックスの絶縁環６の一方
の端面に銀ろう付されている。セラミックスの絶縁環６
の他方の端には、コバール等の溶接板５が銀ろう付され
ている。FIG. 2 shows a sectional view of a conventional semiconductor package 10. However, the state before final assembly is shown in order to make the structure of the package easier to understand. The lower copper electrode 8 of the power semiconductor device package 10 is made of Kovar (Fe-29% Ni-17) having a thermal expansion coefficient similar to that of ceramics.
% Co) or Fe-42% Ni alloy or the like, and silver brazing is applied to one end surface of the insulating ring 6 of ceramics through a lower diaphragm plate 7 having a diaphragm structure. Ceramic insulation ring 6
A welding plate 5 such as Kovar is brazed to the other end of the.
【０００４】もう一方の上部銅電極１は、絞り構造を有
する銅の上部絞り板２を介して銀ろう付けされたコバー
ル等の溶接板３がろう付けされている。パッケージ１０
内に半導体エレメント９を収めた後に、溶接板５と溶接
板３とが溶接により接合され、エレメント９がパッケー
ジ１０内に密封される。上下の銅電極とエレメント９と
の密着性を高めるため、上部絞り板２と下部絞り板７は
可撓性をもたせてある。The other upper copper electrode 1 is brazed with a welding plate 3 such as Kovar brazed with silver through an upper diaphragm plate 2 made of copper having a diaphragm structure. Package 10
After housing the semiconductor element 9 therein, the welding plate 5 and the welding plate 3 are joined by welding, and the element 9 is sealed in the package 10. In order to improve the adhesion between the upper and lower copper electrodes and the element 9, the upper diaphragm plate 2 and the lower diaphragm plate 7 have flexibility.
【０００５】[0005]
【発明が解決しようとする課題】ところが、電力用半導
体素子の高耐圧化、大電流容量化のため、半導体エレメ
ントの直径は急速に大口径化してきている。それに伴
い、パッケージの外形が大きくなると、セラミックスの
絶縁環６と下部銅電極８との間に、可撓性を有する下部
絞り板７を挟んでも、セラミックスの絶縁環６と下部銅
電極８との熱膨張係数の差により発生する歪みを吸収し
きれず、下部銅電極８が変形するようになった。例え
ば、直径１３０ｍｍの下部銅電極８では、約１５０μｍ
の反りを生じた。そのため、上下の銅電極１、８と半導
体エレメント９との接触が悪く、冷却が不十分で信頼性
上問題となることがあった。However, the diameter of the semiconductor element is rapidly increasing due to the higher withstand voltage and larger current capacity of the power semiconductor element. Along with this, when the outer shape of the package becomes large, even if the flexible lower diaphragm plate 7 is sandwiched between the ceramic insulating ring 6 and the lower copper electrode 8, the ceramic insulating ring 6 and the lower copper electrode 8 are separated from each other. The strain generated due to the difference in thermal expansion coefficient could not be completely absorbed and the lower copper electrode 8 was deformed. For example, with the lower copper electrode 8 having a diameter of 130 mm, about 150 μm
Caused a warp. Therefore, the contact between the upper and lower copper electrodes 1 and 8 and the semiconductor element 9 is poor, and the cooling may be insufficient, causing a problem in reliability.
【０００６】一方、パッケージの小型化の要求から絶縁
環６の直径は小さくしなければならず、また、半導体素
子からの熱放散性の向上のため、銅電極８は大口径化し
なければならないので、絶縁環６と銅電極８との間の距
離はむしろ狭めたい要求がある。従って、セラミックス
と銅電極との間にろう付される絞り板によって、熱膨張
係数の差により生じる歪みを緩和する方法も充分な効果
を得難くなってきている。On the other hand, the diameter of the insulating ring 6 has to be made small in order to reduce the size of the package, and the copper electrode 8 has to have a large diameter in order to improve the heat dissipation from the semiconductor element. The distance between the insulating ring 6 and the copper electrode 8 needs to be narrowed. Therefore, it is becoming difficult to obtain a sufficient effect in the method of relaxing the strain caused by the difference in thermal expansion coefficient by the diaphragm plate brazed between the ceramics and the copper electrode.
【０００７】そこで、容易に絞り構造を加工出来、且
つ、材料が柔らかいため、熱膨張係数の差による収縮に
順応できる銅の絞り板のろう付けを試みた。ところが熱
膨張係数において、銅板（２２×１０-6℃-1）とセラミ
ックス（アルミナ：７×１０-6℃-1）との間に大きな隔
たりがあることから、銅の絞り板を直接、セラミックス
の絶縁環６にろう付けすると銅の絞り板の表面に割れや
引きつりが生じ、気密不良が発生した。Therefore, an attempt has been made to braze a copper diaphragm plate which can easily process the diaphragm structure and can adapt to contraction due to the difference in thermal expansion coefficient because the material is soft. However, in terms of the coefficient of thermal expansion, there is a large gap between the copper plate (22 × 10 -6 ° C -1 ) and the ceramics (alumina: 7 × 10 -6 ° C -1 ). When the insulating ring 6 was brazed, the surface of the copper diaphragm was cracked or dragged, resulting in poor airtightness.
【０００８】以上の問題に鑑みて、本発明の目的は、大
型化した平型パッケージにおいても、ろう付けされる銅
電極に歪みを与えず、且つ、良好な気密性の高い平型半
導体素子を提供することにある。In view of the above problems, it is an object of the present invention to provide a flat semiconductor element having high airtightness, which does not give distortion to a brazed copper electrode even in a large flat package. To provide.
【０００９】[0009]
【課題を解決するための手段】上記の目的を達成するた
めに本発明は、セラミックスの絶縁環に銅電極の周縁部
の絞り板がろう付けされた平型半導体素子において、銅
からなる絞り板が、その熱膨張係数がセラミックスより
大きく、銅より小さい金属板を間に挟んで絶縁環の端面
に一体ろう付けされているものとする。In order to achieve the above object, the present invention relates to a flat semiconductor element in which a diaphragm plate around the periphery of a copper electrode is brazed to an insulating ring made of ceramics. However, it is assumed that they are integrally brazed to the end surface of the insulating ring with a metal plate having a coefficient of thermal expansion larger than that of ceramics and smaller than copper interposed therebetween.
【００１０】前記金属板としては、金属板の熱膨張係数
が８×１０-6〜２０×１０-6℃-1であること、特に、Ｆ
ｅ−４２％Ｎｉ合金、コバール、鉄のいずれかがよい。
特に、絶縁環が角型環であるものがよい。上記の手段を
講じることによって、下記の作用が得られる。The metal plate has a coefficient of thermal expansion of 8 × 10 −6 to 20 × 10 −6 ° C. −1 , and in particular, F
One of e-42% Ni alloy, Kovar, and iron is preferable.
In particular, the insulating ring is preferably a square ring. By taking the above means, the following effects can be obtained.
【００１１】すなわち、銅からなる絞り板を用いること
によって、銅電極と絞り板の熱膨張係数は同じになる。
また、銅の絞り板が、その熱膨張係数がセラミックスよ
り大きく、銅より小さい金属板を間に挟んで絶縁環の端
面に一体ろう付けされているものとすれば、銅絞り板と
セラミックの絶縁環との熱膨張係数の違いによる歪み
は、銅絞り板の収縮がこの介在する金属板により緩和さ
れる。更に、銅絞り板は柔軟性に富み、歪みを伝え難
い。That is, by using the diaphragm plate made of copper, the copper electrode and the diaphragm plate have the same coefficient of thermal expansion.
Also, if the copper diaphragm plate is integrally brazed to the end face of the insulating ring with a metal plate having a coefficient of thermal expansion larger than that of ceramics and smaller than copper sandwiched between the copper diaphragm plate and the ceramic, The strain due to the difference in the coefficient of thermal expansion from the ring is relaxed by the intervening metal plate for the contraction of the copper diaphragm. Furthermore, the copper diaphragm is highly flexible, and it is difficult to convey distortion.
【００１２】前記金属板としては、Ｆｅ−４２％Ｎｉ合
金、コバール、鉄のいずれも、その熱膨張係数は、セラ
ミックのそれより大きく、かつ銅のそれより小さい。特
に、絶縁環が角型環であれば、不均質な歪みが大きい部
分を生じるが、その抑制効果が大きい。As the metal plate, any of Fe-42% Ni alloy, Kovar, and iron has a coefficient of thermal expansion larger than that of ceramics and smaller than that of copper. In particular, if the insulating ring is a square ring, a portion having a large amount of non-uniform strain is generated, but the suppressing effect is large.
【００１３】[0013]
【発明の実施の形態】本発明は、半導体パッケージのセ
ラミックスの絶縁環と絞り板との接合において、銅電極
と同じ材質の銅の絞り板を用い、その銅の絞り板とセラ
ミックスの絶縁環との間に、セラミックスの熱膨張係数
と銅のそれと間の熱膨張係数をもつ、金属板を挟んでろ
う付けするものである。そのような金属板としては、Ｆ
ｅ−４２％Ｎｉ合金、コバール、鉄等を用いることがで
きる。BEST MODE FOR CARRYING OUT THE INVENTION The present invention uses a copper diaphragm plate made of the same material as a copper electrode in joining a ceramic insulating ring of a semiconductor package and a diaphragm plate. A metal plate having a coefficient of thermal expansion of ceramics and a coefficient of thermal expansion of that of copper is sandwiched between and brazed. As such a metal plate, F
An e-42% Ni alloy, Kovar, iron or the like can be used.
【００１４】[0014]
【実施例】以下、本発明の実施例を図面を参照しながら
説明する。 実施例１ 図１は、本発明の実施例の半導体素子の断面図を示す。
円環状の絶縁環６は純度９０〜９６％アルミナセラミッ
クス製で、その外径は１５０mm、高さ２８mmである。そ
の絶縁環６の一方の端面（図では下側）には、Ｆｅ−４
２％Ｎｉ合金の環状の金属板２０を挟んで、下部銅電極
１８の周縁部の銅の下部絞り板１７がろう付けされ、他
方の端面には、Ｆｅ−４２％Ｎｉ合金の溶接板１５がや
はりろう付けされている。上部銅電極１１の周縁部に
は、銅の上部絞り板１２がろう付けされ、さらにその周
縁部にＦｅ−４２％Ｎｉ合金の溶接板１３がやはりろう
付けされている。下部銅電極１８の上にサイリスタのエ
レメント１９が載せられ、そのエレメントの上部電極に
上部銅電極１１が接触するように位置ぎめして、溶接板
１３と溶接板１５の外周が溶接されている。１４は、エ
レメント１９の位置ぎめのための四フッ化エチレン樹脂
の位置ぎめガイドである。ここで、上部、下部とは区別
のために仮りに付したのであって、組立時或いは使用時
の上下関係を示すものではない。エレメント１９と上部
電極の間にＭｏ等の円板を挟むこともある。また、サイ
リスタのゲート電極とゲート端子は適当な方法で接続さ
れているがその構造は省略した。Embodiments of the present invention will be described below with reference to the drawings. Example 1 FIG. 1 is a sectional view of a semiconductor device according to an example of the present invention.
The annular insulating ring 6 is made of alumina ceramics having a purity of 90 to 96% and has an outer diameter of 150 mm and a height of 28 mm. Fe-4 is formed on one end surface (lower side in the figure) of the insulating ring 6.
A copper lower drawing plate 17 on the peripheral portion of the lower copper electrode 18 is brazed with an annular metal plate 20 of 2% Ni alloy sandwiched therebetween, and a welding plate 15 of Fe-42% Ni alloy is provided on the other end face. After all it is brazed. An upper diaphragm plate 12 made of copper is brazed to the peripheral portion of the upper copper electrode 11, and a welded plate 13 of Fe-42% Ni alloy is also brazed to the peripheral portion thereof. An element 19 of a thyristor is placed on the lower copper electrode 18, the upper electrode of the thyristor is positioned so that the upper copper electrode 11 comes into contact, and the outer circumferences of the welding plate 13 and the welding plate 15 are welded. Reference numeral 14 is a positioning guide of tetrafluoroethylene resin for positioning the element 19. Here, the upper part and the lower part are tentatively attached for the purpose of distinction, and do not show the vertical relationship at the time of assembly or use. A disc of Mo or the like may be sandwiched between the element 19 and the upper electrode. The gate electrode and gate terminal of the thyristor are connected by an appropriate method, but the structure is omitted.
【００１５】図１の構造を得る製造方法を以下に説明す
る。まず、純度９０〜９６％アルミナセラミックス製の
円環状の絶縁環６の両方の端面にＭｏ−Ｍｎ粉ペースト
をスクリーン印刷により塗布し、それらを加湿水素中１
４００〜１５５０℃で焼き付け、その後、その面にニッ
ケルメッキを行い、絶縁環６の両端面に強固な金属層を
形成する。A manufacturing method for obtaining the structure of FIG. 1 will be described below. First, Mo-Mn powder paste is applied by screen printing to both end surfaces of an annular insulating ring 6 made of alumina ceramics having a purity of 90 to 96%, and they are applied in humidified hydrogen 1
After baking at 400 to 1550 ° C., nickel plating is performed on the surface to form strong metal layers on both end surfaces of the insulating ring 6.
【００１６】グラファイトのろう付け用治具内に、Ｆｅ
−４２％Ｎｉ合金の溶接板１５を置き、銀ろうを挟ん
で、上記導電性処理をした絶縁環６をおく。更にその絶
縁環６の端面上に、銀ろうを挟んで、Ｆｅ−４２％Ｎｉ
合金の環状の金属板２０、再び銀ろうを置いた上に、下
部絞り板１７をおき、更にろう付けする部分に銀ろう片
を挟んで直径１３０mm、高さ１０mmの下部銅電極１８を
置く。（すなわち、図１と逆さまの状態でろう付けする
が、これは絶対に必要な条件ではない。）銀ろうとして
は、例えばＪＩＳのＢＡｇ−８を用いることができる。
そのろう付け用治具を、水素雰囲気中，８００〜８５０
℃で１０分間保持してろう付けを行う。なお、上記銀ろ
うＢＡｇ−８の融点は７８３℃である。ろう付けの雰囲
気は真空でもよい。Fe is placed in a graphite brazing jig.
A welding plate 15 of -42% Ni alloy is placed, and the insulating ring 6 which has been subjected to the conductive treatment is placed with silver brazing material sandwiched therebetween. Further, on the end face of the insulating ring 6, sandwiching a silver solder, Fe-42% Ni
An annular metal plate 20 of an alloy and a silver brazing material are placed again, a lower diaphragm plate 17 is placed, and a silver brazing piece is sandwiched between the brazing portions, and a lower copper electrode 18 having a diameter of 130 mm and a height of 10 mm is placed. (That is, the brazing is performed upside down with respect to FIG. 1, but this is not an absolutely necessary condition.) As silver brazing, for example, BAg-8 of JIS can be used.
The brazing jig is placed in a hydrogen atmosphere at 800 to 850
Hold at 10 ° C for 10 minutes to perform brazing. The melting point of the above silver wax BAg-8 is 783 ° C. The brazing atmosphere may be vacuum.
【００１７】また、上部銅電極１１と上部絞り板１２お
よびＦｅ−４２％Ｎｉ合金の溶接板１３を銀ろうを用い
てろう付けする。先の絶縁環６をろう付けした下部銅電
極１８上にサイリスタのエレメント１９を置き、溶接板
をろう付けした上部電極を被せて溶接板１３、１５の外
周を溶接した。図示されない置換用パイプからパッケー
ジ内をガス置換し、最後に置換用パイプを閉じて密封す
る。Further, the upper copper electrode 11, the upper diaphragm plate 12 and the Fe-42% Ni alloy welding plate 13 are brazed using silver brazing. The thyristor element 19 was placed on the lower copper electrode 18 to which the insulating ring 6 was brazed, and the outer periphery of the welding plates 13 and 15 was welded by covering the upper electrode to which the welding plate was brazed. The inside of the package is replaced with gas from a replacement pipe (not shown), and finally the replacement pipe is closed and sealed.
【００１８】このように銅の下部絞り板１７を用い、絶
縁環６にＦｅ−４２％Ｎｉ合金の金属板２０を介してろ
う付けすることによって、従来、Ｆｅ−Ｎｉ合金の絞り
板で直接ろう付けした時のような大きな反りは生ぜず、
下部銅電極１８の反り量は２０μm 以下となった。そし
て、その結果、ろう付け後、従来行っていた銅電極表面
を平滑にするための加工が必要無くなった。As described above, the lower diaphragm plate 17 made of copper is brazed to the insulating ring 6 through the metal plate 20 made of Fe-42% Ni alloy so that the conventional diaphragm plate made of Fe-Ni alloy is directly brazed. No big warpage like when attached,
The warp amount of the lower copper electrode 18 became 20 μm or less. As a result, after brazing, the conventional work for smoothing the surface of the copper electrode is no longer necessary.
【００１９】これは、下部銅電極１８と下部絞り板１７
との間には、熱膨張係数の差による歪みを生じないこ
と、下部絞り板１７と絶縁環１６との間の熱膨張係数の
差による歪みは、中間のＦｅ−４２％Ｎｉ合金の金属板
２０で緩和されること、また、銅の下部絞り板１７は延
性に富むことから、下部絞り板１７と絶縁環１６との間
の熱膨張係数の差による歪みを下部銅電極１８に伝えな
いことによると考えられる。This is the lower copper electrode 18 and the lower diaphragm plate 17.
Distortion caused by the difference in the thermal expansion coefficient between the lower diaphragm plate 17 and the insulating ring 16 is not caused by the difference in the thermal expansion coefficient between the lower diaphragm plate 17 and the insulating ring 16. 20 and the lower diaphragm plate 17 made of copper is rich in ductility. Therefore, strain due to the difference in thermal expansion coefficient between the lower diaphragm plate 17 and the insulating ring 16 should not be transmitted to the lower copper electrode 18. It is believed that
【００２０】また、銅の絞り板をセラミックスの絶縁環
に直接ろう付けした場合に生じたような割れや引きつり
は生じず、気密不良の問題も起きなかった。これも、セ
ラミックスの絶縁環１６と銅の下部絞り板１７との間に
セラミックスと銅との中間の熱膨張係数を有する金属板
２０が介在するため、収縮量の差による歪みが緩和さ
れ、割れや引きつりが発生しないものと考えられる。Further, the cracks and drags that would occur when the copper diaphragm plate was directly brazed to the ceramic insulating ring did not occur, and the problem of airtightness did not occur. This is also because the metal plate 20 having a coefficient of thermal expansion intermediate between that of ceramics and copper is interposed between the insulating ring 16 of ceramics and the lower drawing plate 17 of copper. It is considered that no dragging or dragging occurs.
【００２１】従って、上記の方法によれば、絶縁環１６
と下部銅電極１８との間の距離を最小にすることができ
る。表１にＦｅ−４２％Ｎｉ合金、コバール、鉄と比較
のための銅、アルミナセラミックの２０〜８００℃の熱
膨張係数を示す。Therefore, according to the above method, the insulating ring 16
The distance between the lower copper electrode 18 and the lower copper electrode 18 can be minimized. Table 1 shows the coefficient of thermal expansion of the Fe-42% Ni alloy, Kovar, copper for comparison with iron and alumina ceramics at 20 to 800 ° C.
【００２２】[0022]
【表１】 実施例２ 実施例１と同様の方法により、強固な金属層を形成した
外形１２０×９０mm、高さ１６mmの角形アルミナセラミ
ックスの角型絶縁環と、コバールの四角環状の金属板３
０、更に、絞り構造を有する銅の下部絞り板とのろう付
け、その下部絞り板と外形１００×７０mm、高さ６mmの
下部銅電極とのろう付け、および角型絶縁環の他方の端
面とコバールの溶接板とのろう付けを同時に行った。[Table 1] Example 2 By a method similar to that of Example 1, a rectangular metal ring 3 made of a rectangular alumina ceramic having an outer shape of 120 × 90 mm and a height of 16 mm and a strong metal layer formed thereon, and a Kovar square annular metal plate 3 were used.
0, further, brazing with a copper lower diaphragm plate having a diaphragm structure, the lower diaphragm plate and a lower copper electrode having an outer shape of 100 × 70 mm and a height of 6 mm, and the other end surface of the rectangular insulating ring. The brazing with the Kovar welding plate was performed at the same time.
【００２３】また、上部銅電極と上部絞り板およびコバ
ールの溶接板を銀ろうを用いてろう付けした。先の絶縁
環をろう付けした下部銅電極１８上にＩＧＢＴのチップ
を置き、溶接板をろう付けした上部電極を被せて溶接板
の外周を溶接する。その後、図示されない置換用パイプ
からパッケージ内をガス置換し、最後に置換用パイプを
閉じて密封した。Further, the upper copper electrode, the upper diaphragm plate and the Kovar welding plate were brazed using silver brazing. The IGBT chip is placed on the lower copper electrode 18 to which the above insulating ring is brazed, the upper electrode brazed to the welding plate is covered, and the outer periphery of the welding plate is welded. Then, the inside of the package was replaced with gas from a replacement pipe (not shown), and finally the replacement pipe was closed and sealed.
【００２４】このようにしたＩＧＢＴのパッケージにお
いても、下部銅電極の反りは問題にならないほど小さか
った。また、従来、角形のセラミックスパッケージにお
いては、下部絞り板の角部に顕著に割れや引きつりを、
生じたが、本実施例の方法においては、下部絞り板の割
れ、引きつりなどがなく、気密不良も無かった。尚、セ
ラミックスとろう付される金属部材との間に挟持される
金属材料としては、Ｆｅ−４２％Ｎｉ合金、コバールの
他、熱膨張係数が１６×１０-6℃-1の鉄も有効であっ
た。Even in such an IGBT package, the warp of the lower copper electrode was so small as not to be a problem. Further, conventionally, in a rectangular ceramic package, cracks or drags are notably formed at the corners of the lower diaphragm plate.
However, in the method of this embodiment, there was no cracking or dragging of the lower diaphragm plate, and there was no airtightness. In addition to the Fe-42% Ni alloy and Kovar, iron having a coefficient of thermal expansion of 16 × 10 -6 ° C -1 is also effective as the metal material sandwiched between the ceramics and the brazed metal member. there were.
【００２５】上記の方法により、大型で銅電極に歪みを
与えず、且つ、良好な気密性の良い、信頼性の高い平型
半導体素子ができる。By the above method, a large flat semiconductor element which does not give strain to the copper electrode and has good airtightness and high reliability can be obtained.
【００２６】[0026]
【発明の効果】以上述べたように、本発明によれば、銅
の絞り板を用い、その絞り板とセラミックスの絶縁環と
の間に、熱膨張係数が銅とセラミックとの間にある金属
板を挟んでろう付けした平型パッケージとすることによ
って、銅電極と銅の絞り板間には熱膨張係数の差による
歪みを発生しない。また、銅絞り板と絶縁環の間の熱膨
張係数の差による歪みは、中間の金属板で緩和される。
更に、銅絞り板は延性に富み、銅絞り板と絶縁環の間の
熱膨張係数の差による歪みを吸収し、銅電極には伝えな
い。As described above, according to the present invention, a copper diaphragm is used, and a metal having a coefficient of thermal expansion between copper and the ceramic is provided between the diaphragm and the ceramic insulating ring. By using the flat package in which the plates are sandwiched and brazed, distortion due to the difference in thermal expansion coefficient does not occur between the copper electrode and the copper diaphragm plate. Further, the strain due to the difference in thermal expansion coefficient between the copper diaphragm and the insulating ring is relaxed by the intermediate metal plate.
Further, the copper diaphragm is rich in ductility, absorbs strain due to the difference in thermal expansion coefficient between the copper diaphragm and the insulating ring, and does not transmit it to the copper electrode.
【００２７】そしてその結果、次の効果が得られる。 銅電極の反りが低減され、銅電極と半導体エレメント
との均一な加圧が可能となるとともに、熱の放熱性が向
上し、信頼性も高められる。 二次的な電極面の加工が不要となる。 絞り板の割れや引きつりがないため、パッケージの気
密性が向上する。 絶縁環の内径に対してより大きな銅電極構造とするこ
とができる。As a result, the following effects can be obtained. The warp of the copper electrode is reduced, uniform pressurization between the copper electrode and the semiconductor element is possible, the heat dissipation is improved, and the reliability is improved. Secondary machining of the electrode surface becomes unnecessary. Since there is no cracking or dragging of the diaphragm plate, the airtightness of the package is improved. The copper electrode structure can be made larger than the inner diameter of the insulating ring.
【００２８】すなわち、これらの効果を通じて本発明
は、電力用半導体素子の一層の大型化、高信頼化に資す
るものである。In other words, through these effects, the present invention contributes to further increase in size and reliability of the power semiconductor element.
【図１】本発明の実施例の平型半導体素子の断面図FIG. 1 is a sectional view of a flat semiconductor device according to an embodiment of the present invention.
【図２】従来の平型半導体パッケージの断面図FIG. 2 is a sectional view of a conventional flat semiconductor package.
１、１１ 上部銅電極 ２、１２ 上部絞り板 ３、１３ 上部溶接板 ４、１４ 位置決めガイド ５、１５ 下部溶接板 ６、１６ 絶縁環 ７、１７ 下部絞り板 ８、１８ 下部銅電極 ９、１９ 半導体エレメント １０ 平型パッケージ ２０ 金属板 1, 11 Upper copper electrode 2, 12 Upper diaphragm plate 3, 13 Upper welding plate 4, 14 Positioning guide 5, 15 Lower welding plate 6, 16 Insulation ring 7, 17 Lower diaphragm plate 8, 18 Lower copper electrode 9, 19 Semiconductor Element 10 Flat package 20 Metal plate
Claims (4)
絞り板がろう付けされた平型パッケージに封入された平
型半導体素子において、銅からなる絞り板が、熱膨張係
数がセラミックスより大きく、ろう付する絞り板より小
さい金属板を間に挟んで絶縁環の端面に一体ろう付けさ
れていることを特徴とする平型半導体素子。1. A flat semiconductor device enclosed in a flat package in which a peripheral plate of a copper electrode is brazed to an insulating ring made of ceramics. The diaphragm plate made of copper has a coefficient of thermal expansion larger than that of ceramics. A flat semiconductor device characterized by being integrally brazed to an end face of an insulating ring with a metal plate smaller than a diaphragm plate to be brazed in between.
１０-6℃-1であることを特徴とする請求項１に記載の平
型半導体素子。2. The thermal expansion coefficient of the metal plate is 8 × 10 −6 to 20 ×.
The flat semiconductor device according to claim 1 , wherein the temperature is 10 -6 ° C -1 .
ル、鉄のいずれかからなることを特徴とする請求項１に
記載の平型半導体素子。3. The flat semiconductor element according to claim 1, wherein the metal plate is made of 42% Ni—Fe alloy, Kovar, or iron.
求項１ないし３のいずれかに記載の平型半導体素子。4. The flat semiconductor device according to claim 1, wherein the insulating ring is a square ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28004695A JP3353570B2 (en) | 1995-08-21 | 1995-10-27 | Flat semiconductor element |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21150995 | 1995-08-21 | ||
| JP7-211509 | 1995-08-21 | ||
| JP28004695A JP3353570B2 (en) | 1995-08-21 | 1995-10-27 | Flat semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09120971A true JPH09120971A (en) | 1997-05-06 |
| JP3353570B2 JP3353570B2 (en) | 2002-12-03 |
Family
ID=26518693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28004695A Expired - Fee Related JP3353570B2 (en) | 1995-08-21 | 1995-10-27 | Flat semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3353570B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000002425A1 (en) * | 1998-07-07 | 2000-01-13 | Telefonaktiebolaget Lm Ericsson (Publ) | A device and method for mounting electronic components on printed circuit boards |
| CN114175407A (en) * | 2019-07-25 | 2022-03-11 | 京瓷株式会社 | Airtight terminal |
-
1995
- 1995-10-27 JP JP28004695A patent/JP3353570B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000002425A1 (en) * | 1998-07-07 | 2000-01-13 | Telefonaktiebolaget Lm Ericsson (Publ) | A device and method for mounting electronic components on printed circuit boards |
| CN114175407A (en) * | 2019-07-25 | 2022-03-11 | 京瓷株式会社 | Airtight terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3353570B2 (en) | 2002-12-03 |
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