JPH0897164A - Method for diffusion in silicon semiconductor wafer and manufacture of discrete substrate - Google Patents
Method for diffusion in silicon semiconductor wafer and manufacture of discrete substrateInfo
- Publication number
- JPH0897164A JPH0897164A JP25876694A JP25876694A JPH0897164A JP H0897164 A JPH0897164 A JP H0897164A JP 25876694 A JP25876694 A JP 25876694A JP 25876694 A JP25876694 A JP 25876694A JP H0897164 A JPH0897164 A JP H0897164A
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- Prior art keywords
- wafer
- thickness
- diffusion
- gas
- impurity
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、トランジスター，ダイ
オード等のディスクリート用基板の製造における不純物
の深い拡散層の形成及び加工方法、さらに詳しくは、シ
リコン半導体インゴットよりスライスされたウエハ両面
に目的とする不純物の深い拡散層を形成し、ディスクリ
ート（トランジスター，ダイオード等）用基板（片側が
不純物の拡散層で反対側が不純物の未拡散層でその表面
は通常ミラー仕上げされている）を製造する際の拡散前
のウエハの処理方法と拡散方法と拡散後のウエハの加工
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to a method for forming and processing a deep diffusion layer of impurities in the manufacture of discrete substrates such as transistors and diodes, and more specifically to both surfaces of a wafer sliced from a silicon semiconductor ingot. Diffusion when manufacturing a substrate for discretes (transistors, diodes, etc.) (diffusion layer of impurities on one side and undiffused layer of impurities on the other side, whose surface is usually mirror-finished) by forming a deep diffusion layer of impurities The present invention relates to a wafer processing method before and a diffusion method and a wafer processing method after diffusion.
【０００２】[0002]
【従来の技術】従来、ディスクリート用基板を製造する
方法は、シリコン半導体インゴットよりスライスしたウ
エハを研磨剤にてラップ加工し又は更にエッチング加工
したウエハを使用してまず第一段階の拡散（即ち、デポ
ジション）として、ボート上に一定間隔をおいて配列し
た複数の素材ウエハを拡散チューブ内に格納し、そのチ
ューブ内に目的とする不純物（Ｐ又はＢ等）のソースを
含むキャリアガス、一般的にはＮ2 及びＯ2 ガスの混合
ガスを送って所望の温度，時間で熱処理し、前記不純物
をウエハ両面に浅く高濃度に拡散させる。2. Description of the Related Art Conventionally, a method of manufacturing a discrete substrate is a method of first diffusing (ie, diffusing) a wafer sliced from a silicon semiconductor ingot and lapped with an abrasive or further etched. As a deposition), a plurality of material wafers arranged at regular intervals on a boat are stored in a diffusion tube, and a carrier gas containing a source of a target impurity (P or B etc.) in the tube is generally used. the desired temperature by sending a mixed gas of N 2 and O 2 gas, and the heat treatment time, is diffused in a high concentration shallow the impurity on the wafer both sides.
【０００３】次に第二段階の拡散（押込み拡散）とし
て、前記デポジション済みの各ウエハを別のボート上に
ＳｉＯ2 粉等を介してお互いに密着させて配設し、拡散
チューブ内にてキャリアガス（Ｎ2 及びＯ2 ガスの混合
ガス）雰囲気下で高温，長時間熱処理して、前記不純物
を所望の深さまで拡散させると共に所望の不純物表面濃
度を達成するようになっていた。前記ウエハの片側の拡
散層は研削加工にて完全に除去し、不純物の未拡散層は
所定の厚みを残してその表面は通常ミラー仕上げしてデ
ィスクリート用基板を製造していた。Next, as a second stage of diffusion (push-in diffusion), the deposited wafers are placed on another boat in close contact with each other via SiO 2 powder or the like, and are placed in a diffusion tube. Heat treatment was performed in a carrier gas (mixed gas of N 2 and O 2 gas) at a high temperature for a long time to diffuse the impurities to a desired depth and achieve a desired impurity surface concentration. The diffusion layer on one side of the wafer is completely removed by grinding, and the non-diffusion layer of impurities has a predetermined thickness, and the surface thereof is usually mirror-finished to manufacture a discrete substrate.
【０００４】[0004]
【発明が解決しようとする課題】従来の方法によると高
温，長時間の第二の拡散工程においてウエハ両面に「粒
子」と呼ばれる化合物が生成してしまっていた。この
「粒子」と呼ばれるものを説明すると、組成的には、
Ｎ，Ｏ，Ｓｉ，不純物（Ｐ又はＢ），その他よりなって
いることは判明しているが、素材ウエハの結晶軸方向に
成長する極めて完全性の高い結晶であってフッ酸はもと
より王水にも溶解せず、現状においては適切な除去手段
が見当らないことから、引続く製造工程（機械加工工
程，次の拡散工程，洗浄工程等）において脱落する等し
て様々な悪影響を及ぼしていた。According to the conventional method, compounds called "particles" are formed on both surfaces of the wafer in the second diffusion step at high temperature for a long time. Explaining what is called "particles", compositionally,
It is known that it is composed of N, O, Si, impurities (P or B), etc., but it is a crystal with extremely high perfectness that grows in the crystal axis direction of the material wafer, and it is not only hydrofluoric acid but also aqua regia. However, since it does not dissolve and there is no suitable removing means at present, it has been adversely affected by being dropped off in the subsequent manufacturing process (machining process, next diffusion process, cleaning process, etc.). .
【０００５】上記「粒子」については、図１（ａ），
（ｂ），（ｃ）に倍率を変えたＳＥＭ写真を示してあ
る。この顕微鏡写真例は、ＦＺ法により作製した面方位
（１１１）のデポジション済みウエハを従来の所定条件
で高温，長時間拡散した時に、ウエハ表面に生成した
「粒子」形態の一例を示し、（１１１）の場合は核らし
きものを中心として結晶方向（１２０°）に成長してい
る様に観察できる。尚、この倍率の電子顕微鏡（ＳＥ
Ｍ）写真は、「粒子」の像を鮮明にするために拡散終了
後のウエハの表面を浅くエッチング処理して撮影したも
のである。Regarding the above-mentioned "particles", refer to FIG.
(B) and (c) show SEM photographs with different magnifications. This micrograph example shows an example of a "particle" morphology generated on the wafer surface when a deposited wafer having a plane orientation (111) produced by the FZ method is diffused at a high temperature for a long time under the conventional predetermined conditions. In the case of (111), it can be observed that the nucleus seems to grow in the crystal direction (120 °). In addition, the electron microscope (SE
M) The photograph was taken by shallowly etching the surface of the wafer after the completion of diffusion in order to make the image of “particles” clear.
【０００６】この粒子生成の原因としてラップ加工時に
形成される加工歪が影響すると考え、更にエッチング加
工（取代２０μ）し加工歪を除去して有効な対策として
きたが、 現在ディスクリート用基板として利用されるウエハ
の面方位は主に（１１１）及び（１００）であるが、面
方位（１１１）ウエハに対しては有効であるものの、面
方位（１００）ウエハに対しては不十分であることが判
明してきた〔特に面方位（１００）ウエハを使用したパ
ワーＭＯＳ系ＦＥＴの深い拡散層（例２５０〜３００
μ）については無力である〕。 その上、面方位（１１１）ウエハに対しては有効で
あるものの、加工歪除去により加工歪が本来もっている
ゲッターリング効果も失われ、このことは第二の拡散工
程中に不純物の拡散（侵入）による未拡散層内に発生す
る転位の吸収作用が失われ、未拡散側の表面に著しく不
均一に分布する転位が発生する。It is considered that the processing strain formed during the lapping process has an influence as a cause of the generation of the particles, and the processing strain is removed by further performing the etching process (20 μ of machining allowance), which has been taken as an effective countermeasure. However, it is currently used as a discrete substrate. The plane orientations of the wafers are mainly (111) and (100), but they are effective for the plane orientation (111) wafers but insufficient for the plane orientation (100) wafers. It has become clear [especially for deep diffusion layers of power MOS FETs using plane orientation (100) wafers (Examples 250 to 300).
μ) is helpless]. Moreover, although effective for the plane-oriented (111) wafer, the gettering effect originally caused by the processing strain is lost by removing the processing strain, which means that the impurity diffusion (penetration) occurs during the second diffusion process. The absorption effect of dislocations generated in the non-diffused layer due to (4) is lost, and dislocations remarkably unevenly distributed occur on the surface on the non-diffused side.
【０００７】ディスクリートがトランジスターであれば
この未拡散層は次のベース，エミッターの形成する層で
あり、不均一な転位の分布は素子となった時の特性の劣
化（特にリーク電流）及びそのバラツキの原因をもたら
す。〔この状態を図２（Ａ）に示す。ウエハは面方位
（１１１）で拡散層は１６０μで未拡散層は９０μでそ
の面はミラー仕上げされている。このウエハのミラー面
をジルトルエッチして転位をエッチピット（三角形）と
し現し光の反射のない様に工夫して写真撮影したもので
ある。図中「シマ」状の白く観える部分が転位（エッチ
ピット）の密集部であり、これの一部分を拡大して図３
に示す。〕かといって加工歪を除去しないと多大な粒子
が発生してしまう。というジレンマがある。If the discrete transistor is a transistor, this non-diffused layer is a layer formed by the next base and emitter, and the uneven distribution of dislocations deteriorates the characteristics (especially leakage current) when it becomes an element and its variation. Bring the cause of. [This state is shown in FIG. The surface orientation of the wafer is (111), the diffusion layer is 160 μ, the non-diffusion layer is 90 μ, and its surface is mirror-finished. The mirror surface of this wafer was dill-etched to show dislocations as etch pits (triangles), and the photograph was taken so as not to reflect light. In the figure, the "striped" white part is a dense dislocation (etch pit) part, and a part of it is enlarged and shown in FIG.
Shown in. However, if the processing strain is not removed, a large amount of particles will be generated. There is a dilemma.
【０００８】本発明は上述したような従来の技術が有す
る問題点に鑑みてなされたものでその目的とするところ
は、ウエハ面方位（１１１）又は（１００）にかかわら
ず粒子の生成を防止し転位の均一化及び低転位化を同時
に達成することにある。The present invention has been made in view of the problems of the above-mentioned conventional techniques, and an object of the present invention is to prevent generation of particles regardless of the wafer plane orientation (111) or (100). The aim is to achieve uniform dislocations and low dislocations at the same time.
【０００９】[0009]
【課題を解決するための手段】前述の目的を達成する為
に本発明は以下の手段を採用する。即ち請求項１に係る
手段は、シリコン単結晶のインゴットよりスライスされ
たウエハを研磨剤（ＦＯ＃１０００、又は＃１２００）
で両面同時にラップ加工（取代６０μ）し、均一な加工
歪を付与し、拡散終了後の加工方法に合せた所要厚さの
面方位（１１１）又は（１００）のウエハを使用して目
的とする不純物の雰囲気下でウエハ両面にデポジション
する第一の拡散工程と、該ウエハをＯ2 ガス０．５％〜
１０（ｖｏｌ）％を含むＡｒ又はＨｅの混合ガスの雰囲
気下で高温，長時間の拡散をする第二の拡散工程より成
り、上記の所要厚さは不純物の拡散層厚をｘj 、ディス
クリート基板となった時の未拡散層厚をｘi とすると、
その時のウエハ厚ｔ1 は、２ｘj ＋ｘi ＋２０≦ｔ1 ≦
２ｘj ＋ｘi ＋８０である。In order to achieve the above object, the present invention employs the following means. That is, the means according to claim 1 uses a polishing agent (FO # 1000 or # 1200) for a wafer sliced from a silicon single crystal ingot.
Then, both sides are simultaneously lapped (removal allowance: 60μ), uniform processing strain is given, and a wafer having a plane orientation (111) or (100) of a required thickness suitable for the processing method after completion of diffusion is used. a first diffusion step of depositing the wafer both sides in an atmosphere of impurities, the wafer O 2 gas 0.5%
It comprises a second diffusion step in which diffusion is carried out at high temperature for a long time in an atmosphere of a mixed gas of Ar or He containing 10 (vol)%, and the required thickness is the diffusion layer thickness of impurities x j , the discrete substrate. When the undiffused layer thickness is x i ,
The wafer thickness t 1 at that time is 2x j + x i + 20 ≦ t 1 ≦
2x j + x i +80.
【００１０】請求項２に係る手段は、シリコン単結晶の
インゴットよりスライスされたウエハを研磨剤（ＦＯ＃
１０００又は＃１２００）で両面同時にラップ加工（取
代６０μ）し、均一な加工歪（略数μ）を付与し拡散後
の加工方法に合せた所要厚の面方位（１１１）又は（１
００）のウエハを使用してウエハ両面に上記のデポジシ
ョンする第一の拡散工程と、該ウエハをＯ2 ガス０．５
％〜１０（ｖｏｌ）％含むＡｒ又はＨｅの混合ガスの雰
囲気下で高温，長時間の拡散をする第二の拡散工程と、
該ウエハを枚葉式に内周刃切断装置でその厚み幅の中央
部より２分割に切断し、その切断面側を研削，研磨加工
する工程の組合せより成るディスクリート用基板製造方
法を採用する。そして、上記の拡散後の加工方法に合わ
せたウエハの所要厚さｔ2 は、内周刃切断装置の刃厚を
ｔc （μｍ）とすると、２（ｘj ＋ｘi ）＋ｔc ＋７５
≦ｔ2≦２（ｘj ＋ｘi ）＋ｔc ＋３００である。According to a second aspect of the present invention, a wafer sliced from a silicon single crystal ingot is polished with a polishing agent (FO #).
1000 or # 1200), both sides are simultaneously lapped (working allowance of 60μ), uniform processing strain (approx. Several μ) is given, and the plane orientation of the required thickness (111) or (1) is adjusted according to the processing method after diffusion.
00) wafer is used to perform the above first deposition step on both sides of the wafer, and the wafer is subjected to O 2 gas 0.5
% To 10 (vol)% in a mixed gas atmosphere of Ar or He at high temperature for a long time, and a second diffusion step,
A method for manufacturing a discrete substrate is adopted in which the wafer is cut into two pieces from the center of its thickness width by a single-wafer type inner peripheral blade cutting device, and the cutting surface side is ground and polished. The required thickness t 2 of the wafer according to the processing method after diffusion is 2 (x j + x i ) + t c +75, where t c (μm) is the blade thickness of the inner peripheral blade cutting device.
≦ t 2 ≦ 2 (x j + x i ) + t c +300.
【００１１】[0011]
【作用】請求項１に係る作用について述べる前に現段階
で結論づけられている粒子生成のメカニズムについて説
明する。この粒子生成のメカニズムについては、粒子の
組成分析（目的とする不純物にデコレートされたＮ，
Ｏ，Ｓｉの化合物）及び今まで判明している事実より粒
子生成の根本原因は、「ウエハが拡散時に高温，長時間
のＯ2 ガス及びＮ2 ガスの共存する雰囲気下に晒される
こと」にあると考えられ、「ウエハ両面の加工歪の有無
又はウエハ面方位（１１１），（１００）の差は粒子生
成に大きく影響を与えＮ2 ガスの割合の高い程、又当然
のことながらより高温、より長時間の程、粒子生成数も
多く、そのサイズも大きくなる」ことが確認されてい
る。そして上記根本原因は、 Ｏ2 ガス１００％ 又は′Ｏ2 ガスとＮ2 ガス
以外の他ガスの混合 Ｎ2 ガス１００％ 又は′Ｎ2 ガスとＯ2 ガス
以外の他ガスの混合 のいずれの雰囲気下でも他の条件に因らず粒子の生成の
ないことで裏付けされる。Before the operation according to claim 1 is described, the mechanism of particle formation, which has been concluded at this stage, will be described. Regarding the mechanism of particle generation, the composition analysis of particles (N, N
O, Si compounds) and the facts that have been known so far are that the root cause of particle formation is that "the wafer is exposed to a high temperature and a long-term coexisting atmosphere of O 2 gas and N 2 gas during diffusion". It is considered that “the presence or absence of processing strain on both sides of the wafer or the difference between the wafer plane orientations (111) and (100) has a large influence on particle generation, and the higher the proportion of N 2 gas, the higher the temperature of course is. , And the longer the time, the greater the number of particles produced and the larger their size. ” And the root cause, O 2 gas of 100% or 'O 2 gas and N 2 100% other gases mixed N 2 gas other than the gas or' any atmosphere of a mixed of N 2 gas and another gas other than O 2 gas Even below, it is supported by the absence of particle formation regardless of other conditions.
【００１２】以下請求項１に係る作用について説明する
と、請求項１は粒子生成のないより低転位のディスクリ
ート用基板を製造する方法であり、これらを簡明に記す
ると以下の２条件、即ち、（１）素材ウエハは研磨剤
（ＦＯ＃１２００又は＃１０００）にてラップ加工され
両面に均一な「加工歪」（１〜１０μ）を有しているこ
と及び、（２）第二拡散はＯ2 ＋Ａｒガス（Ｈｅガス）
の雰囲気下で行うことであり、条件（１）の均一に分布
する加工歪はそれが本来有しているゲッターリング効果
により第二拡散中に不純物の拡散により不純物の未拡散
層内に発生する転位を吸収し、かつ条件（２）で行なっ
ているため粒子の生成もない。即ち条件（１）（２）は
粒子生成のない低転位ウエハ製造のためのお互いに補完
し合う対の条件である。ディスクリート基板は片側の拡
散層（ｘj ）と反対側の未拡散層（ｘi ）よりなるが、
素材ウエハとしては最小限２ｘj ＋ｘi の厚さが必要で
あり、加工余裕代は２０μ以上と過大にならない様な８
０μ以下である。The operation according to claim 1 will be described below. Claim 1 is a method for producing a discrete dislocation substrate having a lower dislocation without generation of particles. To briefly describe these, the following two conditions, that is, ( 1) The material wafer is lapped with an abrasive (FO # 1200 or # 1000) and has a uniform “processing strain” (1 to 10 μ) on both sides, and (2) the second diffusion is O 2 + Ar gas (He gas)
The processing strain uniformly distributed under the condition (1) is generated in the non-diffused layer of impurities due to the diffusion of impurities during the second diffusion due to the gettering effect which it originally has. No particles are generated because the dislocations are absorbed and the condition (2) is used. That is, the conditions (1) and (2) are mutually complementary pair conditions for the production of low-dislocation wafers without grain formation. The discrete substrate comprises a diffusion layer (x j ) on one side and a non-diffusion layer (x i ) on the other side,
As a material wafer, a minimum thickness of 2x j + x i is required, and the processing allowance is 20 μ or more so that it does not become excessive.
It is 0 μ or less.
【００１３】次に請求項２に係る作用について説明す
る。請求項２は簡明に記すと以下の３条件、即ち、
（１）素材ウエハは研磨剤（ＦＯ＃１２００又は＃１０
００）にてラップ加工され両面に均一な「加工歪」（１
〜１０μ）を有して、かつ拡散後の加工を考慮した通常
の倍程の「特別な厚さ」を有すること、（２）第二拡散
はＯ2 ＋Ａｒガス（又はＨｅガス）の雰囲気下であるこ
と、（３）拡散終了後のウエハはその厚み幅の中央部よ
り２分割に切断し、所要の厚さのディスクリート用基板
に仕上げること（当然のことながら素材ウエハ１枚に対
して２枚のディスクリート用基板を得る）、であり、条
件（１）の「加工歪」及び（２）に係る作用は前述した
ものと基本的には同一と考えられるが、この時にウエハ
は「加工歪」を有するだけでなく通常の倍程の所要厚さ
（後述）を有しており、このことは転位に関して請求項
１に係る通常のウエハの厚さで得られる効果（転位レベ
ル）の又更に数分の一程に下げることが実証されてい
る。（例えば、拡散深さが１６０μ、未拡散層が９０μ
の一例で述べるとＦＺ法によるウエハについては１／１
０に、そしてＣＺ法によるウエハについては１／２〜１
／３程度に減少できる。） 尚、この理由についてはウエハ中央部の未拡散が厚い分
だけ転位発生が緩和されると考えても現象と一致する。
したがって、条件（１）の素材ウエハが更に低転位化を
目標として「特別な厚さ」のウエハを使用できるために
は、条件（３）が不可欠である。以上の様に条件（１）
（２）及び（３）はお互いに補完し合って、粒子生成の
ない極めて低転位の高品位ディスクリート用基板の提供
を可能とすることができる。Next, the operation according to claim 2 will be described. Briefly speaking, claim 2 has the following three conditions:
(1) The material wafer is an abrasive (FO # 1200 or # 10
00) lap processing and uniform "processing distortion" on both sides (1
10 μ) and having a “special thickness” that is about twice the normal amount in consideration of processing after diffusion, (2) The second diffusion is in an atmosphere of O 2 + Ar gas (or He gas). (3) The wafer after the diffusion is cut into two parts from the center of the thickness width, and finished into a discrete substrate with a required thickness (naturally, 2 It is considered that the operation relating to the condition (1) "working strain" and the condition (2) is basically the same as that described above, but at this time, the wafer is "working strain". In addition to the above, it also has a required thickness (which will be described later) about twice as much as usual, which means that in addition to the effect (dislocation level) obtained with the normal wafer thickness according to claim 1 on dislocation, It has been proved to lower it to a few minutes. (For example, the diffusion depth is 160μ and the undiffused layer is 90μ.
For example, it is 1/1 for a wafer manufactured by the FZ method.
0, and 1/2 to 1 for CZ wafers
It can be reduced to about / 3. Note that the reason for this is in agreement with the phenomenon even if it is considered that the generation of dislocations is alleviated by the amount of undiffusion in the central portion of the wafer being thick.
Therefore, the condition (3) is indispensable so that the raw material wafer of the condition (1) can be used as a wafer having a “special thickness” for the purpose of further reducing dislocation. As described above, condition (1)
(2) and (3) complement each other, and it is possible to provide an extremely low dislocation-free, high-quality discrete substrate without grain formation.
【００１４】又、素材ウエハの所要厚さ（ｔ2 ）は次式
であり、 ２（ｘj ＋ｘi ）＋３３０＋７５≦ｔ2 ≦２（ｘj ＋ｘ
i ）＋３３０＋３００ その式中の｛２（ｘj ＋ｘi ）＋３３０｝は加工形態を
考えた必要最小限の厚さであり、（７５μ〜３００μ）
×１／２はディスクリート用基板１枚当りの切断面側の
研削，研磨代であり、最小限３７．５μは必要であり、
特性（低転位）を重視して意識的に更に厚くする場合の
他は１５０μ以上はコスト的に無理をきたす。尚、請求
項１及び２におけるＯ2 ガス割合が０．５％〜１０％と
なっているのは、０．５％以上のＯ2 ガスは高温，長時
間の拡散中にＳｉＯ2 膜が形成されていってＳｉ原子の
蒸発を防ぎ、又逆に１０％以下のＯ2 ガスは過度のＳｉ
Ｏ2 膜形成による面のアレ（アバタ，クラック等）を防
止する。請求項３，４及び請求項５，６に係る作用はい
ずれもが本発明の対象としている実用上の範囲である。The required thickness (t 2 ) of the material wafer is given by the following equation: 2 (x j + x i ) + 330 + 75 ≦ t 2 ≦ 2 (x j + x
i ) + 330 + 300 {2 (x j + x i ) +330} in the formula is the minimum necessary thickness considering the processing form, (75 μ to 300 μ)
× 1/2 is the grinding and polishing allowance on the cut surface side for each discrete substrate, and a minimum of 37.5μ is required,
Except for the purpose of intentionally increasing the thickness with emphasis on the characteristic (low dislocation), 150 μm or more causes cost prohibition. The O 2 gas ratio in claims 1 and 2 is 0.5% to 10% because the O 2 gas of 0.5% or more forms a SiO 2 film during diffusion at high temperature for a long time. Therefore, the vaporization of Si atoms is prevented, and conversely 10% or less of O 2 gas is excessive Si.
Prevents surface irregularities (avatars, cracks, etc.) due to the O 2 film formation. The operations according to claims 3 and 4 and claims 5 and 6 are all within the practical range targeted by the present invention.
【００１５】[0015]
【実施例】以下本発明に係る実施例について説明する。
「表１」は従来法と本発明法との「粒子」及び「転位」
に係る比較表で、ＦＺ法により作製した口径１００φの
面方位（１００）のウエハと、ＦＺ法により作製した口
径１００φの面方位（１１１）のウエハ２種を対象とし
て、従来法と本発明法に分けて実施した結果である。拡
散深さは１６０μでディスクリート用基板となった時の
未拡散層は９０μで、全厚さは２５０μとなる。ウエハ
厚さは標準によるものは２ｘj ＋ｘi ＋４５＝４５５μ
で、拡散終了後２分割切断するものは２（ｘj ＋ｘi ）
＋３３０＋１５０＝９８０μである。従来法はシリコン
単結晶のインゴットよりスライスされたウエハを研磨剤
（ＦＯ＃１２００）でラップ加工（取代６０μ）したも
のと、更にエッチング加工（取代２０μ）を対象に一般
的洗浄後、Ｐ（リン）雰囲気中でデポジションし、引き
続きＯ2 ガス：Ｎ2 ガスが１：３よりなる雰囲気中で高
温（１２８０℃），長時間（１５０Ｈｒ）拡散し、終了
後片側の拡散層は完全に除去し、中央部の不純物の未拡
散層厚が９０μになる様に研削後研磨加工し、ミラー面
に仕上げたものである。EXAMPLES Examples according to the present invention will be described below.
"Table 1" shows "particles" and "dislocations" between the conventional method and the method of the present invention.
In the comparison table according to the above, the conventional method and the method of the present invention are applied to two types of wafers having a plane orientation (100) of 100φ diameter produced by the FZ method and two wafers having a plane orientation (111) of 100φ diameter produced by the FZ method. It is the result of carrying out by dividing into. The diffusion depth is 160μ, the undiffused layer is 90μ when it is used as a discrete substrate, and the total thickness is 250μ. The standard wafer thickness is 2x j + x i + 45 = 455μ
And, the one that is cut into two after the diffusion is 2 (x j + x i )
It is + 330 + 150 = 980μ. In the conventional method, a wafer sliced from a silicon single crystal ingot is lapped with a polishing agent (FO # 1200) (60 μ removal allowance), and after further general cleaning for etching (20 μ removal allowance), P (phosphorus) is used. ) Deposition in an atmosphere, followed by diffusion at a high temperature (1280 ° C.) for a long time (150 hours) in an atmosphere of O 2 gas: N 2 gas of 1: 3, and after completion, the diffusion layer on one side is completely removed. The mirror surface is finished by grinding and polishing so that the thickness of the non-diffused layer of impurities in the central portion becomes 90 μm.
【００１６】一方、本発明法によるものは同じくラップ
加工された４５５μ及び９８０μのウエハを一般的な洗
浄後、同じくＰ（リン）雰囲気下でデポジションし、引
き続きＯ2 ガス５％を含むＡｒガスの雰囲気中で高温，
長時間の拡散を行い、終了後厚み幅の中央部より２分割
に切断し、厚さ３２５μのウエハを得てその切断面側を
研削，研磨加工し、ミラー面に仕上げたものである。粒
子数はディスクリート用基板のＨＦ処理した拡散層側表
面をＳＥＭでウエハ中心を数回観察し、視野内の平均的
粒子数を単位面積換算して示した。又、転位はディスク
リート用基板の未拡散層側のミラー面をジルトルエッチ
ングし、光学的顕微鏡で視野内のエッチピット数を単位
面積換算したＥＰＤ値（エッチピット密度数）で示し
た。右側数値はウエハ中心の値であり左側数値はウエハ
外周４点の平均値を示す。但し、面方位（１００）はエ
ッチピット（三角形）としては観察できず、小さい円形
窪みとして現われるものをカウントしたため、参考用と
いう意味で（ ）で示した。On the other hand, according to the method of the present invention, the same lapping 455 μ and 980 μ wafers are generally washed, and then deposited in the same P (phosphorus) atmosphere, and then Ar gas containing 5% of O 2 gas is continuously applied. High temperature in the atmosphere of
After being diffused for a long time, after completion, it is cut into two parts from the central part of the thickness width, a wafer having a thickness of 325 μ is obtained, and the cut surface side is ground and polished to be a mirror surface. The number of particles is shown by observing the surface of the discrete substrate on the side of the HF-treated diffusion layer several times with a SEM at the center of the wafer and converting the average number of particles in the visual field into a unit area. The dislocations are shown as EPD values (etch pit density numbers) obtained by uniting the number of etch pits in the visual field with an optical microscope after the mirror surface on the side of the non-diffusion layer of the discrete substrate was etched. The numerical value on the right side is the value at the center of the wafer, and the numerical value on the left side is the average value of four points on the outer periphery of the wafer. However, the plane orientation (100) cannot be observed as etch pits (triangles), and those appearing as small circular pits were counted. Therefore, () is shown for reference.
【００１７】[0017]
【表１】 [Table 1]
【００１８】従来法（１）は面方位（１１１）には粒子
が生成しないが（１００）には多数発生しており、面方
位（１１１）及び（１００）は共に著しく転位が不均一
に分布している〔図２（Ａ）〕。従来法（２）は転位の
不均一性は消滅〔図２（Ｂ）〕しているものの粒子の発
生は最大である。これはウエハ表面に形成されている加
工歪の影響と考えられる。本発明法の（１）及び（２）
によるものはウエハ面方位（１１１）及び（１００）共
に粒子の生成はなく、かつ本発明（２）によるものは転
位は加工歪によって吸収されたレベル〔従来法（２）の
（１１１）ウエハの２５２０〜２０７０ケ／ｃｍ2 〕よ
り更に１桁程低下させることができており、最終的目標
としている未拡散層内に結晶欠陥を発生させない無欠陥
拡散法に近づいたものとなっている。尚、本実施例はＦ
Ｚ法によるウエハを対象としたが、ＣＺ法によるものは
転位の発生レベルに差（ＣＺ法によるものは転位が発生
しやすい）は生じるものの同様の傾向であり、粒子の生
成についても傾向の差は生じない。In the conventional method (1), particles are not generated in the plane orientation (111), but a large number are generated in the plane orientation (100), and both the plane orientations (111) and (100) remarkably disperse nonuniformly. (FIG. 2 (A)). In the conventional method (2), the nonuniformity of dislocations disappears [Fig. 2 (B)], but the generation of grains is maximum. This is considered to be due to the processing strain formed on the wafer surface. (1) and (2) of the method of the present invention
According to the present invention (2), dislocations are absorbed by the processing strain (particles of the (111) wafer of the conventional method (2)). 2520 to 2070 cells / cm 2 ], and it is closer to the defect-free diffusion method in which crystal defects are not generated in the undiffused layer, which is the final target. In this example, F
Although the wafer by the Z method was targeted, the CZ method has a similar tendency although there is a difference in the dislocation generation level (the CZ method tends to generate dislocations), and the difference in the tendency also in particle generation. Does not occur.
【００１９】又、本発明法（２）によるものは拡散層の
特に深いもの（例えば２００μ以上）については圧倒的
に品質面，コスト面で有利であり、本発明法（１）によ
るものについては拡散層の浅いもの（２０μ〜８０μ）
及び２つのオリエンテーションフラット〔片方は一般的
にＣＦ（カットフラット）とよばれる〕を有して２分割
切断が不適合のものに有用である。The method (2) of the present invention is overwhelmingly advantageous in terms of quality and cost for a deep diffusion layer (for example, 200 μ or more), and the method (1) of the present invention is used. Shallow diffusion layer (20-80μ)
And having two orientation flats, one of which is commonly referred to as a CF (cut flat), is useful for those incompatible with a two-piece cut.
【００２０】[0020]
【発明の効果】以上説明したように本発明の拡散方法に
よれば、シリコン半導体ウエハに深い拡散層を形成して
ディスクリート用基板を製造していく時に、本発明によ
るラップ加工された均一な加工歪を有してその後の２分
割切断可能な厚さのウエハを使用してＯ2 ガスを含むＡ
ｒガス又はＨｅガスの雰囲気下で高温，長時間の拡散を
し、拡散後その厚み幅の中央部より２分割に切断し、そ
の切断面側を研削，研磨してディスクリート用基板に仕
上げる方法は粒子生成のない極めて低転位の高品位の製
品とすることができ、それ以降の工程における粒子剥離
等による問題（ミラー面への付着，蒸着不良）を未然に
防止することができ生産性を向上できると共に、無欠陥
拡散に近い極めて低転位の不純物未拡散層を利用して特
性のすぐれたディスクリートを製造することができる。As described above, according to the diffusion method of the present invention, when a discrete substrate is manufactured by forming a deep diffusion layer on a silicon semiconductor wafer, uniform lapping according to the present invention is performed. A containing O 2 gas using a wafer having a thickness that is distorted and is capable of being cut in two parts
A method of diffusing at a high temperature for a long time in an atmosphere of r gas or He gas, cutting into two parts from the central part of the thickness width after diffusion, and grinding and polishing the cut surface side to finish a discrete substrate is It can be a high-quality product with extremely low dislocations that does not generate particles, and can prevent problems such as particle peeling in subsequent processes (adhesion to the mirror surface, vapor deposition failure) and improve productivity. In addition, it is possible to manufacture a discrete having excellent characteristics by utilizing an impurity undiffused layer having an extremely low dislocation close to defect-free diffusion.
【図１】従来の方法によって生成された粒子構造を示す
顕微鏡写真である。FIG. 1 is a micrograph showing a grain structure produced by a conventional method.
【図２】ウエハのミラー面に生じた転位の結晶構造を示
す写真である。FIG. 2 is a photograph showing a crystal structure of dislocations generated on a mirror surface of a wafer.
【図３】図２（Ａ）の結晶構造を示す写真の部分拡大写
真である。FIG. 3 is a partially enlarged photograph of the photograph showing the crystal structure of FIG.
Claims (6)
あるシリコン単結晶のインゴットを所定厚さにスライス
し、得られたウエハを研磨剤を用いて両面同時にラッピ
ングした下記（１）式の厚さ（ｔ1 ）のウエハ面方位
（１１１）または（１００）のウエハ面に不純物の雰囲
気中でデポジションする第１の拡散工程と、第１拡散工
程終了後のウエハをＯ2 ガス０．５〜１０（ｖｏｌ）％
を含むＡｒまたはＨｅの混合ガス雰囲気中で高温度で長
時間処理し、該ウエハの中央部に不純物の未拡散層を有
し両面に不純物の拡散層を形成したウエハを得る第２の
拡散工程とより成るシリコン半導体ウエハの拡散方法。 ２ｘj ＋ｘi ＋２０≦ｔ1 ≦２ｘj ＋ｘi ＋８０………(1) ｘj ：ウエハ不純物拡散層厚（μｍ） ｘi ：ディスクリート基板となった時のウエハ不純物未
拡散層厚（μｍ）1. A silicon single crystal ingot having a crystal axis of <111> or <100> is sliced to a predetermined thickness, and the obtained wafer is simultaneously lapped on both sides with an abrasive to obtain a film of the following formula (1). A first diffusion step of depositing a wafer surface orientation (111) or (100) having a thickness (t 1 ) in an atmosphere of impurities, and a wafer after the completion of the first diffusion step are treated with O 2 gas of 0. 5-10 (vol)%
Second diffusion step for obtaining a wafer in which a non-diffused layer of impurities is formed in the central portion of the wafer and impurity diffused layers are formed on both sides of the wafer, which is treated at a high temperature for a long time in a mixed gas atmosphere of Ar or He containing A method of diffusing a silicon semiconductor wafer comprising: 2x j + x i + 20 ≦ t 1 ≦ 2x j + x i +80 (1) x j : Wafer impurity diffusion layer thickness (μm) x i : Wafer impurity non-diffusion layer thickness (μm) when a discrete substrate is formed
あるシリコン単結晶のインゴットを所定厚さにスライス
し、得られたウエハを研磨剤を用いて両面同時にラッピ
ングした下記（２）式の厚さ（ｔ2 ）のウエハ面方位
（１１１）または（１００）のウエハ面に不純物の雰囲
気中でデポジションする第１の拡散工程と、第１拡散工
程終了後のウエハをＯ2 ガス０．５〜１０（ｖｏｌ）％
を含むＡｒまたはＨｅの混合ガス雰囲気中で高温度で長
時間処理し、該ウエハの中央部に不純物の未拡散層を有
し両面に不純物の拡散層を形成したウエハを得る第２の
拡散工程と、第２の拡散工程後のウエハを厚み幅の中央
部の不純物未拡散層より枚葉式に内周刃切断装置で２分
割に切断し、該ウエハの切断面を研削・研磨しミラー仕
上げすることを特徴とするディスクリート基板の製造方
法。 ２（ｘj ＋ｘi ）＋ｔc ＋７５≦ｔ2 ≦２（ｘj ＋ｘi ）＋ｔc ＋３００…(2) ｘj ：ウエハ不純物拡散層厚（μｍ） ｘi ：ディスクリート基板となった時のウエハ不純物未
拡散層厚（μｍ） ｔ2 ：ウエハの厚さ（μｍ） ｔc ：内周刃切断装置の刃厚（μｍ）2. A silicon single crystal ingot having a crystal axis of <111> or <100> is sliced to a predetermined thickness, and the obtained wafer is simultaneously lapped on both sides with an abrasive to obtain the following formula (2). A first diffusion step of depositing a wafer plane orientation (111) or (100) having a thickness (t 2 ) in an atmosphere of impurities, and a wafer after the completion of the first diffusion step are treated with O 2 gas of 0. 5-10 (vol)%
Second diffusion step for obtaining a wafer in which a non-diffused layer of impurities is formed in the central portion of the wafer and impurity diffused layers are formed on both sides of the wafer, which is treated at a high temperature for a long time in a mixed gas atmosphere of Ar or He containing Then, the wafer after the second diffusion step is cut into two pieces from the impurity non-diffused layer in the central portion of the thickness width by an inner peripheral blade cutting device, and the cut surface of the wafer is ground / polished to be a mirror finish. A method of manufacturing a discrete substrate, comprising: 2 (x j + x i ) + t c + 75 ≦ t 2 ≦ 2 (x j + x i ) + t c +300 (2) x j : Wafer impurity diffusion layer thickness (μm) x i : Wafer when it becomes a discrete substrate Impurity non-diffused layer thickness (μm) t 2 : Wafer thickness (μm) t c : Blade thickness (μm) of inner peripheral blade cutting device
１３１０℃であることを特徴とするシリコン半導体ウエ
ハの拡散方法3. The high temperature according to claim 1 is 1250 ° C. or higher.
Method of diffusing silicon semiconductor wafer, characterized by being 1310 ° C.
１３１０℃であることを特徴とするディスクリート基板
の製造方法。4. The high temperature according to claim 2 is 1250 ° C. or higher.
1310 degreeC, The manufacturing method of the discrete substrate characterized by the above-mentioned.
５０時間であることを特徴とするシリコン半導体ウエハ
の拡散方法。5. The long time in claim 1 is 20 hours to 4 hours.
A method for diffusing a silicon semiconductor wafer, which is for 50 hours.
５０時間であることを特徴とするティスクリート基板の
製造方法。6. The long time in claim 2 is 20 hours to 4 hours.
A method for manufacturing a tiscrete substrate, which is characterized by being for 50 hours.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6258766A JP2607853B2 (en) | 1994-09-27 | 1994-09-27 | Silicon semiconductor wafer diffusion method and discrete substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6258766A JP2607853B2 (en) | 1994-09-27 | 1994-09-27 | Silicon semiconductor wafer diffusion method and discrete substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0897164A true JPH0897164A (en) | 1996-04-12 |
| JP2607853B2 JP2607853B2 (en) | 1997-05-07 |
Family
ID=17324796
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6258766A Expired - Fee Related JP2607853B2 (en) | 1994-09-27 | 1994-09-27 | Silicon semiconductor wafer diffusion method and discrete substrate manufacturing method |
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| Country | Link |
|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0945530A1 (en) * | 1998-03-26 | 1999-09-29 | Naoetsu Electronics Company | A production method for a discrete structure substrate |
| US8329563B2 (en) | 2006-02-24 | 2012-12-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a gettering layer and manufacturing method therefor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5725255B2 (en) | 2012-02-23 | 2015-05-27 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| WO2013180244A1 (en) | 2012-05-31 | 2013-12-05 | 富士電機株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-09-27 JP JP6258766A patent/JP2607853B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0945530A1 (en) * | 1998-03-26 | 1999-09-29 | Naoetsu Electronics Company | A production method for a discrete structure substrate |
| US6093648A (en) * | 1998-03-26 | 2000-07-25 | Naoetsu Electronics Company | Production method for a discrete structure substrate |
| KR100293686B1 (en) * | 1998-03-26 | 2001-09-17 | 마츠자와 히데미 | Manufacturing Method of Discrete Substrate |
| US8329563B2 (en) | 2006-02-24 | 2012-12-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a gettering layer and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2607853B2 (en) | 1997-05-07 |
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