JPH088429A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH088429A JPH088429A JP6140564A JP14056494A JPH088429A JP H088429 A JPH088429 A JP H088429A JP 6140564 A JP6140564 A JP 6140564A JP 14056494 A JP14056494 A JP 14056494A JP H088429 A JPH088429 A JP H088429A
- Authority
- JP
- Japan
- Prior art keywords
- silicon carbide
- semiconductor
- layer
- trench
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 55
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000013078 crystal Substances 0.000 claims abstract description 28
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 97
- 238000009792 diffusion process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Carbon And Carbon Compounds (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置、例えば、
絶縁ゲート型電界効果トランジスタ、とりわけ大電力用
の縦型ＭＯＳＦＥＴに関する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, for example,
The present invention relates to an insulated gate field effect transistor, and more particularly to a vertical MOSFET for high power.
【０００２】[0002]
【従来の技術】近年、電力用トランジスタとしてシリコ
ン単結晶材料を使用して作製される縦型パワーＭＯＳＦ
ＥＴが多用されている。電力用トランジスタの損失を低
減するためにはオン抵抗の低減が必要であり、効果的に
オン抵抗低減が可能な素子構造として図９に示すトレン
チゲート型パワーＭＯＳＦＥＴ（例えば、特開昭５９−
８３７４号公報）が提案されている。トレンチゲート型
パワーＭＯＳＦＥＴはｎ型半導体基板２０上にｎ型エピ
タキシャル層２１が形成され、ｎ型エピタキシャル層２
１上にｐ型拡散層２２が形成され、さらに、ｐ型拡散層
２２の所定領域にｎ型拡散層２３が形成されている。
又、ｎ型拡散層２３とｐ型拡散層２２を貫通してｎ型エ
ピタキシャル層２１に達するトレンチ２４が形成され、
トレンチ２４内にはゲート酸化膜層２５を介してポリシ
リコン層２６が充填されている。ポリシリコン層２６の
上面には酸化膜層２７が形成され、酸化膜層２７上を含
むｎ型拡散層２３上にはアルミ層２８が形成されてい
る。又、ｎ型半導体基板２０の裏面にはドレイン電極層
２９が形成されている。そして、電流がトレンチ２４側
面のチャネル部を通じて縦方向（表面に対して垂直方
向）に流れる。2. Description of the Related Art In recent years, a vertical power MOSF manufactured by using a silicon single crystal material as a power transistor.
ET is heavily used. In order to reduce the loss of the power transistor, it is necessary to reduce the on-resistance, and as a device structure capable of effectively reducing the on-resistance, a trench gate type power MOSFET shown in FIG.
No. 8374) has been proposed. In the trench gate type power MOSFET, the n-type epitaxial layer 21 is formed on the n-type semiconductor substrate 20, and the n-type epitaxial layer 2 is formed.
1, a p-type diffusion layer 22 is formed, and an n-type diffusion layer 23 is further formed in a predetermined region of the p-type diffusion layer 22.
Further, a trench 24 penetrating the n-type diffusion layer 23 and the p-type diffusion layer 22 to reach the n-type epitaxial layer 21 is formed,
A polysilicon layer 26 is filled in the trench 24 via a gate oxide film layer 25. An oxide film layer 27 is formed on the upper surface of the polysilicon layer 26, and an aluminum layer 28 is formed on the n-type diffusion layer 23 including the oxide film layer 27. A drain electrode layer 29 is formed on the back surface of the n-type semiconductor substrate 20. Then, the current flows in the vertical direction (the direction perpendicular to the surface) through the channel portion on the side surface of the trench 24.
【０００３】一方、図９に示したトレンチゲート型パワ
ーＭＯＳＦＥＴを炭化珪素にて構成することが行われて
いる（例えば、特開平４−２３９７７８号公報）。この
場合、一般に面方位（０００１）の６Ｈ炭化珪素が用い
られる。ここで、「Ｈ」は六方晶系であることを示し、
そのＨの前の数値Ｎ（＝６）は原子積層がＮ層で１周期
である結晶構造を示す。On the other hand, the trench gate type power MOSFET shown in FIG. 9 is made of silicon carbide (for example, Japanese Patent Laid-Open No. 4-239778). In this case, 6H silicon carbide having a plane orientation (0001) is generally used. Here, “H” indicates that it is a hexagonal system,
The numerical value N (= 6) before the H indicates a crystal structure in which the atomic stack is an N layer and has one cycle.
【０００４】[0004]
【発明が解決しようとする課題】ところが、面方位（０
００１）の６Ｈ炭化珪素を用いたトレンチゲート型パワ
ーＭＯＳＦＥＴにおいては、チャネル抵抗を含めた素子
全体のオン抵抗が高くなってしまう。However, the plane orientation (0
In the trench gate type power MOSFET using 6H silicon carbide of (001), the ON resistance of the entire device including the channel resistance becomes high.
【０００５】そこで、この発明の目的は、オン抵抗を低
くすることができる半導体装置を提供することにある。Therefore, an object of the present invention is to provide a semiconductor device capable of reducing the on-resistance.
【０００６】[0006]
【課題を解決するための手段】トレンチゲート型ＭＯＳ
ＦＥＴにおいては、電流がトレンチ側面のチャネル部を
通じて縦方向に流れるので、チャネル抵抗を含めた素子
全体のオン抵抗は基板材料である炭化珪素の縦方向のキ
ャリア移動度に依存する。このため、トレンチゲート型
ＭＯＳＦＥＴのオン抵抗を低くするには縦方向のキャリ
ア移動度を大きくすればよい。Means for Solving the Problems Trench gate type MOS
In the FET, a current flows in the vertical direction through the channel portion on the side surface of the trench, so that the on-resistance of the entire device including the channel resistance depends on the carrier mobility in the vertical direction of silicon carbide that is the substrate material. Therefore, in order to reduce the on-resistance of the trench gate type MOSFET, the carrier mobility in the vertical direction may be increased.
【０００７】そこで、本発明者らは電子移動度の結晶方
位の依存性について調べた。それには、電子移動度に関
係する有効質量の結晶方位依存性を調べることから行っ
た。実験値や経験定数を参照しない第１原理計算（例え
ば、日本物理学会誌第４８巻第６号（１９９３年）Ｐ４
２５）により、２Ｈと４Ｈと６Ｈの炭化珪素の電子有効
質量を求めた。六方晶系炭化珪素の基本単位格子を図８
に示す三次元直交座標にて表し、その三次元直交座標の
各軸方向（ｘ，ｙ，ｚ方向）の電子有効質量ｍ xx * ，ｍ
yy * ，ｍzz * と、真空中での電子の有効質量ｍo の比で
ある電子有効質量比ｍ* ／ｍo の値は、表１に示す結果
となった。尚、図８において、ａ，ｂ，ｃは結晶軸を示
す。[0007] Therefore, the present inventors have found that the crystallinity of electron mobility
I investigated the dependence of position. For that,
From investigating the crystal orientation dependence of the effective mass
It was First-principles calculations that do not refer to experimental values or empirical constants (eg
For example, P4, Vol. 48, No. 6 (1993) of the Physical Society of Japan
25), the electron effectiveness of 2H, 4H, and 6H silicon carbide
The mass was calculated. The basic unit cell of hexagonal silicon carbide is shown in FIG.
The three-dimensional rectangular coordinates shown in
Electron effective mass m in each axial direction (x, y, z direction) xx *, M
yy *, Mzz *And the effective mass m of electrons in vacuumoIn the ratio of
Certain electron effective mass ratio m*/ MoIs the result shown in Table 1.
Became. In FIG. 8, a, b, and c indicate crystal axes.
You
【０００８】[0008]
【表１】 [Table 1]
【０００９】又、有効質量ｍ* と移動度μとの関係は、
衝突間隔τc を用いて、 μ＝ｑ・τc ／ｍ*・・・（１） と表すことができる（ただし、ｑは電気素量）。即ち、
有効質量ｍ* が小さいほど移動度μが大きいと言える。The relationship between the effective mass m * and the mobility μ is
Using the collision interval τ c , it can be expressed as μ = qτ c / m * ... (1) (where q is an elementary charge). That is,
It can be said that the smaller the effective mass m *, the larger the mobility μ.
【００１０】従来の面方位（０００１）の６Ｈ炭化珪素
を用いたトレンチゲート型ＭＯＳＦＥＴにおいては、チ
ャネルの電子移動方向が＜０００１＞軸方向（ｚ方向）
となり、電子有効質量比ｍ* ／ｍo は表１から「１．３
９」であり、大きな値となり電子移動度μが小さく、オ
ン抵抗は大きい。In the conventional trench gate type MOSFET using 6H silicon carbide having a plane orientation (0001), the electron movement direction of the channel is the <0001> axis direction (z direction).
Therefore, the electron effective mass ratio m * / m o can be calculated from Table 1 as “1.3
9 ”, which is a large value, the electron mobility μ is small, and the on-resistance is large.
【００１１】そこで、請求項１に記載の発明は、第１導
電型の低抵抗層と当該低抵抗層上にエピタキシャル成長
にて形成された第１導電型の高抵抗層の二層にて構成さ
れた炭化珪素よりなる半導体基板と、前記半導体基板の
表面上にエピタキシャル成長にて形成された炭化珪素よ
りなる第２導電型の半導体層と、前記半導体層内の所定
領域に前記半導体基板と隔てて形成された第１導電型の
半導体領域と、前記半導体領域と半導体層を貫通し前記
半導体基板に達する溝と、前記溝の内面に形成されたゲ
ート絶縁膜と、前記溝内における前記ゲート絶縁膜の内
側に形成されたゲート電極層と、前記半導体層表面およ
び半導体領域表面に形成されたソース電極層と、前記半
導体基板の裏面側に形成されたドレイン電極層とを備え
る半導体装置において、前記溝の側面に形成されるチャ
ネルのキャリア移動方向を、炭化珪素の結晶構造での三
次元直交座標の各軸方向におけるキャリア有効質量のう
ち最も小さい、あるいは２番目に小さい軸方向とほぼ一
致させた半導体装置をその要旨とする。Therefore, the invention according to claim 1 is composed of two layers of a first conductivity type low resistance layer and a first conductivity type high resistance layer formed on the low resistance layer by epitaxial growth. A semiconductor substrate made of silicon carbide, a second conductivity type semiconductor layer made of silicon carbide formed on the surface of the semiconductor substrate by epitaxial growth, and formed in a predetermined region in the semiconductor layer separately from the semiconductor substrate. A first conductive type semiconductor region, a groove penetrating the semiconductor region and the semiconductor layer to reach the semiconductor substrate, a gate insulating film formed on an inner surface of the groove, and a gate insulating film in the groove. A semiconductor device comprising a gate electrode layer formed inside, a source electrode layer formed on the surface of the semiconductor layer and a semiconductor region surface, and a drain electrode layer formed on the back surface side of the semiconductor substrate. Then, the carrier movement direction of the channel formed on the side surface of the groove is almost the same as the smallest or second smallest axis of the effective carrier mass in each axial direction of the three-dimensional orthogonal coordinates in the silicon carbide crystal structure. The matched semiconductor devices will be the gist.
【００１２】請求項２に記載の発明は、請求項１に記載
の発明における前記炭化珪素を六方晶系炭化珪素とした
半導体装置をその要旨とする。請求項３に記載の発明
は、請求項１に記載の発明における前記溝の側面に形成
されるチャネルのキャリア移動方向を、４Ｈ炭化珪素の
＜０００１＞軸方向とほぼ一致させた半導体装置をその
要旨とする。[0012] The gist of the invention described in claim 2 is a semiconductor device in which the silicon carbide in the invention described in claim 1 is hexagonal system silicon carbide. According to a third aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, the carrier movement direction of the channel formed on the side surface of the groove is substantially aligned with the <0001> axis direction of 4H silicon carbide. Use as a summary.
【００１３】請求項４に記載の発明は、請求項１に記載
の発明における前記溝の側面に形成されるチャネルのキ
ャリア移動方向を、２Ｈ炭化珪素の＜０００１＞軸方向
とほぼ一致させた半導体装置をその要旨とする。According to a fourth aspect of the present invention, in the semiconductor according to the first aspect of the present invention, the carrier movement direction of the channel formed on the side surface of the groove is made substantially coincident with the <0001> axis direction of 2H silicon carbide. The device is the gist.
【００１４】[0014]
【作用】請求項１，２に記載の発明は、電流が溝側面の
チャネル部を通じて縦方向に流れる。このとき、チャネ
ルのキャリア移動方向が、炭化珪素の結晶構造での三次
元直交座標の各軸方向におけるキャリア有効質量のうち
最も小さい、あるいは２番目に小さな軸方向とほぼ一致
しているので、キャリア移動方向においてキャリア有効
質量が小さくキャリア移動度が大きいため、オン抵抗の
低い特性が得られる。According to the present invention, the electric current flows in the vertical direction through the channel portion on the side surface of the groove. At this time, since the carrier moving direction of the channel is substantially the same as the smallest or second smallest axial effective mass of the carrier effective mass in each axial direction of the three-dimensional orthogonal coordinates in the silicon carbide crystal structure, Since the effective carrier mass is small and the carrier mobility is large in the moving direction, low on-resistance characteristics can be obtained.
【００１５】請求項３に記載の発明は、請求項１に記載
の発明の作用に加え、溝の側面に形成されるチャネルの
キャリア移動方向が４Ｈ炭化珪素の＜０００１＞軸方向
とほぼ一致しているので、キャリア移動方向においてキ
ャリア有効質量が小さくキャリア移動度が大きいため、
オン抵抗の低い特性が得られる。According to the invention described in claim 3, in addition to the action of the invention described in claim 1, the carrier movement direction of the channel formed on the side surface of the groove is substantially coincident with the <0001> axis direction of 4H silicon carbide. Therefore, since the effective carrier mass is small and the carrier mobility is large in the carrier moving direction,
A characteristic with low on-resistance can be obtained.
【００１６】請求項４に記載の発明は、請求項１に記載
の発明の作用に加え、溝の側面に形成されるチャネルの
キャリア移動方向が２Ｈ炭化珪素の＜０００１＞軸方向
とほぼ一致しているので、キャリア移動方向においてキ
ャリア有効質量が小さくキャリア移動度が大きいため、
オン抵抗の低い特性が得られる。According to the invention described in claim 4, in addition to the function of the invention described in claim 1, the carrier movement direction of the channel formed on the side surface of the groove is substantially coincident with the <0001> axis direction of 2H silicon carbide. Therefore, since the effective carrier mass is small and the carrier mobility is large in the carrier moving direction,
A characteristic with low on-resistance can be obtained.
【００１７】[0017]
（第１実施例）以下、この発明を具体化した第１実施例
を図面に従って説明する。(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.
【００１８】図１に本実施例のトレンチゲート型パワー
ＭＯＳＦＥＴ（縦型パワーＭＯＳＦＥＴ）の断面図を示
す。第１導電型の低抵抗層としてのｎ+ 型単結晶炭化珪
素（以下、ＳｉＣ）基板１は、４ＨＳｉＣ（０００１）
カーボン面を表面とし、かつ低抵抗でキャリア密度が５
×１０18ｃｍ-3程度である。このｎ+ 型単結晶ＳｉＣ基
板１上に、第１導電型の高抵抗層としてのｎ型エピタキ
シャル層２と、第２導電型の半導体層としてのｐ型エピ
タキシャル層３が順次積層されている。ｎ型エピタキシ
ャル層２は、キャリア密度が１×１０16ｃｍ-3程度で厚
さが１０μｍ程度となっている。又、ｐ型エピタキシャ
ル層３は、キャリア密度が１×１０17ｃｍ-3程度で厚さ
が２μｍ程度となっており、該ｐ型エピタキシャル層３
の表面４が素子表面となっている。FIG. 1 is a sectional view of a trench gate type power MOSFET (vertical power MOSFET) of this embodiment. The n + -type single crystal silicon carbide (hereinafter referred to as SiC) substrate 1 as the first conductivity type low resistance layer is formed of 4HSiC (0001).
The carbon surface is the surface, and the resistance is low and the carrier density is 5
It is about 10 18 cm -3 . On this n + type single crystal SiC substrate 1, an n type epitaxial layer 2 as a first conductivity type high resistance layer and a p type epitaxial layer 3 as a second conductivity type semiconductor layer are sequentially laminated. The n-type epitaxial layer 2 has a carrier density of about 1 × 10 16 cm −3 and a thickness of about 10 μm. The p-type epitaxial layer 3 has a carrier density of about 1 × 10 17 cm −3 and a thickness of about 2 μm.
The surface 4 of is the element surface.
【００１９】本実施例では、ｎ+ 型単結晶ＳｉＣ基板１
とｎ型エピタキシャル層２とから半導体基板１４が構成
されている。ｐ型エピタキシャル層３の表面４における
所定領域には、第１導電型の半導体領域としてのｎ+ ソ
ース領域５が形成され、ｎ+ ソース領域５はキャリア濃
度が１×１０19ｃｍ-3程度で接合深さが０．５μｍ程度
となっている。又、ｐ型エピタキシャル層３の表面４の
所定位置にトレンチ６が形成されている。このトレンチ
６は、ｎ+ ソース領域５とｐ型エピタキシャル層３を貫
通しｎ型エピタキシャル層２に達し、ｐ型エピタキシャ
ル層３の表面にほぼ垂直な側面６ａおよびｐ型エピタキ
シャル層３の表面に平行な底面６ｂを有する。つまり、
トレンチ６の側面６ａは４ＨＳｉＣの＜０００１＞軸方
向となっている。In this embodiment, an n + type single crystal SiC substrate 1 is used.
And the n-type epitaxial layer 2 form a semiconductor substrate 14. An n + source region 5 as a semiconductor region of the first conductivity type is formed in a predetermined region on the surface 4 of the p-type epitaxial layer 3, and the n + source region 5 has a carrier concentration of about 1 × 10 19 cm −3 . The junction depth is about 0.5 μm. A trench 6 is formed at a predetermined position on the surface 4 of the p-type epitaxial layer 3. The trench 6 penetrates the n + source region 5 and the p-type epitaxial layer 3 to reach the n-type epitaxial layer 2, and is parallel to the side surface 6 a substantially perpendicular to the surface of the p-type epitaxial layer 3 and the surface of the p-type epitaxial layer 3. A bottom surface 6b. That is,
The side surface 6a of the trench 6 is in the <0001> axis direction of 4HSiC.
【００２０】トレンチ６の内部には、ゲート絶縁膜とし
てのゲート熱酸化膜７を介してゲート電極層８が配置さ
れている。ここで、ゲート熱酸化膜７は１１００℃で５
時間程度の一度の熱酸化工程により形成され、トレンチ
６の側面６ａに位置する厚さが５０ｎｍ程度の薄いゲー
ト熱酸化膜７ａと、トレンチ６の底面６ｂに位置する厚
さが５００ｎｍ程度の厚いゲート熱酸化膜７ｂからな
る。さらに、ゲート熱酸化膜７はｎ+ ソース領域５上に
も形成され、この領域におけるゲート熱酸化膜７ｃも厚
さが５００ｎｍ程度に厚くなっている。Inside the trench 6, a gate electrode layer 8 is arranged via a gate thermal oxide film 7 as a gate insulating film. Here, the gate thermal oxide film 7 is 5 at 1100 ° C.
A thin gate thermal oxide film 7a having a thickness of about 50 nm located on the side surface 6a of the trench 6 and a thick gate having a thickness of about 500 nm located on the bottom surface 6b of the trench 6, which are formed by a single thermal oxidation process for about an hour. The thermal oxide film 7b is used. Further, the gate thermal oxide film 7 is also formed on the n + source region 5, and the gate thermal oxide film 7c in this region is also thickened to about 500 nm.
【００２１】又、ゲート電極層８は、ゲート熱酸化膜７
に接しリンをドープした第１のポリシリコン層８ａと第
２のポリシリコン層８ｂからなる。ゲート電極層８上に
は、厚さが１μｍ程度の層間絶縁膜９が配置されてい
る。さらに、層間絶縁膜９上を含めたｎ+ ソース領域５
の表面およびｐ型エピタキシャル層３の表面には、ソー
ス電極層１０が配置され、このソース電極層１０はｎ+
ソース領域５とｐ型エピタキシャル層３に共に接してい
る。ｎ+ 型単結晶ＳｉＣ基板１の裏面には、同基板１に
接するドレイン電極層１１が設けられている。The gate electrode layer 8 is the gate thermal oxide film 7
Of the first polysilicon layer 8a and the second polysilicon layer 8b which are in contact with each other and are doped with phosphorus. An interlayer insulating film 9 having a thickness of about 1 μm is arranged on the gate electrode layer 8. Furthermore, the n + source region 5 including the interlayer insulating film 9 is also included.
The surface and the p-type epitaxial layer 3 on the surface, is arranged a source electrode layer 10, the source electrode layer 10 is n +
Both the source region 5 and the p-type epitaxial layer 3 are in contact with each other. On the back surface of the n + type single crystal SiC substrate 1, a drain electrode layer 11 that is in contact with the substrate 1 is provided.
【００２２】ここで、トレンチ６の側面６ａのゲート熱
酸化膜７ａは薄いために閾電圧を低くでき（例えば２
Ｖ）、しかもトレンチ６の底面６ｂのゲート熱酸化膜７
ｂは厚いためにゲート・ドレイン間の耐圧を高く（例え
ば５００Ｖ以上）できる。Since the gate thermal oxide film 7a on the side surface 6a of the trench 6 is thin, the threshold voltage can be lowered (for example, 2
V) and the gate thermal oxide film 7 on the bottom surface 6b of the trench 6
Since b is thick, the breakdown voltage between the gate and the drain can be increased (for example, 500 V or more).
【００２３】このトレンチゲート型パワーＭＯＳＦＥＴ
の製造工程を、図２〜６を用いて、詳細に説明する。ま
ず、図２に示すように、表面の面方位が（０００１）カ
ーボン面である低抵抗のｎ+ 型単結晶４Ｈ−ＳｉＣ基板
１を用意する。そして、そのｎ+ 型単結晶４Ｈ−ＳｉＣ
基板１の表面に、キャリア密度が１×１０16ｃｍ-3程度
で厚さが１０μｍ程度のｎ型エピタキシャル層２と、キ
ャリア密度が１×１０17ｃｍ-3程度で厚さが２μｍ程度
のｐ型エピタキシャル層３を順次積層する。This trench gate type power MOSFET
The manufacturing process of will be described in detail with reference to FIGS. First, as shown in FIG. 2, a low-resistance n + -type single crystal 4H—SiC substrate 1 whose surface orientation is a (0001) carbon face is prepared. Then, the n + type single crystal 4H-SiC
On the surface of the substrate 1, an n-type epitaxial layer 2 having a carrier density of about 1 × 10 16 cm −3 and a thickness of about 10 μm, and a p-type layer having a carrier density of about 1 × 10 17 cm −3 and a thickness of about 2 μm. The type epitaxial layers 3 are sequentially laminated.
【００２４】このようにして、ｎ+ 型単結晶４Ｈ−Ｓｉ
Ｃ基板１とｎ型エピタキシャル層２とからなる半導体基
板１４を形成する。続いて、図３に示すように、ｐ型エ
ピタキシャル層３に対しマスク材１２を用いてイオン注
入法により表面のキャリア濃度が１×１０19ｃｍ-3程度
で接合深さが０．５μｍ程度のｎ+ ソース領域５を形成
する。In this way, the n + -type single crystal 4H--Si
A semiconductor substrate 14 including the C substrate 1 and the n-type epitaxial layer 2 is formed. Subsequently, as shown in FIG. 3, a mask material 12 is used for the p-type epitaxial layer 3 by an ion implantation method so that the carrier concentration on the surface is about 1 × 10 19 cm −3 and the junction depth is about 0.5 μm. The n + source region 5 is formed.
【００２５】次に、図４に示すように、マスク材１３を
用いて反応性イオンエッチング（ＲＩＥ）法により、ｎ
+ ソース領域５とｐ型エピタキシャル層３を貫通しｎ型
エピタキシャル層２に達するトレンチ６を形成する。こ
のトレンチ６は、ｐ型エピタキシャル層３の表面にほぼ
垂直な側面６ａおよびｐ型エピタキシャル層３の表面に
平行な底面６ｂを有する。Next, as shown in FIG. 4, n is formed by a reactive ion etching (RIE) method using a mask material 13.
A trench 6 penetrating the source region 5 and the p-type epitaxial layer 3 and reaching the n-type epitaxial layer 2 is formed. The trench 6 has a side surface 6 a substantially perpendicular to the surface of the p-type epitaxial layer 3 and a bottom surface 6 b parallel to the surface of the p-type epitaxial layer 3.
【００２６】続いて、図５に示すように、マスク材１３
を除去した後、熱酸化法によりゲート熱酸化膜７を１１
００℃で５時間程度の一度の熱酸化工程により形成す
る。この熱酸化によりトレンチ６の側面６ａに位置する
厚さが５０ｎｍ程度の薄いゲート熱酸化膜７ａと、トレ
ンチ６の底面６ｂに位置する厚さが５００ｎｍ程度の厚
いゲート熱酸化膜７ｂが形成される。さらに、ｎ+ ソー
ス領域５上には厚さが５００ｎｍ程度の厚いゲート熱酸
化膜７ｃが形成される。Subsequently, as shown in FIG. 5, the mask material 13
After removing the film, the gate thermal oxide film 7 is removed by thermal oxidation.
It is formed by a single thermal oxidation step at 00 ° C. for about 5 hours. By this thermal oxidation, a thin gate thermal oxide film 7a having a thickness of about 50 nm located on the side surface 6a of the trench 6 and a thick gate thermal oxide film 7b having a thickness of about 500 nm located on the bottom surface 6b of the trench 6 are formed. . Further, a thick gate thermal oxide film 7c having a thickness of about 500 nm is formed on n + source region 5.
【００２７】続いて、図６に示すように、トレンチ６内
を、第１及び第２ポリシリコン層８ａ，８ｂにより順次
埋め戻す。しかる後、図１に示すように、第１及び第２
ポリシリコン層８ａ，８ｂ上を含めたゲート熱酸化膜７
上に、ＣＶＤ法により層間絶縁層９を形成し、ソースコ
ンタクト予定位置のｎ+ ソース領域５とｐ型エピタキシ
ャル層３の表面上にあるゲート熱酸化膜７と層間絶縁層
９を除去する。その後、ｎ+ ソース領域５とｐ型エピタ
キシャル層３及び層間絶縁層９上にソース電極層１０を
形成するとともに、ｎ+ 型単結晶４Ｈ−ＳｉＣ基板１の
裏面にドレイン電極層１１を形成し、トレンチゲート型
ＳｉＣパワーＭＯＳＦＥＴを完成する。Subsequently, as shown in FIG. 6, the inside of the trench 6 is sequentially backfilled with the first and second polysilicon layers 8a and 8b. Then, as shown in FIG. 1, the first and second
Gate thermal oxide film 7 including on the polysilicon layers 8a and 8b
An interlayer insulating layer 9 is formed thereon by the CVD method, and the gate thermal oxide film 7 and the interlayer insulating layer 9 on the surface of the n + source region 5 at the source contact planned position and the p-type epitaxial layer 3 are removed. Then, the source electrode layer 10 is formed on the n + source region 5, the p-type epitaxial layer 3 and the interlayer insulating layer 9, and the drain electrode layer 11 is formed on the back surface of the n + -type single crystal 4H—SiC substrate 1. A trench gate type SiC power MOSFET is completed.
【００２８】このように製造されたトレンチゲート型Ｓ
ｉＣパワーＭＯＳＦＥＴにおいては次のように動作す
る。図７に示すように、ゲート電極層８に正の電圧を印
加することにより、電子電流はソース電極層１０からｎ
+ ソース領域５、トレンチ６の側面６ａでのｐ型エピタ
キシャル層３の端面に形成されるチャネル領域、ｎ型エ
ピタキシャル層２、ｎ+ 型単結晶４Ｈ−ＳｉＣ基板１、
ドレイン電極層１１の経路で流れる。このように、トレ
ンチ６の側面６ａでのｐ型エピタキシャル層３の端面が
チャネルになり、ソース・ドレイン間に電流が流れる。
このとき、チャネルは縦方向、即ち、４ＨＳｉＣにおけ
る＜０００１＞軸方向に形成される。その結果、チャネ
ル部では電子は＜０００１＞軸方向に流れ、又、ｎ型エ
ピタキシャル層２とｎ+ 型単結晶４Ｈ−ＳｉＣ基板１で
も電子は＜０００１＞軸方向に流れる。従って、トレン
チゲート型パワーＭＯＳＦＥＴのオン抵抗を考えた場
合、オン抵抗を占めるチャネル抵抗とエピタキシャル抵
抗は＜０００１＞軸方向の電子移動度に依存する。４Ｈ
ＳｉＣの＜０００１＞軸方向の電子移動度は表１の電子
有効質量比の値から６ＨＳｉＣの＜０００１＞軸方向の
電子移動度に比べ４倍（≒１．３９／０．３１）大き
く、表面の面方位が（０００１）である４ＨＳｉＣを用
いることにより６ＨＳｉＣを用いた場合に比べオン抵抗
は１／４以下になる。The trench gate type S manufactured as described above
The iC power MOSFET operates as follows. By applying a positive voltage to the gate electrode layer 8 as shown in FIG.
+ Source region 5, a channel region formed on the end face of the p-type epitaxial layer 3 on the side surface 6a of the trench 6, an n-type epitaxial layer 2, an n + -type single crystal 4H—SiC substrate 1,
It flows in the route of the drain electrode layer 11. In this way, the end surface of the p-type epitaxial layer 3 on the side surface 6a of the trench 6 serves as a channel, and a current flows between the source and drain.
At this time, the channel is formed in the vertical direction, that is, in the <0001> axis direction of 4HSiC. As a result, electrons flow in the <0001> axis direction in the channel portion, and also in the n-type epitaxial layer 2 and the n + -type single crystal 4H—SiC substrate 1, electrons flow in the <0001> axis direction. Therefore, when considering the on-resistance of the trench gate type power MOSFET, the channel resistance and the epitaxial resistance occupying the on-resistance depend on the electron mobility in the <0001> axis direction. 4H
The electron mobility in the <0001> axis direction of SiC is 4 times (≈1.39 / 0.31) larger than the electron mobility in the <0001> axis direction of 6HSiC from the value of the electron effective mass ratio in Table 1, By using 4HSiC whose plane orientation is (0001), the on-resistance becomes 1/4 or less as compared with the case of using 6HSiC.
【００２９】このように本実施例では、ｎ+ 型単結晶Ｓ
ｉＣ基板１（第１導電型の低抵抗層）と当該ＳｉＣ基板
１上にエピタキシャル成長にて形成されたｎ型エピタキ
シャル層２（第１導電型の高抵抗層）の二層にて構成さ
れた炭化珪素よりなる半導体基板１４と、半導体基板１
４の表面上にエピタキシャル成長にて形成された炭化珪
素よりなるｐ型エピタキシャル層３（第２導電型の半導
体層）と、ｐ型エピタキシャル層３内の所定領域に半導
体基板１４と隔てて形成されたｎ+ ソース領域５（第１
導電型の半導体領域）と、ｎ+ ソース領域５とｐ型エピ
タキシャル層３を貫通し半導体基板１４に達するトレン
チ６と、トレンチ６の内面に形成されたゲート熱酸化膜
７（ゲート絶縁膜）と、トレンチ６内におけるゲート熱
酸化膜７の内側に形成されたゲート電極層８と、ｐ型エ
ピタキシャル層３およびｎ+ ソース領域５表面に形成さ
れたソース電極層１０と、半導体基板１４の裏面側に形
成されたドレイン電極層１１とを備えるトレンチゲート
型パワーＭＯＳＦＥＴにおいて、トレンチ６の側面に形
成されるチャネルのキャリア移動方向を、４Ｈ炭化珪素
の＜０００１＞軸方向とした（半導体基板１４とｐ型エ
ピタキシャル層３とが接する面に垂直な方向を４Ｈ炭化
珪素の＜０００１＞軸方向とした）。即ち、トレンチ６
の側面に形成されるチャネルの電子移動方向を、表１に
おいて４Ｈ炭化珪素の結晶構造での三次元直交座標の各
軸方向における電子有効質量のうち２番目に小さな軸方
向とした。よって、電流がトレンチ側面のチャネル部を
通じて縦方向に流れるが、チャネルの電子移動方向が、
炭化珪素の結晶構造での三次元直交座標の各軸方向にお
ける電子有効質量のうち２番目に小さい軸方向としてい
るので、電子移動方向において電子有効質量が小さく電
子移動度が大きいため、オン抵抗の低い特性が得られ
る。 （第２実施例）次に、第２実施例を第１実施例との相違
点を中心に説明する。As described above, in this embodiment, the n + -type single crystal S
Carbonization consisting of two layers, iC substrate 1 (first conductivity type low resistance layer) and n type epitaxial layer 2 (first conductivity type high resistance layer) formed on the SiC substrate 1 by epitaxial growth Semiconductor substrate 14 made of silicon, and semiconductor substrate 1
P type epitaxial layer 3 (second conductivity type semiconductor layer) made of silicon carbide formed by epitaxial growth on the surface of No. 4 and a semiconductor substrate 14 formed in a predetermined region in p type epitaxial layer 3. n + source region 5 (first
A conductive type semiconductor region), a trench 6 penetrating the n + source region 5 and the p type epitaxial layer 3 to reach the semiconductor substrate 14, and a gate thermal oxide film 7 (gate insulating film) formed on the inner surface of the trench 6. , The gate electrode layer 8 formed inside the gate thermal oxide film 7 in the trench 6, the source electrode layer 10 formed on the surfaces of the p-type epitaxial layer 3 and the n + source region 5, and the back surface side of the semiconductor substrate 14. In the trench gate type power MOSFET including the drain electrode layer 11 formed on the side surface of the trench 6, the carrier moving direction of the channel formed on the side surface of the trench 6 is the <0001> axis direction of 4H silicon carbide (the semiconductor substrate 14 and p The direction perpendicular to the surface in contact with the type epitaxial layer 3 was defined as the <0001> axis direction of 4H silicon carbide). That is, the trench 6
In Table 1, the electron transfer direction of the channel formed on the side surface is defined as the second smallest axial direction of the electron effective mass in each axial direction of the three-dimensional rectangular coordinates in the 4H silicon carbide crystal structure. Therefore, current flows vertically through the channel portion on the side surface of the trench, but the electron transfer direction of the channel is
Since the second smallest axis of the electron effective mass in each axis direction of the three-dimensional Cartesian coordinate in the crystal structure of silicon carbide is used, the electron effective mass is small and the electron mobility is large in the electron moving direction. Low characteristics are obtained. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.
【００３０】本実施例では、図１におけるｎ+ 型単結晶
ＳｉＣ基板１とｎ型エピタキシャル層２およびｐ型エピ
タキシャル層３は、２Ｈ炭化珪素で、かつ、表面の面方
位が（０００１）カーボン面を用いている。In the present embodiment, the n + type single crystal SiC substrate 1, the n type epitaxial layer 2 and the p type epitaxial layer 3 in FIG. 1 are 2H silicon carbide and the surface plane orientation is (0001) carbon plane. Is used.
【００３１】よって、ｎ+ 型単結晶ＳｉＣ基板１とｎ型
エピタキシャル層２とが接する面に垂直な方向が２Ｈ炭
化珪素の＜０００１＞軸方向となっている。その結果、
トレンチ６の側面に形成されるチャネルの電子移動方向
が、表１において、２Ｈ炭化珪素の結晶構造での三次元
直交座標の各軸方向における電子有効質量のうち最も小
さい軸方向となっている。Therefore, the direction perpendicular to the surface where n + type single crystal SiC substrate 1 and n type epitaxial layer 2 are in contact is the <0001> axis direction of 2H silicon carbide. as a result,
In Table 1, the electron movement direction of the channel formed on the side surface of the trench 6 is the smallest axial direction of the electron effective masses in each axial direction of the three-dimensional orthogonal coordinates in the 2H silicon carbide crystal structure.
【００３２】このように本実施例では、トレンチ６の側
面に形成されるチャネルのキャリア移動方向を、２Ｈ炭
化珪素の結晶構造での三次元直交座標の各軸方向におけ
る電子有効質量のうち最も小さい軸方向とした。その結
果、電流が流れる方向において電子有効質量が小さく、
電子移動度が大きいため、オン抵抗の低い特性が得られ
る。As described above, in the present embodiment, the carrier moving direction of the channel formed on the side surface of the trench 6 is the smallest among the electron effective masses in the respective axial directions of the three-dimensional orthogonal coordinates in the 2H silicon carbide crystal structure. Axial direction. As a result, the electron effective mass is small in the direction of current flow,
Since the electron mobility is high, the characteristics of low on-resistance can be obtained.
【００３３】尚、この発明は上記各実施例に限定される
ものではなく、上記各実施例では半導体基板として表面
の面方位が（０００１）カーボン面を用いたが、表面の
面方位が（０００１）シリコン面でもよい。さらに、上
記各実施例ではｎチャネルＭＯＳＦＥＴに具体化した
が、導電型のｎとｐを入れ換えたｐチャネルＭＯＳＦＥ
Ｔとし、正孔をキャリアとして使用する場合に適用して
もよい。The present invention is not limited to the above-mentioned embodiments. In each of the above-mentioned embodiments, a carbon face having a surface orientation of (0001) was used as a semiconductor substrate, but the surface orientation of the surface was (0001). ) It may be a silicon surface. Further, in each of the above-mentioned embodiments, the n-channel MOSFET is embodied, but the p-channel MOSFE in which the conductivity types n and p are exchanged is used.
This may be applied when T is used and holes are used as carriers.
【００３４】又、トレンチ６の側面に形成されるチャネ
ルのキャリア移動方向と、炭化珪素の結晶構造での三次
元直交座標の各軸方向におけるキャリア有効質量のうち
最も小さい、あるいは２番目に小さな軸方向とは、完全
に一致させる必要はなく数度（７〜８度）ズレていても
よい。つまり、トレンチ６の側面６ａが、炭化珪素の結
晶構造での三次元直交座標の各軸方向におけるキャリア
有効質量のうち最も小さい、あるいは２番目に小さな軸
方向に対し数度（７〜８度）ズレていてもよい。The smallest or second smallest axis of carrier effective mass in the carrier movement direction of the channel formed on the side surface of trench 6 and in each axis direction of the three-dimensional orthogonal coordinates in the crystal structure of silicon carbide. The direction does not have to be completely the same, and may be shifted by several degrees (7 to 8 degrees). That is, the side surface 6a of the trench 6 has the smallest or the second smallest carrier effective mass in each axial direction of the three-dimensional orthogonal coordinates in the crystal structure of silicon carbide, or several degrees (7 to 8 degrees) with respect to the second smallest axial direction. It may be off.
【００３５】尚、上記各実施例では、溝として基板表面
に垂直な側面をもつトレンチの場合について示したが、
これに限られるものではなく、エッチング条件やエッチ
ング方法（例えば、ケミカルエッチング法やＬＯＣＯＳ
酸化法等）を変更して、溝側面が垂直でない傾斜した側
面をもつ溝に適用してもよい。In each of the above embodiments, the trench having the side surface perpendicular to the substrate surface is shown as the groove.
It is not limited to this, but the etching conditions and etching method (for example, chemical etching method and LOCOS
The oxidation method, etc.) may be modified to apply to a groove having inclined side surfaces where the groove side surfaces are not vertical.
【００３６】[0036]
【発明の効果】以上詳述したように、請求項１，２，
３，４に記載の発明によれば、オン抵抗を低くできる優
れた効果を発揮する。As described in detail above, claims 1, 2, and
According to the inventions of 3 and 4, an excellent effect that the on-resistance can be lowered is exhibited.
【図１】実施例の半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device of an example.
【図２】実施例の半導体装置の製造工程を説明するため
の断面図である。FIG. 2 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図３】実施例の半導体装置の製造工程を説明するため
の断面図である。FIG. 3 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the example.
【図４】実施例の半導体装置の製造工程を説明するため
の断面図である。FIG. 4 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the example.
【図５】実施例の半導体装置の製造工程を説明するため
の断面図である。FIG. 5 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the example.
【図６】実施例の半導体装置の製造工程を説明するため
の断面図である。FIG. 6 is a cross-sectional view for explaining the manufacturing process for the semiconductor device of the example.
【図７】実施例の半導体装置の作用を説明するための断
面図である。FIG. 7 is a cross-sectional view for explaining the operation of the semiconductor device of the example.
【図８】ＳｉＣでの基本単位格子を説明するための説明
図である。FIG. 8 is an explanatory diagram for explaining a basic unit cell of SiC.
【図９】従来の半導体装置の断面図である。FIG. 9 is a cross-sectional view of a conventional semiconductor device.
１…ｎ+ 型単結晶ＳｉＣ基板、２…ｎ型エピタキシャル
層、３…ｐ型エピタキシャル層、５…ｎ+ ソース領域、
６…トレンチ、７…ゲート熱酸化膜、８…ゲート電極
層、１０…ソース電極層、１１…ドレイン電極層、１４
…半導体基板1 ... n + type single crystal SiC substrate, 2 ... n type epitaxial layer, 3 ... p type epitaxial layer, 5 ... n + source region,
6 ... Trench, 7 ... Gate thermal oxide film, 8 ... Gate electrode layer, 10 ... Source electrode layer, 11 ... Drain electrode layer, 14
... Semiconductor substrate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 戸倉 規仁 愛知県刈谷市昭和町１丁目１番地 日本電 装 株式会社内 (72)発明者 加納 浩之 愛知県愛知郡長久手町大字長湫字横道41番 地の１株式会社豊田中央研究所内 (72)発明者 夫馬 弘雄 愛知県愛知郡長久手町大字長湫字横道41番 地の１株式会社豊田中央研究所内 (72)発明者 林 秀光 愛知県愛知郡長久手町大字長湫字横道41番 地の１株式会社豊田中央研究所内 (72)発明者 三輪 和利 愛知県愛知郡長久手町大字長湫字横道41番 地の１株式会社豊田中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Norihito Tokura, 1-chome, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd. (72) Hiroyuki Kano, 41, Nagakute, Nagakute-cho, Aichi-gun, Aichi prefecture No.1 Toyota Central Research Institute Co., Ltd. (72) Hiroo Ozuma Inoue Hiroo Azuma 41 Nagakute-cho, Aichi-gun, Aichi Pref. 1 Yokota Central Research Institute Ltd. (72) Inventor Hidemitsu Hayashi Nagakute-cho, Aichi-gun Aichi 1 in Toyota Central Research Institute Co., Ltd. at 41 Nagayoji Yokodori (72) Inventor Miwa Wari 1 in Toyota Central Research Institute, Ltd. at 41 Nagayoke Yokoido, Aichi-gun, Aichi-gun
Claims (4)
にエピタキシャル成長にて形成された第１導電型の高抵
抗層の二層にて構成された炭化珪素よりなる半導体基板
と、 前記半導体基板の表面上にエピタキシャル成長にて形成
された炭化珪素よりなる第２導電型の半導体層と、 前記半導体層内の所定領域に前記半導体基板と隔てて形
成された第１導電型の半導体領域と、 前記半導体領域と半導体層を貫通し前記半導体基板に達
する溝と、 前記溝の内面に形成されたゲート絶縁膜と、 前記溝内における前記ゲート絶縁膜の内側に形成された
ゲート電極層と、 前記半導体層表面および半導体領域表面に形成されたソ
ース電極層と、 前記半導体基板の裏面側に形成されたドレイン電極層と
を備える半導体装置において、 前記溝の側面に形成されるチャネルのキャリア移動方向
を、炭化珪素の結晶構造での三次元直交座標の各軸方向
におけるキャリア有効質量のうち最も小さい、あるいは
２番目に小さい軸方向とほぼ一致させたことを特徴とす
る半導体装置。1. A semiconductor substrate made of silicon carbide composed of two layers of a first conductivity type low resistance layer and a first conductivity type high resistance layer formed on the low resistance layer by epitaxial growth. A second conductivity type semiconductor layer made of silicon carbide formed on the surface of the semiconductor substrate by epitaxial growth, and a first conductivity type semiconductor region formed in a predetermined region in the semiconductor layer separated from the semiconductor substrate. A groove penetrating the semiconductor region and the semiconductor layer to reach the semiconductor substrate; a gate insulating film formed on the inner surface of the groove; and a gate electrode layer formed inside the gate insulating film in the groove. A semiconductor device including a source electrode layer formed on the surface of the semiconductor layer and a surface of the semiconductor region, and a drain electrode layer formed on a back surface side of the semiconductor substrate. The semiconductor carrier characterized in that the carrier moving direction of the channel is substantially the same as the smallest or second smallest axial effective carrier mass in each axial direction of the three-dimensional orthogonal coordinates in the silicon carbide crystal structure. apparatus.
ことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the silicon carbide is hexagonal silicon carbide.
ャリア移動方向を、４Ｈ炭化珪素の＜０００１＞軸方向
とほぼ一致させたことを特徴とする請求項１に記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the carrier movement direction of the channel formed on the side surface of the groove is made substantially coincident with the <0001> axis direction of 4H silicon carbide.
ャリア移動方向を、２Ｈ炭化珪素の＜０００１＞軸方向
とほぼ一致させたことを特徴とする請求項１に記載の半
導体装置。4. The semiconductor device according to claim 1, wherein a carrier moving direction of a channel formed on a side surface of the groove is made substantially coincident with a <0001> axis direction of 2H silicon carbide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6140564A JPH088429A (en) | 1994-06-22 | 1994-06-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6140564A JPH088429A (en) | 1994-06-22 | 1994-06-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH088429A true JPH088429A (en) | 1996-01-12 |
Family
ID=15271622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6140564A Pending JPH088429A (en) | 1994-06-22 | 1994-06-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088429A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977564A (en) * | 1996-10-16 | 1999-11-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2000509559A (en) * | 1996-06-06 | 2000-07-25 | クリー リサーチ インコーポレイテッド | Silicon carbide metal insulator semiconductor field effect transistor |
| JP2000312003A (en) * | 1999-02-23 | 2000-11-07 | Matsushita Electric Ind Co Ltd | Insulated gate type semiconductor element and manufacture thereof |
| JP2007207935A (en) * | 2006-01-31 | 2007-08-16 | Fuji Electric Holdings Co Ltd | Process for fabricating silicon carbide semiconductor element |
| JP2008147232A (en) * | 2006-12-06 | 2008-06-26 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| JP2012099834A (en) * | 2011-12-19 | 2012-05-24 | Fuji Electric Co Ltd | Method of manufacturing mos gate type silicon carbide semiconductor device |
| WO2012098861A1 (en) * | 2011-01-17 | 2012-07-26 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
-
1994
- 1994-06-22 JP JP6140564A patent/JPH088429A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000509559A (en) * | 1996-06-06 | 2000-07-25 | クリー リサーチ インコーポレイテッド | Silicon carbide metal insulator semiconductor field effect transistor |
| US5977564A (en) * | 1996-10-16 | 1999-11-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US6246077B1 (en) | 1996-10-16 | 2001-06-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2000312003A (en) * | 1999-02-23 | 2000-11-07 | Matsushita Electric Ind Co Ltd | Insulated gate type semiconductor element and manufacture thereof |
| JP2007207935A (en) * | 2006-01-31 | 2007-08-16 | Fuji Electric Holdings Co Ltd | Process for fabricating silicon carbide semiconductor element |
| JP2008147232A (en) * | 2006-12-06 | 2008-06-26 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| WO2012098861A1 (en) * | 2011-01-17 | 2012-07-26 | パナソニック株式会社 | Semiconductor device and method for manufacturing same |
| JP2012099834A (en) * | 2011-12-19 | 2012-05-24 | Fuji Electric Co Ltd | Method of manufacturing mos gate type silicon carbide semiconductor device |
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