JPH0883929A - Semiconductor light emitting element and manufacture thereof - Google Patents
Semiconductor light emitting element and manufacture thereofInfo
- Publication number
- JPH0883929A JPH0883929A JP22020694A JP22020694A JPH0883929A JP H0883929 A JPH0883929 A JP H0883929A JP 22020694 A JP22020694 A JP 22020694A JP 22020694 A JP22020694 A JP 22020694A JP H0883929 A JPH0883929 A JP H0883929A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- layer
- insulating substrate
- type
- semiconductor light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本願発明は、たとえば青色発光Ｌ
ＥＤなど、絶縁基板を用いて構成されるタイプの半導体
発光素子、およびその半導体発光素子の製造方法に関す
る。BACKGROUND OF THE INVENTION The present invention relates to, for example, blue light emission L.
The present invention relates to a semiconductor light emitting element of a type configured using an insulating substrate such as an ED, and a method for manufacturing the semiconductor light emitting element.
【０００２】[0002]
【従来の技術】赤色や緑色の発光ＬＥＤは、一般には、
ＧａＰ基板やＧａＡｓＰ基板などの導電性基板を用いて
製造されている。したがって、このような半導体発光素
子については、たとえば図４に示すように、一対の電極
１０ａ，１０ｂを、基板２ｅの表面に形成された積層部
６ｅのうち最表層の半導体層５ｅと基板２ｅの裏面とに
各々設けることができる。また、このような半導体発光
素子では、たとえば図５に示すように、リードフレーム
３０へのボンディングを行う場合に、下側の電極１０ｂ
をそのままリード３０ａへ導通接着させることができ、
ワイヤボンディングは上側の電極１０ａを１本のワイヤ
３２ｂによってリード３０ｂへ接続させるだけでよい。2. Description of the Related Art Generally, red and green light emitting LEDs are
It is manufactured using a conductive substrate such as a GaP substrate or a GaAsP substrate. Therefore, in such a semiconductor light emitting device, for example, as shown in FIG. 4, a pair of electrodes 10a and 10b are provided between the outermost semiconductor layer 5e and the substrate 2e of the laminated portion 6e formed on the surface of the substrate 2e. They can be provided on the back surface and the back surface, respectively. Further, in such a semiconductor light emitting device, for example, as shown in FIG. 5, when bonding to the lead frame 30, the lower electrode 10b is formed.
Can be directly adhered to the lead 30a,
The wire bonding need only connect the upper electrode 10a to the lead 30b by one wire 32b.
【０００３】これに対し、青色発光ＬＥＤについては、
絶縁基板としてのサファイア基板が採用されているのが
実情である。このような発光ＬＥＤについては、ただ単
に絶縁基板の裏面に電極を形成しても、この電極は基板
によって半導体層と絶縁されているから意味をなさな
い。On the other hand, for blue light emitting LEDs,
In reality, a sapphire substrate is used as an insulating substrate. With respect to such a light emitting LED, even if an electrode is simply formed on the back surface of the insulating substrate, it is meaningless because the electrode is insulated from the semiconductor layer by the substrate.
【０００４】そこで、従来では、絶縁基板を用いた青色
発光ＬＥＤなどの半導体発光素子を製造する場合には、
たとえば図６に示すように、絶縁基板２ｆの表面に形成
された積層部６ｆのうち、発光層４ｆおよびｐ型半導体
層５ｆの一部の領域Ｂをエッチングによって除去してい
た。そして、このエッチングされた領域Ｂに露出したｎ
型半導体層３ｆの表面に一方の電極１０ｂを設けてい
た。なお、他方の電極１０ａは、ｐ型半導体層５ｆの表
面に設けていた。Therefore, conventionally, when a semiconductor light emitting device such as a blue light emitting LED using an insulating substrate is manufactured,
For example, as shown in FIG. 6, in the laminated portion 6f formed on the surface of the insulating substrate 2f, a part of the region B of the light emitting layer 4f and the p-type semiconductor layer 5f is removed by etching. Then, n exposed in the etched region B
One electrode 10b was provided on the surface of the type semiconductor layer 3f. The other electrode 10a was provided on the surface of the p-type semiconductor layer 5f.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の図６に示した半導体発光素子では、積層部６ｆの表
面側（上面側）に２つの電極１０ａ，１０ｂが形成され
ているために、リードフレームへのボンディングを行う
場合には、たとえば図７に示すように、２本のワイヤ３
２ａ，３２ｂを用いて各リード３０ａ，３０ｂへのワイ
ヤボンディング作業を行う必要がある。したがって、そ
のボンディング作業の工程数が図５で示した場合に比較
すると増加し、発光ランプを製作する際の製造効率が悪
くなるという難点があった。However, in the conventional semiconductor light emitting device shown in FIG. 6 described above, since the two electrodes 10a and 10b are formed on the surface side (upper surface side) of the laminated portion 6f, the leads are not formed. When bonding to the frame, for example, as shown in FIG.
It is necessary to perform wire bonding work on the leads 30a and 30b using the wires 2a and 32b. Therefore, the number of steps of the bonding work is increased as compared with the case shown in FIG. 5, and there is a drawback that the manufacturing efficiency at the time of manufacturing the light emitting lamp is deteriorated.
【０００６】また、上記従来の半導体発光素子では、リ
ードフレーム３０へのワイヤボンディング工程の内容
が、図５で示した工程とは相違するために、たとえば図
４で示したタイプの半導体発光素子を用いて発光ランプ
を製造するための既存の生産ラインをそのまま利用して
発光ランプの生産を行うことができない。したがって、
従来では、絶縁基板を用いた半導体発光素子を部品とす
る発光ランプを製造する場合には、その半導体発光素子
専用の生産ラインを別途用意する必要が生じ、設備費用
が多大となる難点もあった。In the conventional semiconductor light emitting device described above, the wire bonding process to the lead frame 30 is different from the process shown in FIG. 5, so that the semiconductor light emitting device of the type shown in FIG. 4 is used. The existing production line for manufacturing a light-emitting lamp using the same cannot be used as it is to produce a light-emitting lamp. Therefore,
Conventionally, when manufacturing a light-emitting lamp including a semiconductor light-emitting element using an insulating substrate as a component, it is necessary to separately prepare a production line dedicated to the semiconductor light-emitting element, which causes a problem that the facility cost becomes large. .
【０００７】さらに、上記従来の半導体発光素子では、
一方の電極１０ｂを形成することを目的として積層部６
ｆの一部の領域Ｂをかなり大きな面積で除去する必要が
あるために、この領域分だけ発光層４ｆの面積が小さく
なる。したがって、半導体発光素子の発光強度がそれだ
け低下し、高い発光輝度が得られなくなるという難点も
生じていた。Further, in the above conventional semiconductor light emitting device,
The laminated portion 6 is formed for the purpose of forming one electrode 10b.
Since it is necessary to remove a part of the region B of f with a considerably large area, the area of the light emitting layer 4f is reduced by this region. Therefore, the light emission intensity of the semiconductor light emitting element is reduced to that extent, and it is difficult to obtain high light emission luminance.
【０００８】本願発明は、このような事情のもとで考え
出されたものであって、絶縁基板を用いた半導体発光素
子であっても、半導体発光素子の上下両面に電極が形成
されているタイプと同様な製造ラインを用いて少ない工
程数でのボンディング作業が行えるようにし、しかも電
極の形成箇所を確保するために発光層の面積を減少させ
るような必要もなくし、発光輝度を高めることができる
ようにすることをその課題としている。The present invention was conceived under such circumstances, and even in a semiconductor light emitting device using an insulating substrate, electrodes are formed on both upper and lower surfaces of the semiconductor light emitting device. It is possible to perform bonding work in a small number of steps using a manufacturing line similar to that of the type, and it is not necessary to reduce the area of the light emitting layer in order to secure the place where the electrode is formed. The task is to be able to do so.
【０００９】[0009]
【課題を解決するための手段】上記の課題を解決するた
め、本願発明では、次の技術的手段を講じている。In order to solve the above problems, the present invention takes the following technical means.
【００１０】すなわち、本願の請求項１に記載の発明
は、絶縁基板の表面上に、ｎ型半導体層、発光層、およ
びｐ型半導体層から構成される積層部が形成されている
半導体発光素子において、上記絶縁基板には、上記積層
部のうち最下層のｎ型またはｐ型の半導体層の形成位置
から絶縁基板の裏面にわたって形成されたスルーホール
内に導電性物質が充填されたコンタクトホールが形成さ
れ、かつ、上記絶縁基板の裏面には、上記コンタクトホ
ールを介して上記最下層の半導体層に導通する導電性膜
が形成されていることを特徴としている。That is, the invention according to claim 1 of the present application is a semiconductor light emitting device in which a laminated portion including an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer is formed on the surface of an insulating substrate. In the insulating substrate, a contact hole in which a conductive substance is filled in a through hole formed from the formation position of the lowermost n-type or p-type semiconductor layer in the laminated portion to the back surface of the insulating substrate is provided. A conductive film is formed on the back surface of the insulating substrate and is electrically connected to the lowermost semiconductor layer through the contact hole.
【００１１】また、本願の請求項２に記載の発明は、上
記請求項１に記載の半導体発光素子を製造するための方
法であって、絶縁基板の表面上に、ｎ型半導体層、発光
層、およびｐ型半導体層から構成される積層部を形成し
た後に、上記絶縁基板には、上記積層部のうち最下層の
ｎ型またはｐ型の半導体層の形成位置から絶縁基板の裏
面にわたってスルーホールを形成し、その後上記絶縁基
板の裏面側へ導電性物質を堆積付着させることにより、
上記スルーホール内へ導電性物質を充填させてコンタク
トホールを形成するとともに、上記絶縁基板の裏面に導
電性膜を形成することを特徴としている。The invention according to claim 2 of the present application is a method for manufacturing the semiconductor light emitting device according to claim 1, wherein an n-type semiconductor layer and a light emitting layer are provided on the surface of the insulating substrate. , And a p-type semiconductor layer are formed, a through hole is formed in the insulating substrate from the formation position of the lowermost n-type or p-type semiconductor layer in the laminate to the back surface of the insulating substrate. And then depositing and depositing a conductive substance on the back surface side of the insulating substrate,
It is characterized in that a conductive material is filled in the through hole to form a contact hole, and a conductive film is formed on the back surface of the insulating substrate.
【００１２】[0012]
【発明の作用および効果】上記請求項１に記載した発明
においては、絶縁基板の表面上に形成された積層部のう
ち、最下層のｎ型またはｐ型の半導体層がコンタクトホ
ールを介して絶縁基板の裏面に形成された導電性膜と導
通しているために、この導電性膜を電極として機能させ
ることができ、あるいはこの導電性膜に電極を形成すれ
ばよいこととなる。また、積層部の最表層に対する電極
形成は従前通り行うことができる。したがって、半導体
発光素子の上下両面に電極を形成したのと同様な構成に
できることとなる。According to the invention described in claim 1, in the laminated portion formed on the surface of the insulating substrate, the lowermost n-type or p-type semiconductor layer is insulated through the contact hole. Since it is electrically connected to the conductive film formed on the back surface of the substrate, this conductive film can function as an electrode, or an electrode may be formed on this conductive film. Further, the electrode formation on the outermost layer of the laminated portion can be performed as before. Therefore, a structure similar to that in which electrodes are formed on the upper and lower surfaces of the semiconductor light emitting device can be obtained.
【００１３】その結果、リードフレームなどへのボンデ
ィングを行う場合には、絶縁基板の裏面側の導電性膜を
リードに対して導電接着させることにより、この導電性
膜にコンタクトホールを介して導通する一方の半導体層
への電気配線接続が行えることとなって、ワイヤボンデ
ィングなどのボンディング作業工程の簡素化が図れ、発
光ランプを製造する際の製造効率を向上させることがで
きるという格別な効果が得られる。As a result, when bonding to a lead frame or the like, the conductive film on the back surface side of the insulating substrate is conductively adhered to the leads so that the conductive film is electrically connected through the contact holes. Since electrical wiring can be connected to one of the semiconductor layers, the bonding work process such as wire bonding can be simplified, and the special effect that the manufacturing efficiency at the time of manufacturing the light emitting lamp can be improved is obtained. To be
【００１４】しかも、このようなボンディング作業は、
上下両面に電極を配置した構造の半導体発光素子につい
てボンディングを行う場合の作業工程と同様であるため
に、発光ランプを製造する場合には、上下両面に電極を
形成した半導体発光素子についての生産ラインをそのま
ま利用することが可能となる。したがって、従来とは異
なり、絶縁基板を用いた半導体発光素子専用の生産ライ
ンを別途準備するような必要もなくなり、設備コストを
大幅に低減することができるという効果も得られる。Moreover, such a bonding operation is
Since this is the same as the work process for bonding a semiconductor light emitting device having a structure in which electrodes are arranged on the upper and lower surfaces, when manufacturing a light emitting lamp, a production line for semiconductor light emitting devices with electrodes formed on the upper and lower surfaces. Can be used as is. Therefore, unlike the prior art, there is no need to separately prepare a production line dedicated to the semiconductor light emitting element using an insulating substrate, and there is an effect that the facility cost can be significantly reduced.
【００１５】また、請求項１に記載した発明では、電極
形成用のスペースを確保する必要性から発光層の一部を
エッチングし、除去する必要はない。したがって、従来
に比較して、発光層の面積を大きくとることができるこ
とにより、発光層の発光強度を強めることができ、高い
発光輝度が得られるという優れた効果も得られる。Further, in the invention described in claim 1, it is not necessary to etch and remove a part of the light emitting layer because it is necessary to secure a space for forming an electrode. Therefore, as compared with the conventional case, the area of the light emitting layer can be made large, so that the light emission intensity of the light emitting layer can be increased, and an excellent effect of obtaining high light emission luminance can also be obtained.
【００１６】請求項２に記載の発明においては、絶縁基
板の表面上に所定の積層部を形成した後に、その積層部
のうち最下層のｎ型またはｐ型の半導体層の形成位置か
ら絶縁基板の裏面にわたってスルーホールを形成し、そ
の後上記絶縁基板の裏面側へ導電性物質を堆積付着させ
るために、コンタクトホールの形成と絶縁基板の裏面へ
の導電性膜の形成とを同時に行うことができる。すなわ
ち、一部の導電性物質が絶縁基板の裏面に形成されたス
ルーホール内に順次充填されてゆくことによりコンタク
トホールが形成されると同時に、他の導電性物質は絶縁
基板の裏面に順次堆積付着し、上記コンタクトホールと
導通した導電性膜が形成されることとなる。したがっ
て、請求項１に記載の半導体発光素子を、簡易な製造工
程によって適切に製造することができる。According to a second aspect of the present invention, after forming a predetermined laminated portion on the surface of the insulating substrate, the insulating substrate is formed from the formation position of the lowermost n-type or p-type semiconductor layer in the laminated portion. A through hole can be formed over the back surface of the insulating substrate, and then a contact hole can be formed and a conductive film can be formed on the back surface of the insulating substrate at the same time in order to deposit and attach a conductive material to the back surface of the insulating substrate. . That is, a part of the conductive material is sequentially filled into the through holes formed on the back surface of the insulating substrate to form contact holes, and at the same time, other conductive materials are sequentially deposited on the back surface of the insulating substrate. A conductive film that adheres and is electrically connected to the contact hole is formed. Therefore, the semiconductor light emitting device according to claim 1 can be appropriately manufactured by a simple manufacturing process.
【００１７】[0017]
【実施例の説明】以下、本願発明の好ましい実施例を、
図面を参照しつつ具体的に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below.
A specific description will be given with reference to the drawings.
【００１８】図１は、本願発明に係る半導体発光素子の
一例を示す断面図である。FIG. 1 is a sectional view showing an example of a semiconductor light emitting device according to the present invention.
【００１９】図１に示す半導体発光素子１は、青色発光
ＬＥＤとして構成されたものであり、絶縁基板としての
サファイア基板２の表面に、ｎ型半導体層３、発光層
４、およびｐ型半導体層５からなる積層部６を形成した
ものである。また、サファイア基板２の裏面には導電性
膜８が形成されているとともに、このサファイア基板２
には、その裏面から上記積層部６の最下層のｎ型半導体
層３の形成位置にわたってコンタクトホール７が形成さ
れている。A semiconductor light emitting element 1 shown in FIG. 1 is configured as a blue light emitting LED, and an n-type semiconductor layer 3, a light emitting layer 4, and a p-type semiconductor layer are formed on the surface of a sapphire substrate 2 as an insulating substrate. The laminated portion 6 composed of 5 is formed. A conductive film 8 is formed on the back surface of the sapphire substrate 2, and the sapphire substrate 2
Has a contact hole 7 formed from the back surface thereof to the position where the lowermost n-type semiconductor layer 3 of the laminated portion 6 is formed.
【００２０】上記ｎ型半導体層３は、サファイア基板２
の表面上に成長させた窒化ガリウムなどのバッファ層９
上に形成されており、ｎ型ＧａＮ層３１、およびｎ型Ａ
ｌＧａＮ層３２（Ａｌ0.2 Ｇａ0.8 Ｎ）によって形成さ
れている。上記発光層４は、たとえばＩｎＧａＮ層（Ｉ
ｎ0.15Ｇａ0.85Ｎ）によって形成されている。また、ｐ
型半導体層５は、ｐ型ＡｌＧａＮ層５１（Ａｌ0.2 Ｇａ
0.8 Ｎ）、およびｐ型ＧａＮ層５２によって形成されて
いる。このｐ型ＧａＮ層５２の表面には、たとえばＴ
ｉ，Ａｕ，Ｎｉなどの電極１０が形成されている。The n-type semiconductor layer 3 is a sapphire substrate 2
Buffer layer 9 such as gallium nitride grown on the surface of
Formed on the n-type GaN layer 31 and the n-type A
The lGaN layer 32 (Al 0.2 Ga 0.8 N) is used. The light emitting layer 4 is, for example, an InGaN layer (I
n 0.15 Ga 0.85 N). Also, p
The type semiconductor layer 5 is a p-type AlGaN layer 51 (Al 0.2 Ga).
0.8 N), and the p-type GaN layer 52. On the surface of this p-type GaN layer 52, for example, T
An electrode 10 made of i, Au, Ni or the like is formed.
【００２１】上記コンタクトホール７は、サファイア基
板２の裏面からこのサファイア基板２およびバッファ層
９を貫通し、積層部６の最下層のｎ型ＧａＮ層３１に到
達するように形成されたスルーホール７０内に、導電性
物質ｍが充填されて構成されている。この導電性物質ｍ
の具体例としては、たとえば燐（Ｐ）の拡散処理がなさ
れることにより導電性が具備されたポリシリコンが適用
される。The contact hole 7 penetrates the sapphire substrate 2 and the buffer layer 9 from the back surface of the sapphire substrate 2 and reaches the lowermost n-type GaN layer 31 of the laminated portion 6, which is a through hole 70. The inside is filled with a conductive substance m. This conductive material m
As a specific example of the above, for example, polysilicon having conductivity by applying a diffusion process of phosphorus (P) is applied.
【００２２】上記導電性膜８は、サファイア基板２の裏
面の全面に形成されているが、この導電性膜８は、上記
コンタクトホール７を形成する導電性物質ｍと同一物質
ｍによって形成することができ、その具体例としては既
述した燐が拡散されたポリシリコンが適用される。この
導電性膜８は、上記コンタクトホール７と導通するよう
に設けられており、このコンタクトホール７を介して上
記ｎ型ＧａＮ層３１に導通している。The conductive film 8 is formed on the entire back surface of the sapphire substrate 2. The conductive film 8 should be formed of the same conductive material m as the contact hole 7. As a specific example, the above-mentioned phosphorus-diffused polysilicon is applied. The conductive film 8 is provided so as to be electrically connected to the contact hole 7, and is electrically connected to the n-type GaN layer 31 through the contact hole 7.
【００２３】次に、上記構成の半導体発光素子１の製造
方法の一例について説明する。Next, an example of a method of manufacturing the semiconductor light emitting device 1 having the above structure will be described.
【００２４】まず、図２（ａ）に示すように、サファイ
ア基板２の表面上に、所定のバッファ層９、ｎ型半導体
層３、発光層４、およびｐ型半導体層５を形成するが、
これは従来既知の有機金属化学気相成長法（ＭＯＣＶＤ
法）によって、上述した各成分の単結晶を順次成長させ
ることにより行うことができる。なお、ｐ型半導体層５
の最表層には電極１０を形成するが、この電極１０の形
成時期は特に限定されず、積層部６を形成した後であれ
ば、いつでもよい。First, as shown in FIG. 2A, a predetermined buffer layer 9, an n-type semiconductor layer 3, a light emitting layer 4, and a p-type semiconductor layer 5 are formed on the surface of the sapphire substrate 2.
This is a known metal organic chemical vapor deposition (MOCVD) method.
Method), a single crystal of each component described above is sequentially grown. The p-type semiconductor layer 5
Although the electrode 10 is formed on the outermost layer, the formation timing of the electrode 10 is not particularly limited, and may be any time after the laminated portion 6 is formed.
【００２５】次いで、上記作業工程が終了した後には、
図２（ｂ）に示すように、サファイア基板２の裏面側か
らｎ型ＧａＮ層３１の下面側の位置までスルーホール７
０を形成する。このスルーホール７０は、エッチング処
理によって形成することが可能であり、その具体的な内
径寸法などは問わない。また、形成個数も問わず、たと
えばこのスルーホール７０を複数箇所設けてもよい。さ
らに、このスルーホール７０がｎ型ＧａＮ層３１の上側
に位置するｎ型ＡｌＧａＮ層３２に到達しない限りにお
いて、ｎ型ＧａＮ層３１が多少浸食される状態に形成さ
れていても構わない。Then, after the above work steps are completed,
As shown in FIG. 2B, the through hole 7 extends from the rear surface side of the sapphire substrate 2 to the position of the lower surface side of the n-type GaN layer 31.
Form 0. The through hole 70 can be formed by an etching process, and its specific inner diameter dimension does not matter. Further, regardless of the number of formed holes, for example, the through holes 70 may be provided at a plurality of positions. Further, as long as the through hole 70 does not reach the n-type AlGaN layer 32 located above the n-type GaN layer 31, the n-type GaN layer 31 may be formed in a state of being slightly eroded.
【００２６】上記のようにしてスルーホール７０を形成
した後には、その後図２（ｃ）に示すように、多結晶体
としてのポリシリコンを、たとえば低圧ＣＶＤ法によっ
てサファイア基板２の裏面側へ順次堆積付着させる。こ
の場合、ポリシリコンに予め燐（Ｐ）を拡散処理させて
いてもよいし、ポリシリコンと同時に燐（Ｐ）をＣＶＤ
法によって所望の比率で混合堆積させるようにしてもよ
い。これにより、図１で示したように、上記スルーホー
ル７０内にはポリシリコンの結晶体を充填させることが
でき、コンタクトホール７を形成する構成することがで
きる。また、これと同時に、サファイア基板２の裏面に
は、ポリシリコンを成膜させることができ、コンタクト
ホール７に導通した導電性膜８を形成することができ
る。したがって、図１で示した半導体発光素子１を適切
に製造することができる。After forming the through hole 70 as described above, as shown in FIG. 2C, polysilicon as a polycrystalline material is sequentially applied to the back surface side of the sapphire substrate 2 by, for example, the low pressure CVD method. Deposit and attach. In this case, the polysilicon may be preliminarily diffused with phosphorus (P), or phosphorus (P) may be CVD-treated simultaneously with the polysilicon.
You may make it carry out mixed deposition at a desired ratio by the method. As a result, as shown in FIG. 1, the through hole 70 can be filled with the polysilicon crystal, and the contact hole 7 can be formed. At the same time, polysilicon can be deposited on the back surface of the sapphire substrate 2, and the conductive film 8 that is electrically connected to the contact hole 7 can be formed. Therefore, the semiconductor light emitting device 1 shown in FIG. 1 can be appropriately manufactured.
【００２７】なお、上記一連の製造作業は、ウエハに対
して行われ、上記のようにして半導体発光素子１を製造
した後には、ダイシングにより、たとえば平面矢視にお
いて一辺が０．５ｍｍ程度の正方形状のチップに分割さ
れる。The above-described series of manufacturing operations are performed on the wafer, and after the semiconductor light emitting device 1 is manufactured as described above, it is subjected to dicing, for example, a square having a side of about 0.5 mm in a plan arrow view. It is divided into chips.
【００２８】以上のようにして製造された半導体発光素
子１は、積層部６の最表層に電極１０が形成されている
他、サファイア基板２の裏面側には、積層部６の最下層
のｎ型ＧａＮ層３１に導通した導電性膜８が形成されて
いる。したがって、この半導体発光素子１を用いて発光
ランプを製造する場合には、図４および図５において説
明したのと同様な簡易な作業工程によってリードフレー
ムへのボンディングを行うことができる。すなわち、サ
ファイア基板２の裏面の導電性膜８をリードフレームに
対して導電性接着剤を用いて接着すれば、もはやｎ型Ｇ
ａＮ層３１に対してのワイヤボンディングを行う必要は
ない。したがって、金線を用いたワイヤボンディング
は、電極１０に対してのみ行えばよく、ボンディング作
業が容易化される。In the semiconductor light emitting device 1 manufactured as described above, the electrode 10 is formed on the outermost layer of the laminated portion 6, and on the back surface side of the sapphire substrate 2, the n of the lowermost layer of the laminated portion 6 is formed. The conductive film 8 is formed so as to be electrically connected to the type GaN layer 31. Therefore, when manufacturing a light emitting lamp using this semiconductor light emitting element 1, bonding to a lead frame can be performed by the same simple working process as described in FIGS. 4 and 5. That is, if the conductive film 8 on the back surface of the sapphire substrate 2 is bonded to the lead frame using a conductive adhesive, the n-type G is no longer present.
It is not necessary to perform wire bonding on the aN layer 31. Therefore, the wire bonding using the gold wire may be performed only on the electrode 10, and the bonding work is facilitated.
【００２９】また、このような半導体発光素子１のボン
ディング作業工程は、実質的には図４および図５におい
て説明したボンディング作業工程と同一であるから、こ
の半導体発光素子１を部品とする青色発光ランプの製造
は、図４に示した半導体発光素子を部品とする発光ラン
プの製造装置を利用して行うことが可能となる。この半
導体発光素子１のボンディング作業を行うための装置と
して、特別仕様の製造設備を別途準備する必要はない。Since the bonding work process of the semiconductor light emitting device 1 is substantially the same as the bonding work process described in FIGS. 4 and 5, blue light emission using the semiconductor light emitting device 1 as a component is performed. The lamp can be manufactured by using the light emitting lamp manufacturing apparatus including the semiconductor light emitting element shown in FIG. 4 as a component. As a device for performing the bonding work of the semiconductor light emitting device 1, it is not necessary to separately prepare a special-purpose manufacturing facility.
【００３０】さらに、この半導体発光素子１において
は、電極１０と導電性膜８との両者間に電圧を印加して
電流供給を行うことにより、発光層４を青色に発光させ
ることができるが、この発光層４にはエッチング処理な
どが施されておらず、その面積はサファイア基板２やｎ
型半導体層３などに比較して何ら狭まっていない。した
がって、発光層４の面積が大きい分だけその発光強度を
強くでき、高い発光輝度が得られることとなる。青色の
発光ＬＥＤについては、従来において高い発光輝度を得
ることが技術的に難しいものとされていたが、発光層４
の面積を大きくすることにより発光輝度を高めることが
でき、そのような難点の解消にも役立つ効果が得られ
る。Further, in the semiconductor light emitting device 1, the light emitting layer 4 can emit blue light by applying a voltage between both the electrode 10 and the conductive film 8 to supply current. The light emitting layer 4 has not been subjected to etching treatment or the like, and its area is sapphire substrate 2 or n.
It is not narrowed in comparison with the type semiconductor layer 3 and the like. Therefore, as the area of the light emitting layer 4 is larger, the light emission intensity can be increased, and high light emission brightness can be obtained. It has been technically difficult to obtain high emission brightness for blue light emitting LEDs in the past, but the light emitting layer 4
It is possible to increase the light emission brightness by increasing the area of, and it is possible to obtain the effect of helping to solve such a difficulty.
【００３１】なお、上記実施例では、発光層４に一切エ
ッチングを施さず、半導体発光素子１の発光面積を最大
限に確保した場合を一例として説明したが、本願発明は
必ずしもこれに限定されない。本願発明では、たとえば
図３に示すように、積層部６の一部の領域Ｂａをエッチ
ングによって除去し、コンタクトホール７がサファイア
基板２の裏面からｎ型ＧａＮ層３１の表面側へ貫通する
ように形成してもよい。この場合には、発光層４の面積
が減少し、発光輝度が多少は低下するものの、従来とは
異なりｎ型ＧａＮ層３１の表面にはやはり電極を設ける
必要はない。すなわち、上記エッチングを行う領域Ｂａ
は、実際には非常に小さい領域で足りる。したがって、
発光層４の面積を大幅に狭めるようなことは回避でき、
発光層４における発光強度をやはり従来よりも強くする
ことができ、本願発明の目的を達成可能である。In the above embodiment, the case where the light emitting layer 4 is not etched at all and the light emitting area of the semiconductor light emitting device 1 is maximized has been described as an example, but the present invention is not necessarily limited to this. In the present invention, for example, as shown in FIG. 3, a partial region Ba of the laminated portion 6 is removed by etching so that the contact hole 7 penetrates from the back surface of the sapphire substrate 2 to the front surface side of the n-type GaN layer 31. You may form. In this case, although the area of the light emitting layer 4 is reduced and the light emission luminance is slightly lowered, it is not necessary to provide an electrode on the surface of the n-type GaN layer 31 unlike the conventional case. That is, the region Ba where the above etching is performed
Is actually a very small area. Therefore,
It is possible to avoid that the area of the light emitting layer 4 is significantly reduced,
The light emission intensity in the light emitting layer 4 can be made stronger than before, and the object of the present invention can be achieved.
【００３２】また、上記実施例では、青色発光ＬＥＤを
一例として説明したが、本願発明は必ずしもこれに限定
されない。本願発明は絶縁基板を用いるタイプの半導体
発光素子の全てに適用可能である。したがって、ｎ型半
導体層、発光層、およびｐ型半導体層などの具体的な材
質なども限定されない。本願発明に係る半導体発光素子
の各部の具体的な構成は種々に設計変更自在であり、ま
たその具体的な製造方法も種々に変更自在である。Further, although the blue light emitting LED has been described as an example in the above embodiment, the present invention is not necessarily limited to this. INDUSTRIAL APPLICABILITY The present invention is applicable to all types of semiconductor light emitting devices that use an insulating substrate. Therefore, specific materials such as the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer are not limited. The specific configuration of each part of the semiconductor light emitting device according to the present invention can be variously changed in design, and the specific manufacturing method thereof can be changed in various ways.
【図１】本願発明に係る半導体発光素子の一例を示す断
面図。FIG. 1 is a sectional view showing an example of a semiconductor light emitting device according to the present invention.
【図２】（ａ）〜（ｃ）は図１に示す半導体発光素子の
製造方法の一例を示す断面図。2A to 2C are cross-sectional views showing an example of a method for manufacturing the semiconductor light emitting device shown in FIG.
【図３】本願発明に係る半導体発光素子の他の例を示す
断面図。FIG. 3 is a cross-sectional view showing another example of the semiconductor light emitting device according to the present invention.
【図４】従来の半導体発光素子の一例を示す断面図。FIG. 4 is a sectional view showing an example of a conventional semiconductor light emitting device.
【図５】図４に示す半導体発光素子のボンディング作業
の一例を示す説明図。5 is an explanatory view showing an example of a bonding operation of the semiconductor light emitting element shown in FIG.
【図６】従来の半導体発光素子の他の例を示す断面図。FIG. 6 is a sectional view showing another example of a conventional semiconductor light emitting device.
【図７】図６に示す半導体発光素子のボンディング作業
の一例を示す説明図。FIG. 7 is an explanatory view showing an example of a bonding operation of the semiconductor light emitting element shown in FIG.
１ 半導体発光素子 ２ サファイア基板（絶縁基板） ３ ｎ型半導体層 ４ 発光層 ５ ｐ型半導体層 ６ 積層部 ７ コンタクトホール ８ 導電性膜 ７０ スルーホール ｍ 導電性物質 1 Semiconductor Light-Emitting Element 2 Sapphire Substrate (Insulating Substrate) 3 n-Type Semiconductor Layer 4 Light-Emitting Layer 5 p-Type Semiconductor Layer 6 Laminated Part 7 Contact Hole 8 Conductive Film 70 Through Hole m Conductive Material
Claims (2)
光層、およびｐ型半導体層から構成される積層部が形成
されている半導体発光素子において、 上記絶縁基板には、上記積層部のうち最下層のｎ型また
はｐ型の半導体層の形成位置から絶縁基板の裏面にわた
って形成されたスルーホール内に導電性物質が充填され
たコンタクトホールが形成され、かつ、 上記絶縁基板の裏面には、上記コンタクトホールを介し
て上記最下層の半導体層に導通する導電性膜が形成され
ていることを特徴とする、半導体発光素子。1. A semiconductor light emitting device having a laminated portion formed of an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer formed on a surface of an insulating substrate, wherein the laminated portion is formed on the insulating substrate. A contact hole filled with a conductive material is formed in a through hole formed from the formation position of the lowermost n-type or p-type semiconductor layer to the back surface of the insulating substrate, and the back surface of the insulating substrate is formed. Is a semiconductor light emitting device, characterized in that a conductive film is formed so as to be electrically connected to the lowermost semiconductor layer through the contact hole.
光層、およびｐ型半導体層から構成される積層部を形成
した後に、 上記絶縁基板には、上記積層部のうち最下層のｎ型また
はｐ型の半導体層の形成位置から絶縁基板の裏面にわた
ってスルーホールを形成し、 その後上記絶縁基板の裏面側へ導電性物質を堆積付着さ
せることにより、上記スルーホール内へ導電性物質を充
填させてコンタクトホールを形成するとともに、上記絶
縁基板の裏面に導電性膜を形成することを特徴とする、
半導体発光素子の製造方法。2. After forming a laminated portion composed of an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the surface of the insulating substrate, the insulating substrate is provided with a bottom layer of the laminated portion. By forming a through hole from the formation position of the n-type or p-type semiconductor layer to the back surface of the insulating substrate, and then depositing and depositing a conductive material on the back surface side of the insulating substrate, the conductive material is deposited in the through hole. A contact hole is formed by filling, and a conductive film is formed on the back surface of the insulating substrate.
Method for manufacturing semiconductor light emitting device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22020694A JPH0883929A (en) | 1994-09-14 | 1994-09-14 | Semiconductor light emitting element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22020694A JPH0883929A (en) | 1994-09-14 | 1994-09-14 | Semiconductor light emitting element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0883929A true JPH0883929A (en) | 1996-03-26 |
Family
ID=16747555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22020694A Pending JPH0883929A (en) | 1994-09-14 | 1994-09-14 | Semiconductor light emitting element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0883929A (en) |
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