JPH0870092A - 絶縁性パッケージを有する半導体デバイス - Google Patents
絶縁性パッケージを有する半導体デバイスInfo
- Publication number
- JPH0870092A JPH0870092A JP7224721A JP22472195A JPH0870092A JP H0870092 A JPH0870092 A JP H0870092A JP 7224721 A JP7224721 A JP 7224721A JP 22472195 A JP22472195 A JP 22472195A JP H0870092 A JPH0870092 A JP H0870092A
- Authority
- JP
- Japan
- Prior art keywords
- package
- wiring board
- semiconductor device
- semiconductor
- wiring boards
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract
で形成することができるように改良する。 【構成】 絶縁性パッケージ40内に同一平面内に電気
的に互いに絶縁されている複数の配線板30、31、3
2を配設し、それらの配線板30、31、32上にそれ
ぞれブリッジ整流器の半導体スイッチ33〜36を導電
的に固定し、その際配線板30〜32及び端子導体1〜
24を1つの導体枠(リードフレーム)から切り抜いて
形成する。
Description
のパッケージ内に配設された薄板製配線板、配線板上に
導電的に固定されている少なくとも1つの半導体基体、
この半導体基体と導電的に接続されている薄板製端子導
体及び配線板と導電的に接続されている少なくとも1つ
の薄板製端子導体を有する半導体デバイスに関する。
バイスは公知である。このような外観のパッケージの優
れたものには例えばDIL(デュアル・イン・ライン=
Dual−in−Line)パッケージ又はP−DSO
(プラスチック・デュアル・スモール・アウトライン=
Plastick−Dual−Small−Outli
ne)パッケージがある。前者は通常の配線用に、後者
はプリント配線板の表面配線(SMD)に使用できるも
のである。これらのパッケージは薄板製の配線板並びに
薄板製の接続端子導体を含んでおり、配線板又は配線板
上に固定されているデバイスと電気的に接続されてい
る。配線板及び端子導体は1つの導体枠(リードフレー
ム)から切り抜いて形成されている。その際半導体デバ
イスが絶縁層によって配線板と電気的に絶縁されていな
いならば、配線板上に固定されている全てのデバイスが
同じ電位を有していることは欠点である。従ってブリッ
ジ回路を容易には形成することができない。
の特徴を有する半導体デバイスのブリッジ回路を僅かな
経費で形成することができるように改良することにあ
る。
が同一平面内にある電気的に互いに絶縁されている複数
の配線板を含んでおり、それらの配線板上にブリッジ整
流器の半導体スイッチが導電的に固定されていることに
より解決される。
する。
絶縁されているプラスチック製パッケージ40に入れら
れている。パッケージ40の外形は破線により概略的に
示されている。この図のパッケージは符号1〜24を付
された24個の端子導体を有するP−DSO24型のも
のである。パッケージはそれぞれ端子導体10、12、
13、15又は4、9、16、21又は1、3、22、
24と接続されている3枚の配線板30、31、32を
含んでいる。配線板30、31、32上にはそれぞれ半
導体スイッチ33、34及び35、36が配設されてい
る。それらは配線板上に例えばろう付け又は導電性接着
剤により固着されており、そのため配線板と導電的に接
続されている。
でボンド線37〜42によって配線板とは導電的に接続
されていない他の端子導体14、17〜20、23と接
続されている。
タであってもよい。配線板30、32上にそれぞれ1個
のMOSトランジスタを、また配線板31上には2個の
MOSトランジスタを配設すれば、簡単な方法で制御さ
れる全波ブリッジを形成することができる。このような
全波ブリッジに関する結線図が図2に示されている。そ
の際図2の回路に相応する部分に図1の機械的に対応す
る部分と同じ符号が付されている。負荷の端子はA及び
Bと符号が付られており、同じ符号はそれぞれ端子3、
19、20又は14、17、18にも見られる。これら
の端子はそれぞれパッケージ内部のボンド線又はパッケ
ージの外側にある導体により互いに接続可能である。
型のMOSFET、主としてnチャネルMOSFETを
使用する場合上記の全波ブリッジに対して3枚の配線板
が必要である。それというのもこれらの場合正の端子は
常にチップの裏側にあるからである。
互いに絶縁されている2枚の配線板を備えることで十分
である。
イッチ34、35又は全てのスイッチ33〜36を制御
に必要な例えば過温度、スイッチの遮断、過電流の遮
断、状況報知のような機能を有するSMART−ICと
して形成してもよい。
り、1枚の薄板から成る導体系(リードフレーム)から
切り抜かれて形成されている。その際端子導体間にある
薄板のウェブは再プレス後に初めて除去される。その結
果直方体のパッケージから端子導体がパッケージの長手
方向に突き出すように形成される。
Claims (5)
- 【請求項1】 a)絶縁性パッケージ、 b)パッケージ内に配設された薄板製配線板、 c)配線板上に導電的に固定されている少なくとも1個
の半導体基体、 d)この半導体基体と導電的に接続されている薄板製端
子導体及び e)配線板と導電的に接続されている少なくとも1つの
薄板製端子導体を有する半導体デバイスにおいて、パッ
ケージ(40)が同一平面内にある電気的に互いに絶縁
されている複数の配線板(30、31、32)を含んで
おり、それらの配線板上にブリッジ整流器の半導体スイ
ッチが導電的に固定されていることを特徴とする半導体
デバイス。 - 【請求項2】 パッケージが2枚の配線板を有してお
り、各々の配線板上に1個の半導体スイッチが配設され
ていることを特徴とする請求項1記載の半導体デバイ
ス。 - 【請求項3】 パッケージが3枚の配線板(30、3
1、32)を有しており、1枚の配線板(31)には2
個の半導体スイッチ(34、35)が、また他の2枚の
配線板(30、32)にそれぞれ1個の半導体スイッチ
(33、36)が配設されていることを特徴とする請求
項1記載の半導体デバイス。 - 【請求項4】 配線板(30、31、32)及び端子導
体(1〜24)が一つの導体枠から切り抜かれて形成さ
れていることを特徴とする請求項1ないし3の1つに記
載の半導体デバイス。 - 【請求項5】 パッケージ(40)が直方体をしてお
り、端子導体(1〜24)が長手側にパッケージから突
出していることを特徴とする請求項1ないし4の1つに
記載の半導体デバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4428686 | 1994-08-12 | ||
DE4428686.4 | 1994-08-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0870092A true JPH0870092A (ja) | 1996-03-12 |
Family
ID=6525599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7224721A Pending JPH0870092A (ja) | 1994-08-12 | 1995-08-09 | 絶縁性パッケージを有する半導体デバイス |
Country Status (4)
Country | Link |
---|---|
US (1) | US5821618A (ja) |
EP (1) | EP0696818B1 (ja) |
JP (1) | JPH0870092A (ja) |
DE (1) | DE59510918D1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1117100A (ja) * | 1997-06-19 | 1999-01-22 | Mitsubishi Electric Corp | 半導体装置 |
DE19806817C1 (de) * | 1998-02-18 | 1999-07-08 | Siemens Ag | EMV-optimierter Leistungsschalter |
US5929520A (en) * | 1998-03-10 | 1999-07-27 | General Electric Company | Circuit with small package for mosfets |
US6054765A (en) * | 1998-04-27 | 2000-04-25 | Delco Electronics Corporation | Parallel dual switch module |
US6278199B1 (en) * | 1999-02-25 | 2001-08-21 | International Rectifier Corp. | Electronic single switch module |
JP4096831B2 (ja) * | 2003-07-09 | 2008-06-04 | 日産自動車株式会社 | 半導体装置の実装構造 |
DE102006012007B4 (de) * | 2005-03-16 | 2013-05-16 | Infineon Technologies Ag | Leistungshalbleitermodul mit oberflächenmontierbaren flachen Außenkontakten und Verfahren zur Herstellung desselben und dessen Verwendung |
DE102006020243B3 (de) * | 2006-04-27 | 2008-01-17 | Infineon Technologies Austria Ag | Leistungshalbleitermodul als H-Brückenschaltung und Verfahren zur Herstellung desselben |
DE102006049949B3 (de) | 2006-10-19 | 2008-05-15 | Infineon Technologies Ag | Halbleitermodul mit Halbleiterchips auf unterschiedlichen Versorgungspotentialen und Verfahren zur Herstelllung desselben |
US7955901B2 (en) | 2007-10-04 | 2011-06-07 | Infineon Technologies Ag | Method for producing a power semiconductor module comprising surface-mountable flat external contacts |
US20090200864A1 (en) * | 2008-02-12 | 2009-08-13 | Josef Maier | Chip on bus bar |
DE102017202770B4 (de) | 2016-08-31 | 2023-06-07 | Infineon Technologies Austria Ag | Halbleiterchipgehäuse mit einem sich wiederholenden Grundflächenmuster |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1047197A (ja) * | 1964-10-14 | |||
JPS5621355A (en) * | 1979-07-28 | 1981-02-27 | Mitsubishi Electric Corp | Semiconductor device |
DE3106376A1 (de) * | 1981-02-20 | 1982-09-09 | Siemens AG, 1000 Berlin und 8000 München | Halbleiteranordnung mit aus blech ausgeschnittenen anschlussleitern |
JPS60250659A (ja) * | 1984-05-25 | 1985-12-11 | Mitsubishi Electric Corp | 複合形半導体装置 |
JPS61225848A (ja) * | 1985-03-30 | 1986-10-07 | Toshiba Corp | 半導体整流装置 |
JPH0740790B2 (ja) * | 1987-02-23 | 1995-05-01 | 株式会社東芝 | 大電力パワ−モジユ−ル |
JPH01289278A (ja) * | 1988-05-17 | 1989-11-21 | Mitsubishi Electric Corp | 半導体集積回路 |
DE4031051C2 (de) * | 1989-11-14 | 1997-05-07 | Siemens Ag | Modul mit mindestens einem Halbleiterschaltelement und einer Ansteuerschaltung |
US5043859A (en) * | 1989-12-21 | 1991-08-27 | General Electric Company | Half bridge device package, packaged devices and circuits |
JP2708320B2 (ja) * | 1992-04-17 | 1998-02-04 | 三菱電機株式会社 | マルチチップ型半導体装置及びその製造方法 |
US5391919A (en) * | 1993-10-22 | 1995-02-21 | International Rectifier Corporation | Semiconductor power module with identical mounting frames |
-
1995
- 1995-07-25 EP EP95111686A patent/EP0696818B1/de not_active Expired - Lifetime
- 1995-07-25 DE DE59510918T patent/DE59510918D1/de not_active Expired - Lifetime
- 1995-08-09 JP JP7224721A patent/JPH0870092A/ja active Pending
- 1995-08-14 US US08/514,771 patent/US5821618A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE59510918D1 (de) | 2004-08-12 |
EP0696818A3 (de) | 1997-07-02 |
US5821618A (en) | 1998-10-13 |
EP0696818B1 (de) | 2004-07-07 |
EP0696818A2 (de) | 1996-02-14 |
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