JPH0870092A - 絶縁性パッケージを有する半導体デバイス - Google Patents

絶縁性パッケージを有する半導体デバイス

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Publication number
JPH0870092A
JPH0870092A JP7224721A JP22472195A JPH0870092A JP H0870092 A JPH0870092 A JP H0870092A JP 7224721 A JP7224721 A JP 7224721A JP 22472195 A JP22472195 A JP 22472195A JP H0870092 A JPH0870092 A JP H0870092A
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JP
Japan
Prior art keywords
package
wiring board
semiconductor device
semiconductor
wiring boards
Prior art date
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Pending
Application number
JP7224721A
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English (en)
Inventor
Alfons Dr Ing Graf
グラーフ アルフオンス
Peter Huber
フーバー ペーター
Schloegel Xaver
シユレーゲル クサーフアー
Peter Sommer
ゾンマー ペーター
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Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH0870092A publication Critical patent/JPH0870092A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】 【目的】 半導体デバイスのブリッジ回路を僅かな経費
で形成することができるように改良する。 【構成】 絶縁性パッケージ４０内に同一平面内に電気
的に互いに絶縁されている複数の配線板３０、３１、３
２を配設し、それらの配線板３０、３１、３２上にそれ
ぞれブリッジ整流器の半導体スイッチ３３〜３６を導電
的に固定し、その際配線板３０〜３２及び端子導体１〜
２４を１つの導体枠（リードフレーム）から切り抜いて
形成する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、絶縁性パッケージ、こ
のパッケージ内に配設された薄板製配線板、配線板上に
導電的に固定されている少なくとも１つの半導体基体、
この半導体基体と導電的に接続されている薄板製端子導
体及び配線板と導電的に接続されている少なくとも１つ
の薄板製端子導体を有する半導体デバイスに関する。
【０００２】
【従来の技術】このようなパッケージを有する半導体デ
バイスは公知である。このような外観のパッケージの優
れたものには例えばＤＩＬ（デュアル・イン・ライン＝
Ｄｕａｌ−ｉｎ−Ｌｉｎｅ）パッケージ又はＰ−ＤＳＯ
（プラスチック・デュアル・スモール・アウトライン＝
Ｐｌａｓｔｉｃｋ−Ｄｕａｌ−Ｓｍａｌｌ−Ｏｕｔｌｉ
ｎｅ）パッケージがある。前者は通常の配線用に、後者
はプリント配線板の表面配線（ＳＭＤ）に使用できるも
のである。これらのパッケージは薄板製の配線板並びに
薄板製の接続端子導体を含んでおり、配線板又は配線板
上に固定されているデバイスと電気的に接続されてい
る。配線板及び端子導体は１つの導体枠（リードフレー
ム）から切り抜いて形成されている。その際半導体デバ
イスが絶縁層によって配線板と電気的に絶縁されていな
いならば、配線板上に固定されている全てのデバイスが
同じ電位を有していることは欠点である。従ってブリッ
ジ回路を容易には形成することができない。
【０００３】
【発明が解決しようとする課題】本発明の課題は、上述
の特徴を有する半導体デバイスのブリッジ回路を僅かな
経費で形成することができるように改良することにあ
る。
【０００４】
【課題を解決するための手段】この課題は、パッケージ
が同一平面内にある電気的に互いに絶縁されている複数
の配線板を含んでおり、それらの配線板上にブリッジ整
流器の半導体スイッチが導電的に固定されていることに
より解決される。
【０００５】
【実施例】本発明を実施例及び図面に基づき以下に詳述
する。
【０００６】図１に基づくブリッジ整流器は全体として
絶縁されているプラスチック製パッケージ４０に入れら
れている。パッケージ４０の外形は破線により概略的に
示されている。この図のパッケージは符号１〜２４を付
された２４個の端子導体を有するＰ−ＤＳＯ２４型のも
のである。パッケージはそれぞれ端子導体１０、１２、
１３、１５又は４、９、１６、２１又は１、３、２２、
２４と接続されている３枚の配線板３０、３１、３２を
含んでいる。配線板３０、３１、３２上にはそれぞれ半
導体スイッチ３３、３４及び３５、３６が配設されてい
る。それらは配線板上に例えばろう付け又は導電性接着
剤により固着されており、そのため配線板と導電的に接
続されている。
【０００７】半導体スイッチは配線板に面していない側
でボンド線３７〜４２によって配線板とは導電的に接続
されていない他の端子導体１４、１７〜２０、２３と接
続されている。
【０００８】半導体スイッチは例えばＭＯＳトランジス
タであってもよい。配線板３０、３２上にそれぞれ１個
のＭＯＳトランジスタを、また配線板３１上には２個の
ＭＯＳトランジスタを配設すれば、簡単な方法で制御さ
れる全波ブリッジを形成することができる。このような
全波ブリッジに関する結線図が図２に示されている。そ
の際図２の回路に相応する部分に図１の機械的に対応す
る部分と同じ符号が付されている。負荷の端子はＡ及び
Ｂと符号が付られており、同じ符号はそれぞれ端子３、
１９、２０又は１４、１７、１８にも見られる。これら
の端子はそれぞれパッケージ内部のボンド線又はパッケ
ージの外側にある導体により互いに接続可能である。
【０００９】ブリッジの上半分と下半分に同じチャネル
型のＭＯＳＦＥＴ、主としてｎチャネルＭＯＳＦＥＴを
使用する場合上記の全波ブリッジに対して３枚の配線板
が必要である。それというのもこれらの場合正の端子は
常にチップの裏側にあるからである。
【００１０】半波ブリッジにはパッケージ内で電気的に
互いに絶縁されている２枚の配線板を備えることで十分
である。
【００１１】単純な可制御スイッチの代わりに例えばス
イッチ３４、３５又は全てのスイッチ３３〜３６を制御
に必要な例えば過温度、スイッチの遮断、過電流の遮
断、状況報知のような機能を有するＳＭＡＲＴ−ＩＣと
して形成してもよい。
【００１２】配線板３０、３１、３２は同一平面上にあ
り、１枚の薄板から成る導体系（リードフレーム）から
切り抜かれて形成されている。その際端子導体間にある
薄板のウェブは再プレス後に初めて除去される。その結
果直方体のパッケージから端子導体がパッケージの長手
方向に突き出すように形成される。
【図面の簡単な説明】
【図１】本発明によるブリッジ整流器の平面図。
【図２】図１のブリッジの結線図。
【符号の説明】
１〜２４ 端子導体 ３０〜３２ 配線板 ３３〜３６ 半導体スイッチ ３７〜４２ ボンド線
───────────────────────────────────────────────────── フロントページの続き (72)発明者 クサーフアー シユレーゲル ドイツ連邦共和国 83679 ザクセンカム ライフアイゼンシユトラーセ 22 (72)発明者 ペーター ゾンマー ドイツ連邦共和国 80804 ミユンヘン ケルナープラツツ ６

Claims (5)

    【特許請求の範囲】
  1. 【請求項１】 ａ）絶縁性パッケージ、 ｂ）パッケージ内に配設された薄板製配線板、 ｃ）配線板上に導電的に固定されている少なくとも１個
    の半導体基体、 ｄ）この半導体基体と導電的に接続されている薄板製端
    子導体及び ｅ）配線板と導電的に接続されている少なくとも１つの
    薄板製端子導体を有する半導体デバイスにおいて、パッ
    ケージ（４０）が同一平面内にある電気的に互いに絶縁
    されている複数の配線板（３０、３１、３２）を含んで
    おり、それらの配線板上にブリッジ整流器の半導体スイ
    ッチが導電的に固定されていることを特徴とする半導体
    デバイス。
  2. 【請求項２】 パッケージが２枚の配線板を有してお
    り、各々の配線板上に１個の半導体スイッチが配設され
    ていることを特徴とする請求項１記載の半導体デバイ
    ス。
  3. 【請求項３】 パッケージが３枚の配線板（３０、３
    １、３２）を有しており、１枚の配線板（３１）には２
    個の半導体スイッチ（３４、３５）が、また他の２枚の
    配線板（３０、３２）にそれぞれ１個の半導体スイッチ
    （３３、３６）が配設されていることを特徴とする請求
    項１記載の半導体デバイス。
  4. 【請求項４】 配線板（３０、３１、３２）及び端子導
    体（１〜２４）が一つの導体枠から切り抜かれて形成さ
    れていることを特徴とする請求項１ないし３の１つに記
    載の半導体デバイス。
  5. 【請求項５】 パッケージ（４０）が直方体をしてお
    り、端子導体（１〜２４）が長手側にパッケージから突
    出していることを特徴とする請求項１ないし４の１つに
    記載の半導体デバイス。
JP7224721A 1994-08-12 1995-08-09 絶縁性パッケージを有する半導体デバイス Pending JPH0870092A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4428686 1994-08-12
DE4428686.4 1994-08-12

Publications (1)

Publication Number Publication Date
JPH0870092A true JPH0870092A (ja) 1996-03-12

Family

ID=6525599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7224721A Pending JPH0870092A (ja) 1994-08-12 1995-08-09 絶縁性パッケージを有する半導体デバイス

Country Status (4)

Country Link
US (1) US5821618A (ja)
EP (1) EP0696818B1 (ja)
JP (1) JPH0870092A (ja)
DE (1) DE59510918D1 (ja)

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JPH1117100A (ja) * 1997-06-19 1999-01-22 Mitsubishi Electric Corp 半導体装置
DE19806817C1 (de) * 1998-02-18 1999-07-08 Siemens Ag EMV-optimierter Leistungsschalter
US5929520A (en) * 1998-03-10 1999-07-27 General Electric Company Circuit with small package for mosfets
US6054765A (en) * 1998-04-27 2000-04-25 Delco Electronics Corporation Parallel dual switch module
US6278199B1 (en) * 1999-02-25 2001-08-21 International Rectifier Corp. Electronic single switch module
JP4096831B2 (ja) * 2003-07-09 2008-06-04 日産自動車株式会社 半導体装置の実装構造
DE102006012007B4 (de) * 2005-03-16 2013-05-16 Infineon Technologies Ag Leistungshalbleitermodul mit oberflächenmontierbaren flachen Außenkontakten und Verfahren zur Herstellung desselben und dessen Verwendung
DE102006020243B3 (de) * 2006-04-27 2008-01-17 Infineon Technologies Austria Ag Leistungshalbleitermodul als H-Brückenschaltung und Verfahren zur Herstellung desselben
DE102006049949B3 (de) 2006-10-19 2008-05-15 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips auf unterschiedlichen Versorgungspotentialen und Verfahren zur Herstelllung desselben
US7955901B2 (en) 2007-10-04 2011-06-07 Infineon Technologies Ag Method for producing a power semiconductor module comprising surface-mountable flat external contacts
US20090200864A1 (en) * 2008-02-12 2009-08-13 Josef Maier Chip on bus bar
DE102017202770B4 (de) 2016-08-31 2023-06-07 Infineon Technologies Austria Ag Halbleiterchipgehäuse mit einem sich wiederholenden Grundflächenmuster

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GB1047197A (ja) * 1964-10-14
JPS5621355A (en) * 1979-07-28 1981-02-27 Mitsubishi Electric Corp Semiconductor device
DE3106376A1 (de) * 1981-02-20 1982-09-09 Siemens AG, 1000 Berlin und 8000 München Halbleiteranordnung mit aus blech ausgeschnittenen anschlussleitern
JPS60250659A (ja) * 1984-05-25 1985-12-11 Mitsubishi Electric Corp 複合形半導体装置
JPS61225848A (ja) * 1985-03-30 1986-10-07 Toshiba Corp 半導体整流装置
JPH0740790B2 (ja) * 1987-02-23 1995-05-01 株式会社東芝 大電力パワ−モジユ−ル
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Also Published As

Publication number Publication date
DE59510918D1 (de) 2004-08-12
EP0696818A3 (de) 1997-07-02
US5821618A (en) 1998-10-13
EP0696818B1 (de) 2004-07-07
EP0696818A2 (de) 1996-02-14

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