JPH0864536A - Forming method of compound semiconductor and compound semiconductor device - Google Patents
Forming method of compound semiconductor and compound semiconductor deviceInfo
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- JPH0864536A JPH0864536A JP19540294A JP19540294A JPH0864536A JP H0864536 A JPH0864536 A JP H0864536A JP 19540294 A JP19540294 A JP 19540294A JP 19540294 A JP19540294 A JP 19540294A JP H0864536 A JPH0864536 A JP H0864536A
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- compound semiconductor
- single crystal
- layer
- group
- forming
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、II−VI族化合物半導体
の形成方法及びII−VI族化合物半導体を用いた化合物半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a II-VI group compound semiconductor and a compound semiconductor device using the II-VI group compound semiconductor.
【０００２】[0002]
【従来の技術】基板上に半導体の単結晶と多結晶を同時
に形成する方法は、III−Ｖ族化合物半導体に関してア
プライド・フィジックス・レターズ第２９巻（１９７６
年）第１６４頁から第１６６頁（Appl．Phys．Lett．vo
l 29，（1976）pp164〜166）に開示されている。この化
合物半導体の形成方法は、図６に示すように、ｎ型Ｇａ
Ａｓ基板１の上に、ｎ型ＡｌＧａＡｓ層３１、ｎ型Ｇａ
Ａｓ層３２及びｐ型ＡｌＧａＡｓ層３３を分子線エピタ
キシー（ＭＢＥ）法により成長させた後（図６
（ａ））、ＳｉＯ2膜の堆積、ホトリソグラフィー及び
エッチングによりＳｉＯ2パタン３４の形成を行い（図
６（ｂ））、再びＭＢＥ法により、ｐ型単結晶ＡｌＧａ
Ａｓ層３５とＡｌＧａＡｓ多結晶層３６、ｐ型単結晶Ｇ
ａＡｓ層３７とＧａＡｓ多結晶層３８をそれぞれ同時に
成長させて形成している。そして、ｐ型電極１３及びｎ
型電極１４をそれぞれ試料の表面及び裏面に形成して半
導体レーザを作製している（図６（ｃ））。2. Description of the Related Art A method for simultaneously forming a single crystal and a polycrystal of a semiconductor on a substrate is described in Applied Physics Letters, Vol. 29 (1976) regarding III-V group compound semiconductors.
Pp. 164 to 166 (Appl. Phys. Lett. Vo)
29, (1976) pp164-166). As shown in FIG. 6, the method of forming this compound semiconductor is based on n-type Ga
On the As substrate 1, n-type AlGaAs layer 31, n-type Ga
After growing the As layer 32 and the p-type AlGaAs layer 33 by the molecular beam epitaxy (MBE) method (FIG. 6).
(A)), the SiO 2 film is deposited, the SiO 2 pattern 34 is formed by photolithography and etching (FIG. 6B), and the p-type single crystal AlGa is again formed by the MBE method.
As layer 35, AlGaAs polycrystal layer 36, p-type single crystal G
The aAs layer 37 and the GaAs polycrystal layer 38 are simultaneously grown and formed. Then, the p-type electrode 13 and n
The mold electrodes 14 are formed on the front surface and the back surface of the sample, respectively, to fabricate a semiconductor laser (FIG. 6C).
【０００３】[0003]
【発明が解決しようとする課題】上記従来技術は、Ｓｉ
Ｏ2パタン形成時にｐ型ＡｌＧａＡｓ層３３表面は大気
に露出されて酸化される。この自然酸化膜はＭＢＥ法に
よる再成長のときに基板温度を６５０℃程度まで昇温す
ることにより除去されていた。ところが、上記従来技術
をII−VI族化合物半導体に適用する場合、基板温度を３
５０℃以上にすると、II−VI族化合物半導体単結晶中に
空孔や格子間原子等の点欠陥が発生するという問題があ
った。また、II−VI族化合物半導体をＭＢＥ法により再
成長させた後、室温まで降温する過程でＳｉＯ2膜とII
−VI族化合物半導体層の界面付近から単結晶領域に向か
って多数の転位が発生するという問題もあった。これら
は、III−Ｖ族化合物半導体に比較してII−VI族化合物
半導体の結合エネルギーが小さいことに起因しており、
前者の問題はII−VI族化合物半導体の加熱が、後者の問
題はＳｉＯ2膜との熱膨張係数差が直接要因となってい
る。SUMMARY OF THE INVENTION The above prior art is based on Si
When the O 2 pattern is formed, the surface of the p-type AlGaAs layer 33 is exposed to the atmosphere and is oxidized. This natural oxide film was removed by raising the substrate temperature to about 650 ° C. during regrowth by the MBE method. However, when the above-mentioned conventional technique is applied to the II-VI group compound semiconductor, the substrate temperature is set to 3
When the temperature is 50 ° C. or higher, there is a problem that point defects such as vacancies and interstitial atoms occur in the II-VI group compound semiconductor single crystal. In addition, after the II-VI group compound semiconductor is regrown by the MBE method and then cooled to room temperature, the SiO 2 film and the II
There is also a problem in that a large number of dislocations are generated from the vicinity of the interface of the —VI compound semiconductor layer toward the single crystal region. These are due to the smaller binding energy of II-VI group compound semiconductors compared to III-V group compound semiconductors.
The former problem is directly due to the heating of the II-VI group compound semiconductor, and the latter problem is directly due to the difference in thermal expansion coefficient from the SiO 2 film.
【０００４】本発明の第１の目的は、結晶性のよいII−
VI族化合物半導体単結晶をII−VI族化合物半導体多結晶
と同時に形成する化合物半導体の形成方法を提供するこ
とにある。The first object of the present invention is II- which has good crystallinity.
It is to provide a method for forming a compound semiconductor in which a group VI compound semiconductor single crystal is formed simultaneously with a group II-VI compound semiconductor polycrystal.
【０００５】本発明の第２の目的は、結晶性のよいII−
VI族化合物半導体単結晶とII−VI族化合物半導体多結晶
を有する化合物半導体装置を提供することにある。The second object of the present invention is II- which has good crystallinity.
A compound semiconductor device having a group VI compound semiconductor single crystal and a group II-VI compound semiconductor polycrystal is provided.
【０００６】[0006]
【課題を解決するための手段】上記第１の目的を達成す
るために、本発明の化合物半導体の形成方法は、基板上
に、化合物半導体単結晶層を形成し、この化合物半導体
単結晶層の所望の部分に、II−VI族化合物半導体の酸化
物からなるマスクを形成し、マスクの開口部の化合物半
導体単結晶層上に、II−VI族化合物半導体単結晶を、マ
スク上に、II−VI族化合物半導体多結晶を同時に形成す
るようにしたものである。In order to achieve the first object, the method for forming a compound semiconductor according to the present invention comprises forming a compound semiconductor single crystal layer on a substrate and forming the compound semiconductor single crystal layer. A mask made of an oxide of a II-VI compound semiconductor is formed at a desired portion, a II-VI compound semiconductor single crystal is formed on the compound semiconductor single crystal layer at the opening of the mask, and a II-VI compound semiconductor is formed on the mask. A group VI compound semiconductor polycrystal is simultaneously formed.
【０００７】上記化合物半導体単結晶層は、II−VI族化
合物半導体単結晶層であることが好ましい。このように
II−VI族化合物半導体単結晶層を用いたとき、上記酸化
物からなるマスクの形成は、このII−VI族化合物半導体
単結晶層の所望の部分の表面部分を酸化して行うことが
できる。The compound semiconductor single crystal layer is preferably a II-VI group compound semiconductor single crystal layer. in this way
When the II-VI group compound semiconductor single crystal layer is used, the mask made of the above oxide can be formed by oxidizing a surface portion of a desired portion of the II-VI compound semiconductor single crystal layer.
【０００８】さらに、上記のように化合物半導体単結晶
層としてII−VI族化合物半導体単結晶層を用いるとき、
この単結晶層を形成して後に、このII−VI族化合物半導
体単結晶層上に表面保護膜を形成することが好ましい。
このようにしたとき、この表面保護膜の所望の部分を除
去し、この部分のII−VI族化合物半導体単結晶層の表面
部分を酸化することにより、上記の酸化物からなるマス
クとすることができる。Further, when the II-VI group compound semiconductor single crystal layer is used as the compound semiconductor single crystal layer as described above,
After forming this single crystal layer, it is preferable to form a surface protective film on this II-VI group compound semiconductor single crystal layer.
In this case, by removing a desired portion of the surface protective film and oxidizing the surface portion of the II-VI group compound semiconductor single crystal layer in this portion, a mask made of the above oxide can be obtained. it can.
【０００９】この表面保護膜は、１５０℃以下の温度で
蒸発する非晶質体からなることが好ましい。例えば、Ｓ
及びＳｅからなる群から選ばれた少なくとも一種の物質
を表面保護膜として用いることができる。このような物
質を用いれば、上記の表面保護膜の除去は、１５０℃以
下の加熱により行うことができる。表面保護膜の厚さ
は、その下の領域の酸化防止のために１ｎｍ以上である
ことが好ましい。厚さの上限は特に定めなくともよい
が、一般には膜形成と膜の蒸発の時間を節約するため
に、１０ｎｍ以下とすることが好ましい。The surface protective film is preferably made of an amorphous material which evaporates at a temperature of 150 ° C. or lower. For example, S
And at least one substance selected from the group consisting of Se can be used as the surface protective film. If such a substance is used, the removal of the surface protective film can be performed by heating at 150 ° C. or lower. The thickness of the surface protective film is preferably 1 nm or more in order to prevent the oxidation of the underlying region. The upper limit of the thickness does not have to be specified in particular, but generally it is preferably 10 nm or less in order to save the time for film formation and film evaporation.
【００１０】上記のII−VI族化合物半導体単結晶と、II
−VI族化合物半導体多結晶との同時形成は、１５０℃か
ら３５０℃の範囲の温度で行うことが好ましく、２５０
℃から３５０℃の範囲の温度で行うことがより好まし
い。形成時の圧力は、１０-5Torrから１０-10Torrの範
囲であることが好ましい。II-VI compound semiconductor single crystal as described above, II
Simultaneous formation with the group VI compound semiconductor polycrystal is preferably carried out at a temperature in the range of 150 ° C to 350 ° C.
More preferably, it is carried out at a temperature in the range of ℃ to 350 ℃. The pressure during formation is preferably in the range of 10 -5 Torr to 10 -10 Torr.
【００１１】また、上記第２の目的を達成するために、
本発明の化合物半導体装置は、上記のいずれかの方法で
製造されたII−VI族化合物半導体と、そのII−VI族化合
物半導体単結晶の少なくとも１部に設けられた化合物半
導体素子とから構成されるようにしたものである。In order to achieve the above second object,
A compound semiconductor device of the present invention comprises a II-VI group compound semiconductor manufactured by any one of the above methods, and a compound semiconductor element provided in at least a part of the II-VI group compound semiconductor single crystal. It was done so.
【００１２】さらに、上記第２の目的を達成するため
に、本発明の化合物半導体装置は、基板上に設けられ
た、II−VI族化合物半導体単結晶層と、このII−VI族化
合物半導体単結晶層の所望の領域の上に設けられたII−
VI族化合物半導体の酸化物からなるマスクと、マスク上
に設けられたII−VI族化合物半導体多結晶と、マスクの
開口部の上記II−VI族化合物半導体単結晶層上に設けら
れたII−VI族化合物半導体のエピタキシャル層と、この
エピタキシャル層の少なくとも１部に設けられた化合物
半導体素子とからなるようにしたものである。Further, in order to achieve the second object, the compound semiconductor device of the present invention has a II-VI group compound semiconductor single crystal layer provided on a substrate and the II-VI group compound semiconductor single crystal layer. II- provided on the desired region of the crystal layer
A mask made of an oxide of a Group VI compound semiconductor, a II-VI group compound semiconductor polycrystal provided on the mask, and a II-group provided on the II-VI group compound semiconductor single crystal layer in the opening of the mask An epitaxial layer of a group VI compound semiconductor and a compound semiconductor element provided in at least a part of the epitaxial layer.
【００１３】[0013]
【作用】II−VI族化合物半導体の酸化物のマスクの上
に、II−VI族化合物半導体を成長させると、マスクの開
口部の酸化物のない領域には単結晶が、マスクの酸化物
のある領域には多結晶層が形成されることが透過型電子
顕微鏡による観察により確認された。また、II−VI族化
合物半導体の成長終了後、室温まで降温する過程で転位
の発生は見られなかった。これは、熱膨張係数がII−VI
族化合物半導体とその酸化物で近いためであると考えら
れる。When the II-VI group compound semiconductor is grown on the II-VI group compound oxide mask, a single crystal is formed in the oxide-free area of the mask opening, and It was confirmed by observation with a transmission electron microscope that a polycrystalline layer was formed in a certain region. Further, after the growth of the II-VI group compound semiconductor was completed, no dislocation was observed in the process of cooling to room temperature. This has a thermal expansion coefficient of II-VI.
This is probably because the group compound semiconductor and its oxide are close to each other.
【００１４】また、化合物半導体を成長させた試料の表
面に表面保護膜としてＳｅ膜又はＳ膜等を形成して、大
気に露出する実験を行った結果、表面保護膜の膜厚が１
ｎｍ以上あれば、自然酸化は表面保護膜のみに発生し
て、その下地の化合物半導体にまで到達しないことが明
らかとなった。また、１５０℃以下の温度で加熱するこ
とにより、この表面保護膜は下地の化合物半導体に結晶
欠陥を形成することなく、容易に蒸発することも判明し
た。Further, as a result of conducting an experiment of forming a Se film or an S film as a surface protective film on the surface of the sample on which the compound semiconductor is grown and exposing it to the atmosphere, the film thickness of the surface protective film is 1
It has been revealed that when the thickness is not less than nm, natural oxidation occurs only in the surface protective film and does not reach the underlying compound semiconductor. It was also found that by heating at a temperature of 150 ° C. or lower, this surface protective film was easily evaporated without forming crystal defects in the underlying compound semiconductor.
【００１５】そこで、例えば、II−VI族化合物半導体を
成長させた試料に、Ｓｅ等からなる膜厚１ｎｍ以上の表
面保護膜を形成し、そして、試料の単結晶を形成しよう
とする領域にホトレジスト膜を形成し、１５０℃程度以
下の温度で加熱すれば、ホトレジストのない多結晶を形
成しようとする領域で表面保護膜の選択的蒸発が行え、
かつ、この際に大気に露出したこの領域のII−VI族化合
物半導体表面は自然酸化され、II−VI族化合物半導体の
酸化物が形成される。この酸化物層の膜厚は１０−２０
ｎｍ程度であり、マスクとして用いることができる。Therefore, for example, a surface protective film of Se or the like having a film thickness of 1 nm or more is formed on a sample on which a II-VI group compound semiconductor is grown, and a photoresist is formed on a region where a single crystal of the sample is to be formed. If a film is formed and heated at a temperature of about 150 ° C. or lower, selective evaporation of the surface protective film can be performed in a region where a photoresist-free polycrystal is to be formed.
At this time, the surface of the II-VI group compound semiconductor in this region exposed to the atmosphere is naturally oxidized and an oxide of the II-VI group compound semiconductor is formed. The thickness of this oxide layer is 10-20.
Since it is about nm, it can be used as a mask.
【００１６】さらに、試料のホトレジストを除去後、Ｍ
ＢＥ装置に導入し、基板温度２５０℃にて単結晶形成領
域の表面保護膜を蒸発させる。この際、基板温度が低い
ため、II−VI族化合物半導体酸化物層の蒸発は起こら
ず、II−VI族化合物半導体中の点欠陥発生もない。その
後、同一基板温度にてII−VI族化合物半導体単結晶と多
結晶の同時ＭＢＥ成長を行うことができる。Further, after removing the photoresist of the sample, M
It is introduced into a BE apparatus and the surface protective film in the single crystal formation region is evaporated at a substrate temperature of 250 ° C. At this time, since the substrate temperature is low, evaporation of the II-VI group compound semiconductor oxide layer does not occur, and no point defect occurs in the II-VI group compound semiconductor. Then, simultaneous MBE growth of II-VI group compound semiconductor single crystal and polycrystal can be performed at the same substrate temperature.
【００１７】[0017]
＜実施例１＞以下、本発明の第１の実施例を図１を用い
て説明する。図１はII−VI族化合物半導体レーザの製造
工程を示す縦断面構造図である。始めに、ｎ型ＧａＡｓ
基板１（電子濃度＝１×１０18／ｃｍ3、不純物＝Ｃ
ｌ）上に、ＭＢＥ法により、ｎ型ＺｎＳ0.06Ｓｅ0.94バ
ッファ層２（電子濃度＝１×１０18／ｃｍ3、不純物＝
Ｃｌ、膜厚＝０．５μｍ）、ｎ型Ｚｎ0.9Ｍｇ0.1Ｓ0.2
Ｓｅ0.8クラッド層３（電子濃度＝５×１０17／ｃｍ3、
不純物＝Ｃｌ、膜厚＝０．５μｍ）、Ｚｎ0.85Ｃｄ0.15
Ｓｅ活性層４（膜厚５ｎｍ、ただし光ガイド層として、
上下にｐ型ＺｎＳ0.06Ｓｅ0.94層（正孔濃度＝１×１０
17／ｃｍ3、不純物＝Ｎ、膜厚＝０．１μｍ）及びｎ型
ＺｎＳ0.06Ｓｅ0.94（電子濃度＝１×１０17／ｃｍ3、
不純物＝Ｃｌ、膜厚＝０．１μｍ）を含む）、ｐ型Ｚｎ
0.9Ｍｇ0.1Ｓ0.2Ｓｅ0.8クラッド層５（正孔濃度＝５×
１０17／ｃｍ3、不純物＝Ｎ、膜厚＝０．３μｍ）を基
板温度２５０℃にて成長させた。続いて、基板温度を２
０〜５０℃まで下げ、Ｓｅ分子線のみを供給することに
より、表面保護層としてＳｅ膜６（膜厚＝２ｎｍ）を形
成した（図１（ａ））。<First Embodiment> A first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a longitudinal sectional structural view showing a manufacturing process of a II-VI group compound semiconductor laser. First, n-type GaAs
Substrate 1 (electron concentration = 1 × 10 18 / cm 3 , impurity = C
On l), by MBE, n-type ZnS 0. 06 Se 0. 94 buffer layer 2 (electron concentration = 1 × 10 18 / cm 3 , the impurity =
Cl, thickness = 0.5 [mu] m), n-type Zn 0. 9 Mg 0. 1 S 0. 2
Se 0. 8 cladding layer 3 (electron concentration = 5 × 10 17 / cm 3 ,
Impurities = Cl, thickness = 0.5μm), Zn 0. 85 Cd 0. 15
Se active layer 4 (film thickness 5 nm, provided as an optical guide layer,
P-type ZnS 0 vertically. 06 Se 0. 94 layer (hole concentration = 1 × 10
17 / cm 3, the impurity = N, thickness = 0.1 [mu] m) and n-type ZnS 0. 06 Se 0. 94 ( electron concentration = 1 × 10 17 / cm 3 ,
(Impurity = Cl, film thickness = 0.1 μm)), p-type Zn
0. 9 Mg 0. 1 S 0. 2 Se 0. 8 cladding layer 5 (hole concentration = 5 ×
10 17 / cm 3 , impurity = N, film thickness = 0.3 μm) was grown at a substrate temperature of 250 ° C. Then, set the substrate temperature to 2
By lowering the temperature to 0 to 50 ° C. and supplying only Se molecular beam, an Se film 6 (film thickness = 2 nm) was formed as a surface protective layer (FIG. 1A).
【００１８】その後、試料をＭＢＥ装置から取り出し、
ホトリソグラフィーにより試料の単結晶形成領域のみに
ホトレジスト７（膜厚＝１μｍ）を形成した。そして、
試料を窒素雰囲気にて１２０℃、１０分間加熱すること
により、ホトレジスト７のない多結晶形成領域のＳｅ膜
６を蒸発させた。この際、ｐ型Ｚｎ0.9Ｍｇ0.1Ｓ0.2Ｓ
ｅ0.8クラッド層５の表面から約２０ｎｍは酸化され、
Ｚｎ酸化物を主成分とするＺｎＭｇＳＳｅ酸化物層８が
形成された（図１（ｂ））。Thereafter, the sample was taken out from the MBE device,
A photoresist 7 (film thickness = 1 μm) was formed only on the single crystal formation region of the sample by photolithography. And
By heating the sample in a nitrogen atmosphere at 120 ° C. for 10 minutes, the Se film 6 in the polycrystalline formation region without the photoresist 7 was evaporated. At this time, p-type Zn 0. 9 Mg 0. 1 S 0. 2 S
e 0. 8 to about 20nm from the surface of the cladding layer 5 is oxidized,
A ZnMgSSe oxide layer 8 containing Zn oxide as a main component was formed (FIG. 1B).
【００１９】ホトレジスト７を除去した試料をＭＢＥ装
置に再導入し、２５０℃に加熱して単結晶形成領域のＳ
ｅ膜６を蒸発させ、同一温度で、ｐ型Ｚｎ0.9Ｍｇ0.1Ｓ
0.2Ｓｅ0.8クラッド層９（正孔濃度＝５×１０17／ｃｍ
3、不純物＝Ｎ、膜厚＝０．３μｍ）とＺｎ0.9Ｍｇ0.1
Ｓ0.2Ｓｅ0.8多結晶層１０（膜厚＝０．３μｍ）、次に
ｐ型ＺｎＳｅＴｅコンタクト層１１（傾斜組成構造、基
板側：ＺｎＳｅ、表面側：ＺｎＴｅ、正孔濃度＝５×１
０17／ｃｍ3（基板側）〜２×１０19／ｃｍ3（表面
側）、不純物＝Ｎ、膜厚＝０．２μｍ）とＺｎＳｅＴｅ
多結晶層１２（基板側がＺｎＳｅリッチ、表面側がＺｎ
Ｔｅリッチであるが多結晶体のため、単結晶層のように
明確に分離しない、膜厚＝０．２μｍ）をそれぞれ同時
にＭＢＥ法により再成長させた。なお、ＺｎＭｇＳＳｅ
酸化物層８上に形成されたＺｎ0.9Ｍｇ0.1Ｓ0.2Ｓｅ0.8
多結晶層１０とＺｎＳｅＴｅ多結晶層１２は高抵抗の絶
縁体であることが電気抵抗測定の結果から確認された。
最後に、試料表面にｐ型電極１３をリフトオフ法によ
り、試料裏面にｎ型電極１４を全面堆積により形成し
て、II−VI族化合物半導体レーザを作製した（図１
（ｃ））。半導体レーザ作製用の単結晶領域幅は１０μ
ｍとした。The sample from which the photoresist 7 has been removed is reintroduced into the MBE apparatus and heated to 250 ° C. to remove S in the single crystal formation region.
evaporated e film 6, at the same temperature, p-type Zn 0. 9 Mg 0. 1 S
0. 2 Se 0. 8 cladding layer 9 (hole concentration = 5 × 10 17 / cm
3, impurity = N, thickness = 0.3 [mu] m) and Zn 0. 9 Mg 0. 1
.. S 0 2 Se 0 8 polycrystalline layer 10 (film thickness = 0.3 [mu] m), then p-type ZnSeTe contact layer 11 (gradient composition structure, substrate: ZnSe, surface: ZnTe, hole concentration = 5 × 1
0 17 / cm 3 (substrate side) to 2 × 10 19 / cm 3 (surface side), impurity = N, film thickness = 0.2 μm) and ZnSeTe
Polycrystalline layer 12 (ZnSe rich on the substrate side, Zn on the surface side
Since they are Te-rich but polycrystalline, they are not clearly separated like a single crystal layer and have a film thickness of 0.2 μm) were regrown at the same time by the MBE method. In addition, ZnMgSSe
Zn 0 formed on the oxide layer 8. 9 Mg 0. 1 S 0. 2 Se 0. 8
It was confirmed from the results of electric resistance measurement that the polycrystalline layer 10 and the ZnSeTe polycrystalline layer 12 were high-resistance insulators.
Finally, a p-type electrode 13 was formed on the front surface of the sample by a lift-off method, and an n-type electrode 14 was formed on the back surface of the sample by blanket deposition to fabricate a II-VI group compound semiconductor laser (FIG. 1).
(C)). Single crystal region width for semiconductor laser fabrication is 10μ
m.
【００２０】本実施例によれば、II−VI族化合物半導体
単結晶を、その結晶性を劣化させずに、高抵抗のII−VI
族化合物半導体多結晶と同時に形成できる効果がある。
また、本実施例により作製されたII−VI族化合物半導体
レーザは、高抵抗II−VI族化合物半導体多結晶が電流ブ
ロック層として作用する電流狭窄構造となっているた
め、全面がII−VI族化合物半導体単結晶からなる従来型
II−VI族化合物半導体レーザに比較してしきい電流が１
／１０以下に低減する効果も見られた。According to the present embodiment, the II-VI group compound semiconductor single crystal is formed into a high-resistance II-VI compound without deteriorating its crystallinity.
There is an effect that it can be formed simultaneously with the group compound semiconductor polycrystal.
Further, since the II-VI group compound semiconductor laser manufactured according to this example has a current confinement structure in which the high-resistance II-VI group compound semiconductor polycrystal acts as a current block layer, the entire surface is a II-VI group semiconductor. Conventional type consisting of compound semiconductor single crystal
Threshold current is 1 compared to II-VI group compound semiconductor lasers
The effect of reducing to / 10 or less was also observed.
【００２１】なお、本実施例で示したII−VI族化合物半
導体混晶の組成は、本実施例の通りでなくてもよいのは
もちろんである。また、基板にはｎ型ＧａＡｓを用いた
が、ｐ型ＧａＡｓ基板や、ＩｎＰ、ＧａＰ、Ｓｉ、Ｚｎ
Ｓｅ等他の半導体基板を用いても同様に実施できる。It is needless to say that the composition of the II-VI group compound semiconductor mixed crystal shown in this embodiment need not be the same as that in this embodiment. Although n-type GaAs was used as the substrate, a p-type GaAs substrate, InP, GaP, Si, Zn were used.
The same operation can be performed using another semiconductor substrate such as Se.
【００２２】＜実施例２＞実施例１のＳｅ膜６の代わり
にＳ膜（膜厚２ｎｍ）を表面保護膜として用いた。Ｓ膜
もＳｅ膜と同様に１２０℃の加熱により蒸発し、実施例
１と同様に良質のII−VI族化合物半導体単結晶をII−VI
族化合物半導体多結晶と同時に形成することができた。
また、作製されたII−VI族化合物半導体レーザの特性も
実施例１と同様であった。なお、Ｓｅ膜６に変えて、１
５０℃以下の温度で蒸発する非晶質の膜、例えば、Ｓと
Ｓｅの混晶の膜を用いても同様の効果が得られることは
明らかである。Example 2 Instead of the Se film 6 of Example 1, an S film (film thickness 2 nm) was used as a surface protective film. Similar to the Se film, the S film also evaporates by heating at 120 ° C., and a high-quality II-VI group compound semiconductor single crystal is obtained as in Example 1 by using II-VI.
It could be formed simultaneously with the group compound semiconductor polycrystal.
The characteristics of the manufactured II-VI group compound semiconductor laser were also similar to those of Example 1. In addition, instead of the Se film 6, 1
It is apparent that the same effect can be obtained by using an amorphous film that evaporates at a temperature of 50 ° C. or lower, for example, a mixed crystal film of S and Se.
【００２３】＜実施例３＞実施例１におけるｐ型Ｚｎ0.
9Ｍｇ0.1Ｓ0.2Ｓｅ0.8クラッド層９をＺｎＳ0.2Se0.
8（正孔濃度＝５×１０17／ｃｍ3、不純物＝Ｎ、膜厚＝
１８ｎｍ）／ＭｇＳ0.2Ｓｅ0.8（正孔濃度＝５×１０17
／ｃｍ3、不純物＝Ｎ、膜厚＝２ｎｍ）超格子１５０周
期から構成した。この際、ＭＢＥ法で同時形成される多
結晶層１０はＺｎ0.9Ｍｇ0.1Ｓ0.2Ｓｅ0.8混晶となっ
た。これは多結晶層１０の粒径が０．１μｍ程度と大き
く、短周期の超格子が形成されなかったためである。[0023] p-type Zn 0 in <Example 3> Example 1.
9 Mg 0. 1 S 0. 2 Se 0. 8 cladding layer 9 of ZnS 0. 2 Se 0.
8 (hole concentration = 5 × 10 17 / cm 3 , impurity = N, film thickness =
18nm) / MgS 0. 2 Se 0. 8 ( hole concentration = 5 × 10 17
/ Cm 3 , impurity = N, film thickness = 2 nm) 150 periods of superlattice. At this time, the polycrystalline layer 10 are simultaneously formed by the MBE method became Zn 0. 9 Mg 0. 1 S 0. 2 Se 0. 8 mixed crystal. This is because the grain size of the polycrystalline layer 10 was as large as about 0.1 μm and a short period superlattice was not formed.
【００２４】ＺｎＳＳｅ／ＭｇＳＳｅ単結晶の超格子層
の屈折率が約３．９であったのに対し、ＺｎＭｇＳＳｅ
混晶の多結晶層の屈折率は約３．５と小さく、II−VI族
化合物半導体レーザにおける光閉じ込めが有効に行われ
た結果、全面がII−VI族化合物半導体単結晶からなる従
来型II−VI族化合物半導体レーザに比較して横モード制
御に優れ、しかもしきい電流が従来の１／２０以下に低
減する効果もあった。なお、本実施例ではクラッド層９
にＺｎＳＳｅ／ＭｇＳＳｅ超格子を用いたが、ＺｎＭｇ
Ｓ等他の組合せによる３元混晶超格子や、２元又は４元
混晶からなる超格子を用いてもよいのはもちろんであ
る。While the refractive index of the superlattice layer of ZnSSe / MgSSe single crystal was about 3.9, ZnMgSSe
The refractive index of the mixed crystal polycrystalline layer is as small as about 3.5, and as a result of effective optical confinement in the II-VI compound semiconductor laser, the conventional type II composed entirely of II-VI compound semiconductor single crystal was obtained. Compared with the group VI compound semiconductor laser, the lateral mode control was excellent, and the threshold current was reduced to 1/20 or less of the conventional one. In this embodiment, the cladding layer 9
ZnSSe / MgSSe superlattice was used for
It is needless to say that a ternary mixed crystal superlattice formed by another combination such as S or a superlattice formed of a binary or quaternary mixed crystal may be used.
【００２５】＜実施例４＞以下、本発明の第４の実施例
を図２から図５を用いて説明する。図２から図５は、II
−VI族化合物半導体ヘテロ接合バイポーラトランジスタ
の製造工程を示す縦断面構造図である。始めに、ｎ型Ｇ
ａＡｓ基板１（電子濃度＝１×１０18／ｃｍ3、不純物
＝Ｃｌ）上に、ＭＢＥ法によりｎ型ＺｎＳ0.06Ｓｅ0.94
サブコレクタ層２’（電子濃度＝１×１０18／ｃｍ3、
不純物＝Ｃｌ、膜厚＝０．５μｍ）を基板温度２５０℃
にて成長させた。続いて、基板温度を２０〜５０℃まで
下げ、Ｓｅ分子線のみを供給することにより表面保護層
としてＳｅ膜６（膜厚＝１ｎｍ）を形成した（図２）。<Fourth Embodiment> A fourth embodiment of the present invention will be described below with reference to FIGS. 2 to 5 are II
FIG. 6 is a vertical cross-sectional structure diagram showing a manufacturing process of a group VI compound semiconductor heterojunction bipolar transistor. First, n-type G
aAs substrate 1 (electron concentration = 1 × 10 18 / cm 3 , the impurity = Cl) on, n-type ZnS 0 by MBE. 06 Se 0. 94
Sub-collector layer 2 ′ (electron concentration = 1 × 10 18 / cm 3 ,
Impurity = Cl, film thickness = 0.5 μm) substrate temperature 250 ° C.
I grew it up. Then, the substrate temperature was lowered to 20 to 50 ° C., and only the Se molecular beam was supplied to form the Se film 6 (film thickness = 1 nm) as a surface protective layer (FIG. 2).
【００２６】その後、試料をＭＢＥ装置から取り出し、
ホトリソグラフィーにより試料の単結晶形成領域のみに
ホトレジスト７（膜厚＝１μｍ）を形成した。そして、
試料を窒素雰囲気にて１２０℃、１０分間加熱すること
により、ホトレジスト７のない多結晶形成領域のＳｅ膜
６を蒸発させた。この際、ｎ型ＺｎＳ0.06Ｓｅ0.94サブ
コレクタ層２’の表面から約１０ｎｍは酸化されて酸化
物層８が形成された（図３）。Thereafter, the sample is taken out from the MBE device,
A photoresist 7 (film thickness = 1 μm) was formed only on the single crystal formation region of the sample by photolithography. And
By heating the sample in a nitrogen atmosphere at 120 ° C. for 10 minutes, the Se film 6 in the polycrystalline formation region without the photoresist 7 was evaporated. At this time, n-type ZnS 0. 06 Se 0. 94 to about 10nm from the surface of the subcollector layer 2 'oxide layer 8 is oxidized is formed (FIG. 3).
【００２７】ホトレジトスト７を除去した試料をＭＢＥ
装置に再導入し、２５０℃に加熱して単結晶形成領域の
Ｓｅ膜６を蒸発させ、同一温度でＭＢＥ法により、同時
に、ｎ型ＺｎＳ0.06Ｓｅ0.94コレクタ層２１（電子濃度
＝５×１０16／ｃｍ3、不純物＝Ｃｌ、膜厚＝０.６μ
ｍ）とＺｎＳ0.06Ｓｅ0.94多結晶層２２（膜厚＝０．６
μｍ）をそれぞれ再成長させて形成した。同様にｐ型Ｚ
ｎＳ0.06Ｓｅ0.94ベース層２３（正孔濃度＝１×１０18
／ｃｍ3、不純物＝Ｎ、膜厚＝０．１μｍ）とＺｎＳ0.
06Ｓｅ0.94多結晶層２４（膜厚＝０．１μｍ）を、ｎ型
Ｚｎ0.9Ｍｇ0.1Ｓ0.2Ｓｅ0.8エミッタ層２５（電子濃度
＝５×１０17／ｃｍ3、不純物＝Ｃｌ、膜厚＝０．１５
μｍ）とＺｎ0.9Ｍｇ0.1Ｓ0.2Ｓｅ0.8多結晶層２６（膜
厚＝０．１５μｍ）を、次にｎ型ＺｎＳ0.06Ｓｅ0.94コ
ンタクト層２７（電子濃度＝５×１０18／ｃｍ3、不純
物＝Ｃｌ、膜厚＝０．２μｍ）とＺｎＳ0.06Ｓｅ0.94多
結晶層２８（膜厚＝０．２μｍ）をそれぞれ再成長させ
て形成した（図４）。この際、II−VI族化合物半導体の
多結晶層２２、２４、２６及び２８は、高抵抗であるこ
とが電気抵抗測定の結果から確認された。MBE was performed on the sample from which Photoresist tost 7 was removed.
Reintroduced apparatus, was heated to 250 ° C. to evaporate the Se film 6 of a single crystal formation region, by the MBE method at the same temperature, at the same time, n-type ZnS 0. 06 Se 0. 94 collector layer 21 (electron concentration = 5 × 10 16 / cm 3 , impurity = Cl, film thickness = 0.6 μ
m) and ZnS 0. 06 Se 0. 94 polycrystalline layer 22 (film thickness = 0.6
μm) was regrown. Similarly p-type Z
nS 0. 06 Se 0. 94 base layer 23 (hole concentration = 1 × 10 18
/ Cm 3 , impurity = N, film thickness = 0.1 μm) and ZnS 0 ..
06 Se 0 to. 94 polycrystalline layer 24 (film thickness = 0.1 [mu] m), n-type Zn 0. 9 Mg 0. 1 S 0. 2 Se 0. 8 emitter layer 25 (electron concentration = 5 × 10 17 / cm 3 , impurity = Cl, film thickness = 0.15
[mu] m) and Zn 0. 9 Mg 0. 1 S 0. 2 Se 0. 8 polycrystalline layer 26 (film thickness = 0.15 [mu] m), then n-type ZnS 0. 06 Se 0. 94 contact layer 27 (electron concentration = 5 × 10 18 / cm 3 , the impurity = Cl, thickness = 0.2 [mu] m) and ZnS 0. 06 Se 0. 94 polycrystalline layer 28 (film thickness = 0.2 [mu] m) was formed by regrowth respectively (Fig. 4). At this time, it was confirmed from the results of electric resistance measurement that the polycrystalline layers 22, 24, 26 and 28 of the II-VI group compound semiconductor had high resistance.
【００２８】その後、試料をＭＢＥ装置から取り出し
て、ホトリソグラフィー及びエッチングにより、ベース
電極形成領域のエミッタ層２５、多結晶層２６、コンタ
クト層２７、多結晶層２８を除去し、この領域のベース
層２３及び多結晶層２４の表面を露出させた。最後に、
ｐ型電極１３をベース領域に、ｎ型電極１４をエミッタ
及びコレクタ領域に形成し、ＺｎＭｇＳＳｅ／ＺｎＳＳ
ｅヘテロ接合バイポーラトランジスタを作製した（図
５）。なお、多結晶層２４が高抵抗であることから、ｐ
型電極１３は単結晶のベース層２３に幅１μｍ以上接触
させて形成した。Thereafter, the sample is taken out from the MBE apparatus, and the emitter layer 25, the polycrystal layer 26, the contact layer 27 and the polycrystal layer 28 in the base electrode formation region are removed by photolithography and etching, and the base layer in this region is removed. The surfaces of 23 and the polycrystalline layer 24 were exposed. Finally,
The p-type electrode 13 is formed in the base region, the n-type electrode 14 is formed in the emitter and collector regions, and ZnMgSSe / ZnSS is formed.
An e-heterojunction bipolar transistor was produced (FIG. 5). Since the polycrystalline layer 24 has high resistance, p
The mold electrode 13 was formed in contact with the single crystal base layer 23 with a width of 1 μm or more.
【００２９】本実施例によれば、II−VI族化合物半導体
単結晶を、その結晶性を劣化させずに、高抵抗のII−VI
族化合物半導体多結晶と同時に形成できる効果がある。
また、本実施例により作製されたII−VI族化合物半導体
ヘテロ接合バイポーラトランジスタは、高抵抗のII−VI
族化合物半導体多結晶層２２が完全に空乏化するため
に、全面がII−VI族化合物半導体単結晶からなる従来型
II−VI族化合物半導体ヘテロ接合バイポーラトランジス
タに比較して、ベース・コレクタ間容量が３０％低減す
る効果も見られた。According to the present embodiment, the II-VI group compound semiconductor single crystal is formed into a high resistance II-VI compound without deteriorating its crystallinity.
There is an effect that it can be formed simultaneously with the group compound semiconductor polycrystal.
In addition, the II-VI group compound semiconductor heterojunction bipolar transistor manufactured by this example has a high resistance of II-VI.
In order to completely deplete the group-group compound semiconductor polycrystal layer 22, a conventional type in which the entire surface is made of a group II-VI compound semiconductor single crystal
Compared to the II-VI group compound semiconductor heterojunction bipolar transistor, the effect of reducing the base-collector capacitance by 30% was also observed.
【００３０】なお、II−VI族化合物半導体混晶の組成
は、本実施例の通りでなくてもよいのはもちろんであ
る。また、基板にはｎ型ＧａＡｓを用いたが、ｐ型Ｇａ
Ａｓ基板や、ＩｎＰ、ＧａＰ、Ｓｉ、ＺｎＳｅ等他の半
導体基板を用いても同様に実施できる。It is needless to say that the composition of the II-VI group compound semiconductor mixed crystal may not be the same as that in this embodiment. Although n-type GaAs was used for the substrate, p-type Ga was used.
The same operation can be performed using an As substrate or another semiconductor substrate such as InP, GaP, Si or ZnSe.
【００３１】＜実施例５＞実施例４におけるＳｅ膜６の
代わりにＳ膜（膜厚２ｎｍ）を表面保護膜として用い
た。Ｓ膜もＳｅ膜と同様に１２０℃以上の加熱により蒸
発し、実施例４と同様に良質のII−VI族化合物半導体単
結晶をII−VI族化合物半導体多結晶と同時に形成するこ
とができた。また、作製されたII−VI族化合物半導体ヘ
テロ接合バイポーラトランジスタの特性も実施例４と同
様であった。Example 5 An S film (film thickness 2 nm) was used as a surface protective film instead of the Se film 6 in Example 4. Like the Se film, the S film was also evaporated by heating at 120 ° C. or higher, and a good quality II-VI group compound semiconductor single crystal could be formed simultaneously with the II-VI compound semiconductor polycrystal as in Example 4. . The characteristics of the manufactured II-VI group compound semiconductor heterojunction bipolar transistor were similar to those of Example 4.
【００３２】[0032]
【発明の効果】本発明の化合物半導体の形成方法によれ
ば、II−VI族化合物半導体酸化物層を用いるため、II−
VI族化合物半導体の加熱や絶縁膜との熱膨張係数差に起
因した点欠陥や線欠陥の発生が極めて少なく、良質のII
−VI族化合物半導体単結晶をII−VI族化合物半導体多結
晶と同時に形成できる。また、本発明の化合物半導体装
置によれば、使用中の転位の発生が極めて少なく、その
特性を長期間維持できる。According to the method for forming a compound semiconductor of the present invention, since the II-VI group compound semiconductor oxide layer is used,
Very few point defects and line defects due to heating of Group VI compound semiconductors and differences in thermal expansion coefficient with insulating film
A group-VI compound semiconductor single crystal can be formed simultaneously with a group II-VI compound semiconductor polycrystal. Further, according to the compound semiconductor device of the present invention, the occurrence of dislocations during use is extremely small, and its characteristics can be maintained for a long period of time.
【図１】本発明の実施例１のII−VI族化合物半導体レー
ザの製造工程を示す縦断面構造図である。FIG. 1 is a vertical sectional structural view showing a manufacturing process of a II-VI group compound semiconductor laser according to a first embodiment of the present invention.
【図２】本発明の実施例２のII−VI族化合物半導体ヘテ
ロ接合バイポーラトランジスタの製造工程を示す縦断面
構造図である。FIG. 2 is a vertical sectional structural view showing a manufacturing process of a II-VI group compound semiconductor heterojunction bipolar transistor of Example 2 of the present invention.
【図３】本発明の実施例２のII−VI族化合物半導体ヘテ
ロ接合バイポーラトランジスタの製造工程を示す縦断面
構造図である。FIG. 3 is a vertical sectional structural view showing a manufacturing process of a II-VI group compound semiconductor heterojunction bipolar transistor of Example 2 of the present invention.
【図４】本発明の実施例２のII−VI族化合物半導体ヘテ
ロ接合バイポーラトランジスタの製造工程を示す縦断面
構造図である。FIG. 4 is a vertical sectional structural view showing a manufacturing process of a II-VI group compound semiconductor heterojunction bipolar transistor of Example 2 of the present invention.
【図５】本発明の実施例２のII−VI族化合物半導体ヘテ
ロ接合バイポーラトランジスタの製造工程を示す縦断面
構造図である。FIG. 5 is a vertical sectional structural view showing a manufacturing process of the II-VI group compound semiconductor heterojunction bipolar transistor of Example 2 of the present invention.
【図６】従来技術によるIII−Ｖ族化合物半導体レーザ
の製造工程を示す縦断面構造図である。FIG. 6 is a vertical sectional structural view showing a manufacturing process of a III-V compound semiconductor laser according to a conventional technique.
１…ｎ型ＧａＡｓ基板 ２…バッファ層 ２’…サブコレクタ層 ３、５、９…クラッド層 ４…活性層 ６…Ｓｅ層 ７…ホトレジスト ８…酸化物層 １０、１２、２２、２４、２６、２８…多結晶層 １１、２７…コンタクト層 １３…ｐ型電極 １４…ｎ型電極 ２１…コレクタ層 ２３…ベース層 ２５…エミッタ層 ３１…ｎ型ＡｌＧａＡｓ層 ３２…ｎ型ＧａＡｓ層 ３３…ｐ型ＡｌＧａＡｓ層 ３４…ＳｉＯ2パタン ３５…ｐ型単結晶ＡｌＧａＡｓ層 ３６…ＡｌＧａＡｓ多結晶層 ３７…ｐ型単結晶ＧａＡｓ層 ３８…ＧａＡｓ多結晶層DESCRIPTION OF SYMBOLS 1 ... N-type GaAs substrate 2 ... Buffer layer 2 '... Subcollector layer 3, 5, 9 ... Clad layer 4 ... Active layer 6 ... Se layer 7 ... Photoresist 8 ... Oxide layer 10, 12, 22, 24, 26, 28 ... Polycrystalline layer 11, 27 ... Contact layer 13 ... P-type electrode 14 ... N-type electrode 21 ... Collector layer 23 ... Base layer 25 ... Emitter layer 31 ... N-type AlGaAs layer 32 ... N-type GaAs layer 33 ... P-type AlGaAs Layer 34 ... SiO 2 pattern 35 ... p type single crystal AlGaAs layer 36 ... AlGaAs polycrystal layer 37 ... p type single crystal GaAs layer 38 ... GaAs polycrystal layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 河田 雅彦 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 大家 彰 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Masahiko Kawada 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory of Hitachi, Ltd. (72) Inventor Akira 1-280 Higashi-Kengokubo, Kokubunji-shi, Tokyo Hitachi Ltd. Central Research Center
Claims (11)
る第１の工程、該化合物半導体単結晶層の所望の部分
に、II−VI族化合物半導体の酸化物からなるマスクを形
成する第２の工程、上記マスクの開口部の上記化合物半
導体単結晶層上に、II−VI族化合物半導体単結晶を、上
記マスク上に、II−VI族化合物半導体多結晶を同時に形
成する第３の工程を有することを特徴とする化合物半導
体の形成方法。1. A first step of forming a compound semiconductor single crystal layer on a substrate, and a step of forming a mask made of an oxide of a II-VI group compound semiconductor on a desired portion of the compound semiconductor single crystal layer. Second step, a third step of simultaneously forming a II-VI group compound semiconductor single crystal on the compound semiconductor single crystal layer in the opening of the mask and a II-VI group compound semiconductor polycrystal on the mask A method for forming a compound semiconductor, comprising:
おいて、上記化合物半導体単結晶層は、II−VI族化合物
半導体単結晶層であることを特徴とする化合物半導体の
形成方法。2. The method for forming a compound semiconductor according to claim 1, wherein the compound semiconductor single crystal layer is a II-VI group compound semiconductor single crystal layer.
おいて、上記酸化物からなるマスクの形成は、上記II−
VI族化合物半導体単結晶層の所望の部分の表面部分を酸
化して行われることを特徴とする化合物半導体の形成方
法。3. The method for forming a compound semiconductor according to claim 2, wherein the mask made of the oxide is formed according to II-
A method for forming a compound semiconductor, which is performed by oxidizing a surface portion of a desired portion of a Group VI compound semiconductor single crystal layer.
おいて、上記第１の工程の後に、上記II−VI族化合物半
導体単結晶層上に表面保護膜を形成する工程を有し、上
記第２の工程は、所望の部分の該表面保護膜を除去し、
該所望の部分の上記II−VI族化合物半導体単結晶層の表
面部分を酸化して、上記酸化物からなるマスクの形成を
行うことを特徴とする化合物半導体の形成方法。4. The method for forming a compound semiconductor according to claim 2, further comprising a step of forming a surface protective film on the II-VI group compound semiconductor single crystal layer after the first step. The second step is to remove the desired surface protection film,
A method for forming a compound semiconductor, which comprises oxidizing a surface portion of the desired II-VI group compound semiconductor single crystal layer to form a mask made of the oxide.
おいて、上記表面保護膜は、１５０℃以下の温度で蒸発
する非晶質体からなることを特徴とする化合物半導体の
形成方法。5. The method for forming a compound semiconductor according to claim 4, wherein the surface protective film is made of an amorphous material that evaporates at a temperature of 150 ° C. or lower.
おいて、上記１５０℃以下の温度で蒸発する非晶質体
は、Ｓ及びＳｅからなる群から選ばれた少なくとも一種
の物質であることを特徴とする化合物半導体の形成方
法。6. The method for forming a compound semiconductor according to claim 5, wherein the amorphous substance that evaporates at a temperature of 150 ° C. or lower is at least one substance selected from the group consisting of S and Se. A method for forming a characteristic compound semiconductor.
物半導体の形成方法において、上記表面保護膜の厚さ
は、１ｎｍから１０ｎｍの範囲であることを特徴とする
化合物半導体の形成方法。7. The method for forming a compound semiconductor according to claim 4, wherein the thickness of the surface protective film is in the range of 1 nm to 10 nm. .
物半導体の形成方法において、上記表面保護膜の除去
は、１５０℃以下の加熱により行うことを特徴とする化
合物半導体の形成方法。8. The method for forming a compound semiconductor according to claim 4, wherein the surface protective film is removed by heating at 150 ° C. or lower.
物半導体の形成方法において、上記II−VI族化合物半導
体単結晶と上記II−VI族化合物半導体多結晶の形成は、
分子線エピタキシー法により行うことを特徴とする化合
物半導体の形成方法。9. The method of forming a compound semiconductor according to claim 1, wherein the II-VI group compound semiconductor single crystal and the II-VI group compound semiconductor polycrystal are formed.
A method for forming a compound semiconductor, which is performed by a molecular beam epitaxy method.
合物半導体の形成方法より製造されたII−VI族化合物半
導体と、上記II−VI族化合物半導体単結晶の少なくとも
１部に設けられた化合物半導体素子とからなることを特
徴とする化合物半導体装置。10. A II-VI group compound semiconductor manufactured by the method for forming a compound semiconductor according to claim 1, and at least a part of the II-VI group compound semiconductor single crystal. And a compound semiconductor element.
導体単結晶層と、該II−VI族化合物半導体単結晶層の所
望の領域の上に設けられたII−VI族化合物半導体の酸化
物からなるマスクと、該マスク上に設けられたII−VI族
化合物半導体多結晶と、上記マスクの開口部の上記II−
VI族化合物半導体単結晶層上に設けられたII−VI族化合
物半導体のエピタキシャル層と、該エピタキシャル層の
少なくとも１部に設けられた化合物半導体素子とからな
ることを特徴とする化合物半導体装置。11. A II-VI group compound semiconductor single crystal layer provided on a substrate, and a II-VI group compound semiconductor provided on a desired region of the II-VI group compound semiconductor single crystal layer. A mask made of an oxide, a II-VI group compound semiconductor polycrystal provided on the mask, and the II-of the opening of the mask.
A compound semiconductor device comprising: an II-VI group compound semiconductor epitaxial layer provided on a Group VI compound semiconductor single crystal layer; and a compound semiconductor element provided on at least a part of the epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19540294A JPH0864536A (en) | 1994-08-19 | 1994-08-19 | Forming method of compound semiconductor and compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19540294A JPH0864536A (en) | 1994-08-19 | 1994-08-19 | Forming method of compound semiconductor and compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864536A true JPH0864536A (en) | 1996-03-08 |
Family
ID=16340527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19540294A Pending JPH0864536A (en) | 1994-08-19 | 1994-08-19 | Forming method of compound semiconductor and compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864536A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019527917A (en) * | 2017-02-07 | 2019-10-03 | エルジー・ケム・リミテッド | Manufacturing method of secondary battery electrode suitable for long life |
-
1994
- 1994-08-19 JP JP19540294A patent/JPH0864536A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019527917A (en) * | 2017-02-07 | 2019-10-03 | エルジー・ケム・リミテッド | Manufacturing method of secondary battery electrode suitable for long life |
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