JP2527227B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2527227B2 JP2527227B2 JP1010152A JP1015289A JP2527227B2 JP 2527227 B2 JP2527227 B2 JP 2527227B2 JP 1010152 A JP1010152 A JP 1010152A JP 1015289 A JP1015289 A JP 1015289A JP 2527227 B2 JP2527227 B2 JP 2527227B2
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- Prior art keywords
- semiconductor layer
- film
- gaas
- semiconductor
- substrate
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、基板半導体と格子定数の異なる半導体の
エピタキシ膜上に半導体素子を形成してなる半導体装置
及びその製造方法に関し、特に装置の性能向上に関する
ものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device in which a semiconductor element is formed on an epitaxy film of a semiconductor having a lattice constant different from that of a substrate semiconductor, and a manufacturing method thereof, and particularly, the performance of the device. It is about improvement.
現在最も注目されているヘテロエピタキシ膜（互いに
格子定数の異なる半導体間でのエピタキシ膜）として
は、Si基板上へ成長したGaAs膜があり、Si素子とGaAs素
子とを同一基板上に形成し、Si素子よりも更に高速でか
つSiと同等の集積度をもたせたICの開発、又Si上にGaAs
太陽電池を作製し、GaAs上の太陽電池より軽量化するこ
とが活発に研究されている。As a hetero-epitaxy film (epitaxy film between semiconductors having different lattice constants) which is currently receiving the most attention, there is a GaAs film grown on a Si substrate, and a Si element and a GaAs element are formed on the same substrate. Development of an IC that is even faster than Si devices and has the same degree of integration as Si, and GaAs on Si
Fabrication of solar cells and making them lighter than solar cells on GaAs are being actively studied.
以下、Si基板上のGaAs膜を例にとり、従来のヘテロ接
合エピを用いた半導体装置について第３図を用いて説明
する。A conventional semiconductor device using a heterojunction epi will be described below with reference to FIG. 3 by taking a GaAs film on a Si substrate as an example.
通常、SiとGaAsとは格子定数（Siを基準として４％異
なる）、並びに熱膨張係数（SiがGaAsの約４倍大きい）
が大きく異なり、Si基板上にGaAsを成長した場合、それ
らの差により結晶欠陥がGaAs中に存在する。これらの結
晶欠陥を低減するために、通常は第３図に示す如く、Si
基板１とGaAs膜６との間に、結晶欠陥がGaAs膜６中へ侵
入するのを防ぐためのGaAs/AlGaAsもしくはGaAs/InGaAs
等により超格子層19を挿入している。現状では上記超格
子を導入し、かつ成長後高温アニールすることにより、
最も良いGaAs結晶が得られている。Usually, Si and GaAs have lattice constants (4% different from Si) and thermal expansion coefficient (Si is about 4 times larger than GaAs).
, And when GaAs is grown on a Si substrate, crystal defects exist in GaAs due to the difference. In order to reduce these crystal defects, as shown in FIG.
GaAs / AlGaAs or GaAs / InGaAs for preventing crystal defects from penetrating into the GaAs film 6 between the substrate 1 and the GaAs film 6.
Etc., the superlattice layer 19 is inserted. At present, by introducing the above superlattice and performing high temperature annealing after growth,
The best GaAs crystals have been obtained.
しかしながら、それでも従来のヘテロエピ膜で結晶欠
陥密度が106cm-2と多く、ヘテロエピ膜を用いた半導体
装置を作製する場合、例えばSi基板上にGaAs膜を成長さ
せて光学的素子を形成する場合、実使用上、このヘテロ
エピ膜の結晶欠陥密度を103cm-2以下にする必要があ
り、更に大幅な結晶欠陥の低減化を必要とするという問
題点があった。However, the conventional heteroepitaxial film still has a high crystal defect density of 10 6 cm -2, and when manufacturing a semiconductor device using the heteroepitaxial film, for example, when growing a GaAs film on a Si substrate to form an optical element. However, in practical use, the crystal defect density of this hetero-epitaxial film needs to be 10 3 cm -2 or less, and there is a problem that it is necessary to significantly reduce the crystal defects.
本発明は上記問題点を解決するためになされたもの
で、Si基板上に成長されたGaAs膜等、基板半導体と格子
定数の異なる半導体のエピ膜の結晶欠陥を大幅に減少
し、実使用上充分な特性を有するエピ膜を用いた半導体
装置及びその製造方法を提供することを目的とする。The present invention has been made in order to solve the above-mentioned problems, and significantly reduces crystal defects in an epitaxial film of a semiconductor having a lattice constant different from that of a substrate semiconductor, such as a GaAs film grown on a Si substrate, in practical use. It is an object of the present invention to provide a semiconductor device using an epi film having sufficient characteristics and a method for manufacturing the semiconductor device.
本発明に係る半導体装置及びその製造方法は、Si等の
第１の半導体基板主面上の所定の領域にのみ第１の半導
体基板と格子定数の異なるGaAs等の第２の半導体層を選
択的に成長させ、第２の半導体層を形成した領域下の第
１の半導体基板を選択的にエッチングし、露出された第
２の半導体層の裏面へ第２の半導体層と同一あるいは第
２の半導体層と格子整合する物質である第３の半導体層
を成長させ、しかる後に第２の半導体層を除去して第３
の半導体層を露出させ、この露出面に素子を形成するよ
うにしたものである。A semiconductor device and a method of manufacturing the same according to the present invention selectively select a second semiconductor layer such as GaAs having a lattice constant different from that of the first semiconductor substrate only in a predetermined region on the main surface of the first semiconductor substrate such as Si. And selectively etching the first semiconductor substrate below the region where the second semiconductor layer is formed, to the back surface of the exposed second semiconductor layer, which is the same as or different from the second semiconductor layer. A third semiconductor layer, which is a material lattice-matched to the layer, is grown, and then the second semiconductor layer is removed to remove the third semiconductor layer.
The semiconductor layer is exposed, and the element is formed on the exposed surface.
本発明においては、下地のSi等第１の半導体基板上の
所定領域に形成されたGaAs等の第２の半導体層下の第１
の半導体基板を選択的に除去し、露出された第２の半導
体層上に第２の半導体層と同一もしくは第２の半導体層
と格子整合できる物質である第３の半導体層を形成する
ことにより、この第３の半導体層は下地の第１の半導体
基板の影響をほとんど受けることがないので格子定数の
差に起因する格子欠陥をほとんど含まないホモエピ膜と
同等の結晶性を有し、この第３の半導体層上に素子を作
成することにより、基板と格子定数の異なるエピ膜上に
高性能素子を形成することができる。In the present invention, the first semiconductor under the second semiconductor layer such as GaAs formed in a predetermined region on the first semiconductor substrate such as the underlying Si.
By selectively removing the semiconductor substrate and forming a third semiconductor layer on the exposed second semiconductor layer, the third semiconductor layer being the same material as the second semiconductor layer or a material that can be lattice-matched with the second semiconductor layer. Since this third semiconductor layer is hardly affected by the underlying first semiconductor substrate, it has crystallinity equivalent to that of a homoepitaxial film containing almost no lattice defects due to the difference in lattice constant. By forming an element on the semiconductor layer of No. 3, a high performance element can be formed on the epi film having a lattice constant different from that of the substrate.
以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による半導体装置の製造フ
ローを示すものであり、図において、１はSi基板、2,3,
4はそれぞれMOSデバイスのソース，ドレイン，ゲート、
５はSiO2/SiN膜、6,9,10は単結晶GaAs膜、７は多結晶Ga
As膜、８はSi基板１が選択的にエッチングされたエッチ
ング孔、11,12,13はそれぞれGaAsFETのソース，ゲー
ト，ドレイン、14はSiN膜、15は層間絶縁膜、16は配線
金属である。FIG. 1 shows a manufacturing flow of a semiconductor device according to an embodiment of the present invention, in which 1 is a Si substrate, 2, 3,
4 is the source, drain, gate of the MOS device,
5 is a SiO 2 / SiN film, 6, 9 and 10 are single crystal GaAs films, and 7 is polycrystalline Ga.
As film, 8 is an etching hole in which the Si substrate 1 is selectively etched, 11, 12, 13 are sources, gates and drains of GaAs FETs, 14 is a SiN film, 15 is an interlayer insulating film, and 16 is a wiring metal. .
第１図（ａ）に示す如く、Si基板１上に所定の領域に
選択的にMOSデバイスのソース2,ドレイン3,ポリSiゲー
ト4,及びSiO2/SiN膜５を形成する。続いて、残された領
域のSi基板１を必要最小限エッチングし、全面にGaAs膜
をMBE,MOCVD、もしくは分子線源としてガスを用いるガ
スMBEにより成長させ、写真製版とエッチングによりMOS
デバイス上のGaAs膜を取り除く。この結果、同図（ａ）
の如く、単結晶GaAs膜６とその周囲のSiO2/SiN膜５上の
多結晶GaAs膜７が残される。続いて、単結晶GaAs膜６下
のSi基板１を選択的にエッチングしてエッチング孔８を
形成し、単結晶GaAs膜６の裏面を露出させ、その露出し
た面にFET用GaAs膜を結晶成長させる。この２回目のGaA
s膜成長後の断面図が同図（ｃ）であり、露出された単
結晶GaAs膜６の裏面上には格子不整合のない良質なGaAs
FET用単結晶GaAs膜９が成長し、その他のSi基板１面上
には格子不整合による格子欠陥の多いGaAs膜10が成長さ
れる。続いて、同図（ｄ）に示す如く、１回目に成長し
た単結晶GaAs膜６及び多結晶GaAs膜７をエッチング除去
する。露出されたGaAsFET用GaAs膜９上にソース電極11,
ドレイン電極13,ゲート電極12を形成し、更にSiN膜14を
形成してGaAsFETを作製し、続いて配線用絶縁膜15を全
面にデポする（同図（ｅ））。最後に、SiMOSデバイス
とGaAsFETとを連結するための配線16を形成して、製造
工程を完了する（同図（ｆ））。As shown in FIG. 1A, a source 2, a drain 3, a poly Si gate 4, and a SiO 2 / SiN film 5 of a MOS device are selectively formed on a Si substrate 1 in predetermined regions. Then, the Si substrate 1 in the remaining region is etched to the minimum required, and a GaAs film is grown on the entire surface by MBE, MOCVD or a gas MBE using a gas as a molecular beam source, and MOS is formed by photoengraving and etching.
Remove the GaAs film on the device. As a result, the figure (a)
As described above, the single crystal GaAs film 6 and the polycrystalline GaAs film 7 on the SiO 2 / SiN film 5 around it are left. Subsequently, the Si substrate 1 under the single crystal GaAs film 6 is selectively etched to form an etching hole 8 to expose the back surface of the single crystal GaAs film 6, and the GaAs film for FET is crystal-grown on the exposed surface. Let This second GaA
A cross-sectional view after the s film is grown is shown in FIG. 7C, and a good quality GaAs with no lattice mismatch is formed on the back surface of the exposed single crystal GaAs film 6.
The single crystal GaAs film 9 for FET is grown, and the GaAs film 10 having many lattice defects due to lattice mismatch is grown on the other surface of the Si substrate 1. Subsequently, as shown in FIG. 3D, the single crystal GaAs film 6 and the polycrystalline GaAs film 7 grown for the first time are removed by etching. The source electrode 11, on the exposed GaAs film 9 for GaAs FET,
The drain electrode 13 and the gate electrode 12 are formed, and the SiN film 14 is further formed to manufacture a GaAs FET, and subsequently, the wiring insulating film 15 is deposited on the entire surface (FIG. 8E). Finally, the wiring 16 for connecting the SiMOS device and the GaAs FET is formed, and the manufacturing process is completed ((f) in the same figure).
このようにして得られた半導体装置のうち、ゲート長
0.5μm,全ゲート幅200μｍのGaAsFET素子は、相互コン
ダクタンスが50mSと、通常のGaAs基板上に成長したGaAs
膜上のGaAsFETと同等の性能を示した。Of the semiconductor devices thus obtained, the gate length
The GaAsFET device with 0.5 μm and total gate width of 200 μm has a transconductance of 50 mS and GaAs grown on a normal GaAs substrate.
It showed the same performance as the GaAs FET on the film.
このように、本実施例によれば、Si基板１上に部分的
に成長されたGaAs膜６下のSi基板１を選択エッチングし
て露出されたGaAs膜６上に成長したGaAs膜９は、格子定
数及び熱膨張係数の差に起因する結晶欠陥の導入を大幅
に低減され、このGaAs膜９上にGaAs素子を形成し、その
他のSi基板１上にSiデバイスを形成することにより、実
使用に充分な特性を有するGaAs及びSiデバイスをSi基板
１に同時に形成することができ、高速演算・大容量メモ
リ機能をもつ新しい半導体装置を実現できる。又、最初
に形成したSi基板１主面側のGaAs膜６はSi素子形成時の
種々の汚染が導入される可能性が高く、本実施例ではこ
のSi基板１主面側のGaAs膜６を除去した後に露出される
清浄な表面をもつGaAs膜９表面上に素子を作製するの
で、汚染の少ない高性能素子を形成することができる。Thus, according to this embodiment, the GaAs film 9 grown on the GaAs film 6 exposed by selective etching of the Si substrate 1 under the GaAs film 6 partially grown on the Si substrate 1 is The introduction of crystal defects due to the difference in the lattice constant and the coefficient of thermal expansion is greatly reduced, and a GaAs element is formed on this GaAs film 9 and an Si device is formed on the other Si substrate 1 for practical use. GaAs and Si devices having sufficient characteristics can be simultaneously formed on the Si substrate 1, and a new semiconductor device having a high-speed operation and large-capacity memory function can be realized. Further, the GaAs film 6 on the main surface side of the Si substrate 1 formed first has a high possibility of introducing various contaminations during the formation of Si elements. In this embodiment, the GaAs film 6 on the main surface side of the Si substrate 1 is Since the element is formed on the surface of the GaAs film 9 having a clean surface which is exposed after the removal, a high-performance element with less contamination can be formed.
尚、GaAs太陽電池とSiデバイスとを結合したい場合に
は、GaAsFET用エピ膜９の代りに太陽電池用のエピ膜を
形成することにより、容易に実現できる。Incidentally, when it is desired to combine the GaAs solar cell and the Si device, it can be easily realized by forming an epi film for the solar cell instead of the epi film 9 for the GaAs FET.
又、共振器端面を露出させる必要のある半導体レーザ
とSiデバイスとを結合することも可能である。すなわ
ち、第１図（ｄ）の工程迄を完了した後に、第２図に示
す如く、まずGaAs膜９領域の所定の領域のみを残すべく
SiN膜17によりパターニングする（第２図（ｂ））。続
いて、SiN膜17及びSiO2/SiN膜５上には成長せず、GaAs
膜９上の露出された部分のみに選択成長する成長条件を
用いて、MOCVDもしくはガスMBEによりGaAs膜９と格子整
合できる半導体レーザ用エピ膜18を形成する（同図
（ｃ））。更にSiN膜17でカバーされた領域のGaAs膜９
領域上に半導体レーザをドライブするGaAsFETを形成
し、ドライバー回路とSiデバイスを結合する。これによ
り高速大容量光ICが実現できる。It is also possible to combine a semiconductor laser that requires exposure of the cavity end face with a Si device. That is, after completing the steps of FIG. 1 (d), first, as shown in FIG. 2, only a predetermined region of the GaAs film 9 region should be left.
Patterning is performed with the SiN film 17 (FIG. 2B). Subsequently, GaAs was not grown on the SiN film 17 and the SiO 2 / SiN film 5, and
An epi film 18 for a semiconductor laser that can be lattice-matched with the GaAs film 9 is formed by MOCVD or gas MBE under the growth condition that selectively grows only on the exposed portion on the film 9 (FIG. 7C). Further, the GaAs film 9 in the area covered by the SiN film 17
A GaAs FET that drives a semiconductor laser is formed on the area, and the driver circuit and the Si device are coupled to each other. As a result, a high-speed, large-capacity optical IC can be realized.
又、上記実施例では全てSiとGaAsを例にとり記述した
が、本発明は他の互いに格子定数の異なる材料間に適用
できることは言うまでもない。例えば、InP−GaAs,Si−
InP,Si−InXGa1-XAS,SI−InXGa1-XAsYP1-Yなどの多くの
材料が挙げられる。In the above embodiments, Si and GaAs have been described as examples, but it goes without saying that the present invention can be applied to other materials having different lattice constants. For example, InP-GaAs, Si-
InP, Si-In X Ga 1 -X AS, many materials, such as SI-In X Ga 1-X As Y P 1-Y and the like.
〔発明の効果〕 以上のように、本発明に係る半導体装置及びその製造
方法によれば、Si等の第１の半導体基板主面上に部分的
に格子定数の異なるGaAs膜等の第２の半導体層を成長
後、この第２の半導体層下の第１の半導体基板を選択的
にエッチングして露出された第２の半導体層裏面上に第
２の半導体層と同一もしくは第２の半導体層と格子整合
できる物質である第３の半導体層を成長し、更に第２の
半導体層を除去して第３の半導体層を露出させ、露出し
た第３の半導体層上に半導体素子を形成するようにした
ので、第３の半導体層と第１の半導体基板との格子定数
及び熱膨張係数の差による格子欠陥の導入が大幅に低減
されホモエピタキシと同等の結晶性が実現されたものと
なり、ホモエピタキシによる半導体上の素子と同等の高
性能素子を基板と格子定数の異なるエピ膜を用いて実現
できるとともに、同一エウハ内での異種間材料による素
子の結合をも実現できる効果がある。[Effects of the Invention] As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the second semiconductor such as a GaAs film having a different lattice constant is partially formed on the main surface of the first semiconductor substrate such as Si. After growing the semiconductor layer, the first semiconductor substrate under the second semiconductor layer is selectively etched to expose the back surface of the second semiconductor layer, which is the same as the second semiconductor layer or the second semiconductor layer. A third semiconductor layer, which is a substance that can be lattice-matched with the second semiconductor layer, is grown, the second semiconductor layer is removed to expose the third semiconductor layer, and a semiconductor element is formed on the exposed third semiconductor layer. Therefore, the introduction of lattice defects due to the difference in lattice constant and thermal expansion coefficient between the third semiconductor layer and the first semiconductor substrate is significantly reduced, and the crystallinity equivalent to homoepitaxy is realized. High performance device equivalent to device on semiconductor by epitaxy Can be realized by using an epitaxial film having a different lattice constant from that of the substrate, and the effect of being able to realize the coupling of elements by different kinds of materials in the same EU.
第１図は本発明の第１の実施例による半導体装置の製造
工程断面図、第２図は本発明の第２の実施例による半導
体装置の製造工程断面図、第３図は従来のヘテロエピ膜
を説明するための断面図である。 図中、１はSi基板、２はソース、３はドレイン、４はポ
リSiゲート、５はSiO2/SiN膜、６は単結晶GaAs膜、７は
多結晶GaAs膜、８はエッチ孔、９は格子欠陥の少ない単
結晶GaAs膜、10は格子欠陥の多い単結晶GaAs膜、11はソ
ース、12はゲート、13はドレイン、14はSiN保護膜、15
は層間絶縁膜、16は配線金属、17は選択エピ用SiN保護
膜、18はレーザ用エピ膜、19は超格子層である。 尚、図中、同一符号は同一又は相当部分を示す。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention in a manufacturing step, FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention in a manufacturing step, and FIG. It is a sectional view for explaining. In the figure, 1 is a Si substrate, 2 is a source, 3 is a drain, 4 is a poly-Si gate, 5 is a SiO 2 / SiN film, 6 is a single crystal GaAs film, 7 is a polycrystalline GaAs film, 8 is an etch hole, 9 Is a single crystal GaAs film with few lattice defects, 10 is a single crystal GaAs film with many lattice defects, 11 is a source, 12 is a gate, 13 is a drain, 14 is a SiN protective film, 15
Is an interlayer insulating film, 16 is a wiring metal, 17 is a SiN protective film for selective epi, 18 is an epi film for laser, and 19 is a superlattice layer. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (2)
第１の半導体基板と格子定数の異なる第２の半導体層を
選択的に成長させ、該第２の半導体層を形成した領域下
の上記第１の半導体基板を選択的に除去して露出させた
該第２の半導体層の裏面上に、該第２の半導体層と同一
あるいは該第２の半導体層と格子整合する物質である第
３の半導体層を成長させ、しかる後に上記第２の半導体
層を除去して露出させた上記第３の半導体層上に形成さ
れた半導体素子を備えたことを特徴とする半導体装置。1. A second semiconductor layer having a lattice constant different from that of the first semiconductor substrate is selectively grown on a predetermined portion of the main surface of the first semiconductor substrate to form the second semiconductor layer. A material that is the same as the second semiconductor layer or lattice-matched to the second semiconductor layer on the back surface of the second semiconductor layer that is exposed by selectively removing the first semiconductor substrate below the region. And a semiconductor element formed on the third semiconductor layer exposed by removing the second semiconductor layer after the third semiconductor layer is grown.
第１の半導体基板と格子定数の異なる第２の半導体層を
選択的に成長する工程と、 該第２の半導体層を形成した領域下の上記第１の半導体
基板を選択的に除去する工程と、 露出された該第２の半導体層の裏面上に、該第２の半導
体層と同一あるいは該第２の半導体層と格子整合する物
質である第３の半導体層を成長する工程と、 しかる後に上記第２の半導体層を除去して上記第３の半
導体層を露出させる工程と、 該露出させた第３の半導体層上に半導体素子を形成する
工程とを含むことを特徴とする半導体装置の製造方法。2. A step of selectively growing a second semiconductor layer having a lattice constant different from that of the first semiconductor substrate at a predetermined portion on the main surface of the first semiconductor substrate, and the second semiconductor layer being formed. A step of selectively removing the first semiconductor substrate under the formed region; and a step of forming the same semiconductor layer as the second semiconductor layer or the second semiconductor layer on the exposed back surface of the second semiconductor layer. Growing a third semiconductor layer, which is a lattice-matching substance, then removing the second semiconductor layer to expose the third semiconductor layer, and exposing the exposed third semiconductor layer And a step of forming a semiconductor element thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1010152A JP2527227B2 (en) | 1989-01-19 | 1989-01-19 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1010152A JP2527227B2 (en) | 1989-01-19 | 1989-01-19 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02191342A JPH02191342A (en) | 1990-07-27 |
| JP2527227B2 true JP2527227B2 (en) | 1996-08-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1010152A Expired - Fee Related JP2527227B2 (en) | 1989-01-19 | 1989-01-19 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2527227B2 (en) |
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1989
- 1989-01-19 JP JP1010152A patent/JP2527227B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02191342A (en) | 1990-07-27 |
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