JPH0863204A - Power circuit of nonvolatile memory - Google Patents
Power circuit of nonvolatile memoryInfo
- Publication number
- JPH0863204A JPH0863204A JP19925394A JP19925394A JPH0863204A JP H0863204 A JPH0863204 A JP H0863204A JP 19925394 A JP19925394 A JP 19925394A JP 19925394 A JP19925394 A JP 19925394A JP H0863204 A JPH0863204 A JP H0863204A
- Authority
- JP
- Japan
- Prior art keywords
- eeprom
- capacitor
- data
- voltage
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control By Computers (AREA)
- Combined Controls Of Internal Combustion Engines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、エンジンの電子制御装
置に係り、特に電気的にデータの消去及び書き込みが可
能な不揮発性メモリを内蔵した装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic control device for an engine, and more particularly to a device having a non-volatile memory capable of electrically erasing and writing data.
【０００２】[0002]
【従来の技術】従来、特開昭60−211504号公報にあるよ
うに電気的にデータの消去及び書き込みが可能な不揮発
性メモリ（以下EEPROM）を内蔵し、外部装置と通信によ
りその不揮発性メモリにデータの書き込みを行う装置が
発明されている。2. Description of the Related Art Conventionally, as disclosed in JP-A-60-212150, a nonvolatile memory (hereinafter referred to as an EEPROM) capable of electrically erasing and writing data is built in, and the nonvolatile memory is communicated with an external device. There has been invented a device for writing data into a memory.
【０００３】[0003]
【発明が解決しようとする課題】ある種類のEEPROMはデ
ータの書き込みに１０ｍｓ程度の書き込み時間が必要で
あり、書き込み時間中に電源が切れるとデータの書き込
みが正確に行えず書き込んだつもりのデータが書き込ま
れていないことが起こる可能性があった。A certain type of EEPROM requires a write time of about 10 ms to write data, and if the power is turned off during the write time, the data cannot be written correctly and the intended data is written. It could happen that it was not written.
【０００４】[0004]
【課題を解決するための手段】それを防ぐためには、EE
PROMの電源ピンに、書き込み時間中に装置の電源が切れ
ても、書き込み時間中はEEPROMの動作電圧を保持できる
ように電圧を保持するコンデンサとダイオードからなる
電圧保持回路を設ければよい。[Means for solving the problem] To prevent it, EE
A voltage holding circuit composed of a capacitor and a diode for holding the voltage may be provided on the power supply pin of the PROM so that the operating voltage of the EEPROM can be held during the writing time even if the device is powered off during the writing time.
【０００５】[0005]
【作用】上記構成により、装置に電源が供給されている
ときはダイオードをとうして流れる電流によりEEPROMを
動作させると共に上記コンデンサを充電する。装置の電
源が切れた後もそのコンデンサにより、EEPROMにその書
き込み時間以上電源供給することにより、データ書き込
み時間中のタイミングで装置の電源が切れても正常にデ
ータを書き込むことができる。With the above construction, when the power is supplied to the device, the EEPROM is operated by the current flowing through the diode and the capacitor is charged. Even after the power of the device is turned off, the capacitor supplies power to the EEPROM for more than the writing time, so that the data can be written normally even when the power of the device is turned off at the timing during the data writing time.
【０００６】[0006]
【実施例】以下、本発明の一実施例を図面を用いて説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【０００７】図１は本発明の構成を示す回路図である。
１は５Ｖ電源回路であり、バッテリー６から、スイッチ
７を介して入力されるバッテリー電圧をＣＰＵ２やここ
には図示しないＩ／Ｏ ＬＳＩ等に５Ｖの電圧ＶＣＣを
供給する。EEPROM5 はCPU2から信号線９を通してデータ
を書き込み可能な不揮発性メモリで、ＣＰＵ２から書き
込まれたデータをスイッチ７がＯＦＦとなり、装置の電
源が切れた後も記憶しておくことができる。コンデンサ
４はEEPROM5 の書き込み時間１０ｍｓの間はEEPROM5 の
消費電流をコンデンサ４のみで供給できる容量を持つ。
ダイオード３は５Ｖ電源回路１からＶＣＣが供給されて
いるときはEEPROM5 に動作電圧を供給すると共に、コン
デンサ４を充電する電流を供給する。そして、装置の電
源が切れＶＣＣが低下したとき、コンデンサ４の電荷が
ＶＣＣ８側に漏れるのを防ぐものである。FIG. 1 is a circuit diagram showing the configuration of the present invention.
Reference numeral 1 denotes a 5V power supply circuit, which supplies a battery voltage input from a battery 6 through a switch 7 to a CPU 2 or an I / O LSI (not shown) or the like with a voltage VCC of 5V. The EEPROM 5 is a non-volatile memory in which data can be written from the CPU 2 through the signal line 9, and the data written from the CPU 2 can be stored even after the switch 7 is turned off and the device is powered off. The capacitor 4 has such a capacity that the consumption current of the EEPROM 5 can be supplied only by the capacitor 4 while the writing time of the EEPROM 5 is 10 ms.
The diode 3 supplies an operating voltage to the EEPROM 5 and a current for charging the capacitor 4 when VCC is supplied from the 5V power supply circuit 1. Then, when the power of the device is turned off and the VCC drops, the charge of the capacitor 4 is prevented from leaking to the VCC8 side.
【０００８】図２にEEPROM5 への書き込みのタイミング
チャートを示す。FIG. 2 shows a timing chart of writing to the EEPROM 5.
【０００９】ＣＰＵ２はＣＳ信号９ａをＨＩとしてEEPR
OM5 をアクティブとする。そして、ＣＬＯＣＫ信号９ｂ
に同期して、ＣＰＵ２から書き込み動作を指定するコマ
ンドとデータを書き込むアドレスそして書き込むデータ
をEEPROMのＤｉ信号９ｃに送信する。そして、送信終了
後ＣＳ信号９ａをＬＯとするとEEPROM5 は書き込み動作
に入り、最大１０ｍｓの書き込み時間経過後書き込みが
終了する。この書き込み時間１０ｍｓの間はEEPROM5 に
電源を供給しておく必要がある。CPU 2 sets CS signal 9a as HI
Activate OM5. Then, the CLOCK signal 9b
In synchronism with the above, the CPU 2 transmits a command designating a write operation, an address for writing data, and the data to be written to the Di signal 9c of the EEPROM. When the CS signal 9a is set to LO after the end of transmission, the EEPROM 5 starts the write operation, and the write is completed after the write time of 10 ms at the maximum has elapsed. It is necessary to supply power to the EEPROM 5 during this writing time of 10 ms.
【００１０】図４にコンデンサ４及びダイオード３がな
い従来の回路の、EEPROM5 の書き込み時間中にスイッチ
７がＯＦＦされた場合のタイミングチャートを示す。FIG. 4 shows a timing chart of the conventional circuit without the capacitor 4 and the diode 3 when the switch 7 is turned off during the writing time of the EEPROM 5.
【００１１】スイッチＯＦＦから１０ｍｓ以内でＶＣＣ
８はEEPROMの動作電圧以下に低下し、書き込んだつもり
のデータが記憶されなくなる恐れがある。VCC within 10 ms after the switch is turned off
The value of 8 drops below the operating voltage of the EEPROM, and the data intended to be written may not be stored.
【００１２】次に図４に図１の回路でEEPROMの書き込み
時間中にスイッチ７がＯＦＦされた場合のタイミングチ
ャートを示す。Next, FIG. 4 shows a timing chart when the switch 7 is turned off during the writing time of the EEPROM in the circuit of FIG.
【００１３】スイッチ７ＯＦＦ後数ｍｓでＣＰＵ２の電
源ラインＶＣＣ８の電圧は低下するがEEPROM5 の電源ラ
イン１０の電圧はコンデンサ４に充電されていた電圧に
より書き込み時間１０ｍｓ以上EEPROM5 の動作電圧以上
に保たれる。従って、データの書き込みは正常に行われ
たことになる。The voltage of the power supply line VCC8 of the CPU 2 drops a few ms after the switch 7 is turned off, but the voltage of the power supply line 10 of the EEPROM 5 is maintained at the write voltage of 10 ms or more due to the voltage charged in the capacitor 4 or more. . Therefore, the writing of data has been normally performed.
【００１４】[0014]
【発明の効果】EEPROM5 の電源ライン１０にコンデンサ
４とダイオード３からなる電圧保持回路を設けることに
より、装置の電源ＯＦＦががEEPROMの書き込み時間中に
発生してもデータの書き込みは正常に行われ、データの
誤書き込みを防ぐことが出来る。By providing the voltage holding circuit composed of the capacitor 4 and the diode 3 on the power supply line 10 of the EEPROM 5, data can be normally written even if the power supply of the device is turned off during the writing time of the EEPROM. , It is possible to prevent erroneous writing of data.
【図１】本発明実施例装置の電源回路図である。FIG. 1 is a power supply circuit diagram of an apparatus according to an embodiment of the present invention.
【図２】EEPROMの書き込みタイミングチャート図であ
る。FIG. 2 is a writing timing chart of EEPROM.
【図３】本発明の回路のスイッチＯＦＦ時の電源電圧波
形図である。FIG. 3 is a power supply voltage waveform diagram when the switch of the circuit of the present invention is OFF.
【図４】従来の回路のスイッチＯＦＦ時の電源電圧波形
図である。FIG. 4 is a waveform diagram of a power supply voltage when a switch of a conventional circuit is turned off.
１…５Ｖ電源回路、２…ＣＰＵ、３…ダイオード、４…
コンデンサ、５…EEPROM、６…バツテリー、７…スイッ
チ、９…信号線。1 ... 5V power supply circuit, 2 ... CPU, 3 ... diode, 4 ...
Capacitor, 5 ... EEPROM, 6 ... Battery, 7 ... Switch, 9 ... Signal line.
Claims (1)
である不揮発性メモリを実装した電子制御装置におい
て、上記不揮発性メモリの電源にその不揮発性メモリの
書き込み時間はそのコンデンサだけでその不揮発性メモ
リを動作させることが可能な容量のコンデンサとダイオ
ードからなる電圧保持回路をもつことを特徴とする不揮
発性メモリの電源回路。1. An electronic control device having a non-volatile memory capable of electrically erasing and writing data, wherein the power supply of the non-volatile memory requires only the capacitor for the write time of the non-volatile memory. A power supply circuit for a non-volatile memory, having a voltage holding circuit composed of a capacitor having a capacity capable of operating a memory and a diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19925394A JPH0863204A (en) | 1994-08-24 | 1994-08-24 | Power circuit of nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19925394A JPH0863204A (en) | 1994-08-24 | 1994-08-24 | Power circuit of nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0863204A true JPH0863204A (en) | 1996-03-08 |
Family
ID=16404716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19925394A Pending JPH0863204A (en) | 1994-08-24 | 1994-08-24 | Power circuit of nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0863204A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112559398A (en) * | 2019-09-10 | 2021-03-26 | 铠侠股份有限公司 | Memory system and power supply circuit |
-
1994
- 1994-08-24 JP JP19925394A patent/JPH0863204A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112559398A (en) * | 2019-09-10 | 2021-03-26 | 铠侠股份有限公司 | Memory system and power supply circuit |
| CN112559398B (en) * | 2019-09-10 | 2024-04-05 | 铠侠股份有限公司 | Memory system and power supply circuit |
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