JPH084089B2 - IC element and wiring connection method in IC element - Google Patents

IC element and wiring connection method in IC element

Info

Publication number
JPH084089B2
JPH084089B2 JP61303719A JP30371986A JPH084089B2 JP H084089 B2 JPH084089 B2 JP H084089B2 JP 61303719 A JP61303719 A JP 61303719A JP 30371986 A JP30371986 A JP 30371986A JP H084089 B2 JPH084089 B2 JP H084089B2
Authority
JP
Japan
Prior art keywords
wiring
layer
hole
film
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61303719A
Other languages
Japanese (ja)
Other versions
JPS63157438A (en
Inventor
文和 伊藤
朗 嶋瀬
聡 原市
貴彦 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61303719A priority Critical patent/JPH084089B2/en
Priority to US07/134,460 priority patent/US4900695A/en
Publication of JPS63157438A publication Critical patent/JPS63157438A/en
Priority to US07/584,180 priority patent/US6753253B1/en
Publication of JPH084089B2 publication Critical patent/JPH084089B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路（以下ICと呼ぶ）においてデ
バッグ、修正・不良解析等のためにチップ完成後その内
部配線間を接続したIC素子並びにIC素子における配線接
続方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC), an IC element in which internal wirings are connected after completion of a chip for debugging, correction, failure analysis, etc. The present invention relates to a wiring connection method for an IC element.

〔従来の技術〕[Conventional technology]

近年ICの高集積化、微細化に伴ない、開発工程におい
てLSIのチップ内配線の一部を切断したり、接続したり
して不良箇所のデバックや修正を行なうことにより設計
ミス、プロセスミスを発見したり、不良解析を行なって
これをプロセス条件に戻し、製品歩留りを向上させるこ
とがますます重要になってきている。このような目的の
ため従来レーザやイオンビームによりICの配線を切断す
る例が報告されている。In recent years, due to the high integration and miniaturization of ICs, design and process errors can be avoided by debugging or repairing defective parts by cutting or connecting some of the LSI's in-chip wiring during the development process. It is becoming more and more important to discover and perform failure analysis and return it to process conditions to improve product yield. Conventionally, there has been reported an example in which an IC wiring is cut by a laser or an ion beam for such a purpose.

すなわち、第１の従来技術としてはテクノ、ダイジェ
ストオブクレオ81 1981第160頁（Tech Digest of CLE
O′81 1981,p160）「レーザストライブカッティングシ
ィステムフォーアイシーデバッキング（Laser Stripe C
utting System for IC debugging）」があり、これにお
いては、レーザにより配線を切断し、不良箇所のテバッ
クを行なう例が報告されている。更に第２の従来技術と
しては、特願昭58−42126号があり、これには、微細な
配線に対処できるように、液体金属イオン源からのイオ
ンビームを0.5μｍ以下のスポットに集束して配線を切
断したり、穴あけを行ない、またイオンビームでこの穴
に蒸着して上下の配線を接続する技術が示されている。That is, as the first conventional technique, techno, digest of cleo 81 1981, p. 160 (Tech Digest of CLE
O'81 1981, p160) "Laser stripe cutting system for Icy debugging (Laser Stripe C
utting System for IC debugging) ”, in which an example is reported in which the wiring is cut by a laser and the defective portion is tevaced. Further, as a second conventional technique, there is Japanese Patent Application No. 58-42126, in which an ion beam from a liquid metal ion source is focused on a spot of 0.5 μm or less so as to cope with fine wiring. A technique is shown in which the wiring is cut or a hole is formed, and an ion beam is deposited in the hole to connect the upper and lower wirings.

更に第３の従来技術としては、イクステンディッドア
ブストラクトオブ第17コンファレンスオンソリッドステ
ィトデバイシズアンドマティリアル1985第193頁（Exten
ded Abstruct of 17 th Conf.on Solid state Devices
and Material 1985,p193）「ダイレクトライティングオ
ブハイリイコンダクティブモリブデンラインズバイレー
ザーインデューストケミカルベイパーディポジッション
（Direct Writing of Highly Conductive Mo Lines by
Laser Induced CVD）」がある。Furthermore, as a third conventional technique, there is an Extented Abstract of 17th Conference on Solid Stitch Devices and Mattial 1985, page 193 (Exten
ded Abstruct of 17th Conf.on Solid state Devices
and Material 1985, p193) "Direct Writing of Highly Conductive Mo Lines by
Laser Induced CVD).

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記第１の従来技術においては配線の切断の手段のみ
が示され、配線間の接続については何ら手段が示されて
いない。またレーザ加工法を用いる場合（１）加工過程
が熱的なものであり、周囲への熱伝導がありまた蒸発・
噴出などのプロセスを経ることなどのため0.5μｍ以下
の微細な加工を行うことはきわめて困難である。（２）
レーザ光はSiO2,Si2N4などの絶縁膜に吸収されにくく、
このため下層のAlやpoli Siの配線などに吸収され、こ
れが蒸発噴出を行なう際に、上部の絶縁膜を爆発的に吹
飛ばすことにより絶縁膜の加工が行われる。このため絶
縁層が２μｍ以上厚い場合は加工が困難である。また周
辺（周囲，上下層）へのダメージが大きく不良発生の原
因となる。これらの結果から多層配線・微細高集積の配
線の加工は困難である。In the first prior art, only the means for cutting the wiring is shown, and no means is shown for the connection between the wirings. When the laser processing method is used, (1) the processing process is thermal, and there is heat conduction to the surroundings;
It is extremely difficult to perform fine processing of 0.5 μm or less due to a process such as ejection. (2)
Laser light is hard to be absorbed by insulating films such as SiO 2 and Si 2 N 4 ,
Therefore, it is absorbed by the wiring of Al or poli Si of the lower layer, and when this evaporates and ejects, the insulating film on the upper side is explosively blown off to process the insulating film. Therefore, when the insulating layer is thicker than 2 μm, processing is difficult. In addition, damage to the periphery (periphery, upper and lower layers) is large, which causes a defect. From these results, it is difficult to process multi-layer wiring and fine highly integrated wiring.

また、第２の従来技術においては（１）′集束イオン
ビームによる切断および穴あけ、（２）′集束イオンビ
ームを用いた上下配線の接続の手段が示されている。集
束イオンビームによる加工は0.5μｍ以下の加工が可能
であること、どのような材料でもスパッタリングにより
上層から順次容易に加工が行えることなどから、第１の
従来技術における問題点をカバーしている。しかしなが
ら（２）′の配線間の接続の手段については、上下の配
線の接続の手順が示されているのみであり、一つの配線
から別の場所の配線へと接続を行なう手段に関しては何
ら触れられていない。Further, in the second prior art, there are shown (1) means for cutting and drilling with a focused ion beam, and (2) means for connecting upper and lower wirings using a focused ion beam. The processing by the focused ion beam covers the problems in the first prior art because processing of 0.5 μm or less is possible, and any material can be processed easily from the upper layer by sputtering. However, only the procedure for connecting the upper and lower wirings is shown for the means of connection between the wirings in (2) ', and there is no mention of the means for connecting from one wiring to a wiring in another place. Not been.

第３の従来技術においては、M0（CO）６（モリブテン
カルボニル）などの金属を有機化合物のガス中におい
て、紫外のレーザをSiO2をコートしたSi基板上に照射し
て、光熱的（photothermal）あるいは光化学的（photoc
hemical）なレーザ誘起CVDプロセスにより、M0（CO）６
を分解し、基板上にM0などの金属を堆積させて金属配線
を直接に描画形成する方法が示されている。しかしなが
らこの場合、単に絶縁膜の上にM0の配線が形成されたの
みであり、実際のICにおいて保護膜や層間絶縁膜などの
絶縁膜の下部にある配線同志を上部の配線との短絡をお
こすことなく接続する手段については示されていない。In the third conventional technique, a metal such as M 0 (CO) 6 (molybdenum carbonyl) is irradiated in a gas of an organic compound with an ultraviolet laser onto a Si substrate coated with SiO 2 to perform photothermal (photothermal). ) Or photochemical (photoc
(hemical) laser-induced CVD process to produce M 0 (CO) 6
Is disassembled and a metal such as M 0 is deposited on the substrate to directly draw and form metal wiring. However, in this case, the wiring of M 0 is simply formed on the insulating film, and in the actual IC, the wiring under the insulating film such as the protective film or the interlayer insulating film is short-circuited with the wiring above. There is no indication of a means of making a successful connection.

本発明の目的は、ICにおいて保護膜や層間絶縁膜など
の絶縁膜に微細な穴加工ができるようにしてその下部に
ある配線と他の部分とを配線接続して、ICのデバック、
修正、不良解析等が行うことができるようにしたIC素子
並びにIC素子における配線接続方法を提供することにあ
る。The purpose of the present invention is to debug the IC by connecting the wiring underneath and other parts by enabling fine hole processing in the insulating film such as a protective film or an interlayer insulating film in the IC,
An object of the present invention is to provide an IC element and a wiring connection method for the IC element, which enables correction, failure analysis, and the like.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記目的を達成するために、IC素子を、IC
素子の内部の上層の配線層の下に形成した下層配線に電
気的に接続する配線膜をIC素子上に形成し、上層の配線
層の穴の周辺に切欠きを設けて上層の配線層から穴の内
部で下層配線と電気的に接続する部分を切り離して下層
配線と上層の配線層とを電気的に切断した構造とした。
また、本発明は、IC素子の配線形成方法を、IC素子の内
部の上層の配線層の下に形成した下層配線の所望の部分
に電気的に接続する新たな配線膜をIC素子上に付加形成
する方法であって、上層の配線層の上に形成された絶縁
膜に第１のエネルギビームを照射して絶縁膜と上層の配
線層に穴をあけて下層配線の所望の部分を露出させ、材
料ガス雰囲気中で穴の内部とIC素子上に第２のエネルギ
ビームを照射して金属膜を析出させて下層配線の所望の
部分に電気的に接続する配線膜をIC素子上に形成し、上
層の配線層の穴の周辺に切欠きを形成して上層の配線層
から穴の内部で下層配線と電気的に接続する部分を切り
離すことにおり下層配線と上層の配線層とを電気的に切
断することを特徴とする配線形成方法とした。In order to achieve the above object, the present invention provides an IC element,
A wiring film that is electrically connected to the lower wiring formed under the upper wiring layer inside the element is formed on the IC element, and a cutout is provided around the hole in the upper wiring The structure in which the lower wiring and the upper wiring layer are electrically disconnected by cutting off the portion electrically connected to the lower wiring inside the hole.
Further, the present invention adds a new wiring film on the IC element to electrically connect the wiring forming method of the IC element to a desired portion of the lower layer wiring formed under the upper wiring layer inside the IC element. A method of forming, wherein the insulating film formed on the upper wiring layer is irradiated with a first energy beam to form a hole in the insulating film and the upper wiring layer to expose a desired portion of the lower wiring. In the material gas atmosphere, a second energy beam is applied to the inside of the hole and the IC element to deposit a metal film and form a wiring film on the IC element to electrically connect to a desired portion of the lower layer wiring. , A notch is formed around the hole of the upper wiring layer to separate the portion electrically connected to the lower wiring inside the hole from the upper wiring layer by electrically connecting the lower wiring and the upper wiring layer. The wiring forming method is characterized by cutting into pieces.

〔作用〕[Action]

この構成により、穴を大きくしてこの穴内に金属を析
出して埋め込んでこの金属が上層配線と接触したとして
も上層配線と切断することができ、上記大きな穴に埋め
込んだ金属を介して下層の配線との接続を十分に行なう
ことができ、その結果IC素子のデバック、修正、不良解
析等について高信頼度で行なうことができる。ところ
で、具体的には、接続すべき複数の配線の場所を試料か
らの２次電子信号又は２次イオン信号を用いた走査イオ
ン顕微鏡を用いることによって検出し、位置決めや照射
箇所の決定を行なった後、イオンビームを照射しこの部
分の配線の上部の絶縁膜を除去する。この場合レーザで
なく集束したイオンビームを用いているため、0.5μｍ
以下に集束して加工することが十分可能である。また材
料による加工の選択性がないためSiO2,Si3N4などの絶縁
膜も上部から逐次に加工出来、これに穴をあけて下部の
配線を露出させることが出来る。その後金属化合物のガ
スをノズルあるいは配管よりこの真空容器内へ導入し、
試料台を相対的に移動して配線を形成すべき箇所に集束
したイオンビームまたは集光したレーザビームが照射さ
れるようにして、イオンビーム誘起CVDプロセスまたは
レーザCVDプロセスにより金属配線を形成する。その結
果、IC完成後その内部配線間を接続でき、ICのデバッ
ク、修正、不良解析等を行うことができる。With this configuration, even if the hole is enlarged and the metal is deposited and embedded in the hole and the metal comes into contact with the upper layer wiring, it can be cut from the upper layer wiring, and the metal embedded in the large hole can be used to connect the lower layer The connection with the wiring can be sufficiently performed, and as a result, debugging, correction, failure analysis, etc. of the IC element can be performed with high reliability. By the way, specifically, the positions of a plurality of wirings to be connected are detected by using a scanning ion microscope using a secondary electron signal or a secondary ion signal from the sample, and positioning and irradiation position determination are performed. After that, an ion beam is irradiated to remove the insulating film above the wiring in this portion. In this case, a focused ion beam is used instead of a laser, so 0.5 μm
It is fully possible to focus and process below. In addition, since there is no processing selectivity depending on the material, an insulating film such as SiO 2 or Si 3 N 4 can be sequentially processed from the upper portion, and a hole can be formed in the insulating film to expose the lower wiring. After that, the metal compound gas is introduced into this vacuum container through a nozzle or piping,
A metal wiring is formed by an ion beam induced CVD process or a laser CVD process such that a focused ion beam or a focused laser beam is irradiated to a place where a wiring is to be formed by relatively moving the sample stage. As a result, after the IC is completed, the internal wirings can be connected, and the IC can be debugged, corrected, and analyzed for defects.

さらに下部の配線との接続を行うために埋込んだ金属
が、上層の配線と電気的に導通することを避けるため、
埋込み金属と接触している上層配線部分を切欠く方法に
ある。Furthermore, in order to prevent the metal embedded to connect to the wiring in the lower part from electrically connecting with the wiring in the upper layer,
This is a method of notching the upper wiring portion that is in contact with the embedded metal.

〔実施例〕〔Example〕

第１図（ａ）〜（ｂ）は本発明によるICへの接続配線
形成を示す図である。1 (a) and 1 (b) are views showing formation of connection wiring to an IC according to the present invention.

第１図（ｂ）はICチップの断面図であり、図示しない
基板（Siなど）の上に絶縁膜１（SiO2など）があり、そ
の上に配線2a,2b,2c（Alなど）が絶縁膜１をはさんで形
成され、さらに最上部に保護膜（SiO2,Si3N4など）１が
形成されている。FIG. 1 (b) is a sectional view of an IC chip, in which an insulating film 1 (SiO 2 or the like) is provided on a substrate (Si or the like) not shown, and wirings 2a, 2b, 2c (Al or the like) are provided thereon. The insulating film 1 is sandwiched and a protective film (SiO 2 , Si 3 N 4 etc.) 1 is further formed on the uppermost part.

今、下層配線2aと他の図示しない配線とを電気的に接
続したい場合、集束イオンビームにより配線2aの上に絶
縁膜１に穴3a,3bをあけ、配線2aの一部を露出する。そ
の後レーザ誘起CVD等により穴3a,3bに金属４を埋込み、
次いで所望の接続点まで金属配線４を形成する。When it is desired to electrically connect the lower layer wiring 2a to another wiring (not shown), holes 3a and 3b are formed in the insulating film 1 on the wiring 2a by the focused ion beam to expose a part of the wiring 2a. After that, the metal 4 is embedded in the holes 3a and 3b by laser induced CVD or the like,
Next, the metal wiring 4 is formed up to a desired connection point.

ICは、多層配線を採用しており、第一層（最下層）2a
から接続を取出す場合は、上層配線を避けなければなら
ない。第１図（ａ）では第２層2bを避けた位置に穴加工
を行っている。しかし第３層（最上層）2cは通常電源配
線であり第１図（ａ）に示すような幅Ｗが広いため、接
続を取出したい場所を常に第三層からはずれた位置に定
めることは困難である。このためほとんどの場合穴3bを
第三層配線2cを貫通してあけることとなり、この穴にレ
ーザCVD等により金属配線４を形成すると、第一層2aと
第三層2cが短絡してしまう。このため、穴3bの外側に第
１図（ａ）で示す切欠き溝５（幅ｗ）を第三層配線2cの
深さよりやや深めの深さｚで加工し、金属配線４と接触
する部分を、第三層配線2cの他の部分から、電気的に切
離す。この後レーザCVD等による金属配線を、切欠き５
の開口方向へ作成する。The IC uses multi-layer wiring, and the first layer (bottom layer) 2a
When taking out the connection from the upper layer wiring, avoid upper layer wiring. In FIG. 1 (a), holes are drilled at positions avoiding the second layer 2b. However, since the third layer (uppermost layer) 2c is usually a power supply wiring and has a wide width W as shown in FIG. 1 (a), it is difficult to always set the location where the connection is to be taken out of the third layer. Is. Therefore, in most cases, the hole 3b is opened through the third layer wiring 2c, and when the metal wiring 4 is formed in this hole by laser CVD or the like, the first layer 2a and the third layer 2c are short-circuited. Therefore, a portion where the notch groove 5 (width w) shown in FIG. 1 (a) is processed outside the hole 3b with a depth z slightly deeper than the depth of the third layer wiring 2c, and contacts with the metal wiring 4. Are electrically separated from other portions of the third-layer wiring 2c. After this, cut the metal wiring by laser CVD etc. into the notch 5
Create in the opening direction.

第２図に示すように、第三層配線2cが曲がっている場
合は、斜めの直線状に第三層配線を切欠いてもよい。こ
のようにするとイオンビームのスキャンが単純にできる
メリットがある。As shown in FIG. 2, when the third layer wiring 2c is bent, the third layer wiring may be cut out in an oblique straight line shape. This has the advantage that the scanning of the ion beam can be simplified.

また第３図に示すように切欠き溝を円孤状にしてもよ
い。この場合はイオンビームのスキャンはＸ方向、Ｙ方
向の正弦波の重ね合わせで可能であるので、単純である
メリットがある。Further, as shown in FIG. 3, the notch groove may have an arc shape. In this case, the scanning of the ion beam can be performed by superposing the sinusoidal waves in the X direction and the Y direction, so that there is an advantage that it is simple.

第１図（ａ）に示すように第二層配線2bが、切欠き溝
５の下に存在する場合は、更に以下の点に注意しなけれ
ばならない。この様な場合は、ICの高密度化が進んでい
る現在、第二層配線が例えば５〜10μｍのピッチで存在
するので、加工穴3a,3bを第二層配線2bから避けて位置
付けると、切欠き溝が第二層配線の上に重なることがし
ばしば起こり得る。この場合は切欠き溝深さの制御が重
要となる。When the second layer wiring 2b exists below the cutout groove 5 as shown in FIG. 1 (a), the following points should be further noted. In such a case, since the second layer wiring is present at a pitch of, for example, 5 to 10 μm at the present when the density of ICs is increasing, when the processed holes 3a and 3b are positioned away from the second layer wiring 2b, It is often possible for the notch groove to overlay the second layer wiring. In this case, it is important to control the depth of the notch groove.

加工物表面に凸部段差がある場合、集束イオンビーム
によるスパッタエッチングを行うと、段差形状が凹から
凸の方向に向けて進行していくことが実験結果（第４
図，第５図）より示される。これは、よく知られている
ように、被エッチング面へのビームの入射角が40〜70゜
付近であると、入射角が０゜の場合よりも1.5〜２倍の
スパッタ率が得られるためである（第６図）。第５図よ
り、この実験の場合、θが約45゜で段差が進行してい
く。If there is a convex step on the surface of the work piece, the sputter etching with a focused ion beam causes the step shape to progress from the concave to the convex (the fourth result).
Fig. 5). This is because, as is well known, when the incident angle of the beam on the surface to be etched is in the range of 40 to 70 °, the sputter rate is 1.5 to 2 times higher than that in the case where the incident angle is 0 °. (Fig. 6). From Fig. 5, in this experiment, the step progresses when θ is about 45 °.

第１図の加工例をＹ−Ｙ断面で見ると、第７図とな
る。第三層配線2cの段差が保護膜１の段差６を生じるた
め、前述の実験事実より切欠溝５の底面には、段差６の
形状がうつってしまい、第二層配線2bの一部がエッチン
グされる。これのため、第７図のＺ−Ｚ断面である第８
図に示すように、第二層配線2bの断面積が減少し素子と
しての信頼性がそこなわれる、あるいは第二層配線2bを
スパッタエッチした際、切欠溝側壁に配線材料が付着し
（７）、第二層と第三層が短絡する問題が生じる。FIG. 7 is a sectional view taken along line YY of the processing example of FIG. Since the step difference of the third layer wiring 2c causes the step difference 6 of the protective film 1, the shape of the step difference 6 is transferred to the bottom surface of the cutout groove 5 from the above-mentioned experimental fact, and a part of the second layer wiring 2b is etched. To be done. For this reason, the eighth cross section taken along the line ZZ in FIG.
As shown in the figure, the cross-sectional area of the second layer wiring 2b is reduced to impair the reliability as an element, or when the second layer wiring 2b is sputter-etched, the wiring material adheres to the side wall of the cutout groove (7 ), The problem that the second layer and the third layer are short-circuited occurs.

この対策として、第９図に示すように、段差６のエッ
ジ部８を第４図のように２次粒子像でとらえ、（ａ）の
ようにエッジ部より集束イオンビーム９のスキャンを開
始する。第９図（ｂ）に示す加工深さＺ（ｔ）は、イオ
ン電流が十分安定な場合（通常の装置では±５％に入
る）加工時間ｔに比例するので時間ｔの関数で決まる。
また段差６の斜度は成膜プロセスにより同一デバイス
の場合、一定であり、あらかじめ知ることができる。Ｚ
（ｔ）とより集束イオンビームのスキャン位置をΔ
（ｔ）＝Ｚ（ｔ）/tan だけ左方へずらすことによ
り、常にエッジ部８から加工を行うことができる。この
関数は上記の関数だけに固定されるものではない。段差
高Z0−Ｚ（ｔ）になるまで、上記のスキャンスタート位
置のずらしを続けると、加工底面は素子表面と同一レベ
ルになる。このあと通常の加工を行うことにより、第10
図に示すように、底面の平坦な切欠溝５を完成すること
ができる。これにより第三層配線の切欠きによる短絡防
止歩留りを向上できる。As a countermeasure against this, as shown in FIG. 9, the edge portion 8 of the step 6 is captured by the secondary particle image as shown in FIG. 4, and the scanning of the focused ion beam 9 is started from the edge portion as shown in FIG. . The machining depth Z (t) shown in FIG. 9 (b) is proportional to the machining time t when the ion current is sufficiently stable (± 5% in a normal apparatus), and is therefore determined by a function of the time t.
Further, the inclination of the step 6 is constant and can be known in advance in the case of the same device by the film forming process. Z
From (t), the focused ion beam scan position is
By shifting to the left by (t) = Z (t) / tan, machining can always be performed from the edge portion 8. This function is not limited to the above functions. If the shift of the scan start position is continued until the step height becomes Z 0 −Z (t), the processed bottom surface becomes the same level as the element surface. After this, by performing normal processing, the 10th
As shown in the figure, the flat bottom cutout groove 5 can be completed. This can improve the short-circuit prevention yield due to the notch of the third layer wiring.

以上述べたように接続部の穴明け加工、短絡防止の切
欠き加工を行った後、レーザまたはイオンビーム誘起CV
Dにより金属配線４を所望の接続点間に生成することに
より、下層配線2bと他の配線との接続を行う。As described above, laser or ion beam induced CV is performed after drilling the connection and notching to prevent short circuits.
The lower layer wiring 2b and other wiring are connected by generating the metal wiring 4 between desired connection points by D.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明によれば、高集積で多層の
配線のICの異なる場所にある配線間を任意に接続するこ
とができ、これにより、LSIの設計，試作，量産工程に
おいて不良解析を容易に行うことができ、開発工程の短
縮，量産立上り期間の短縮，歩留りの向上が可能となる
効果をする。As described above, according to the present invention, it is possible to arbitrarily connect wirings at different places in a highly integrated and multi-layered wiring IC, which enables failure analysis in LSI design, trial manufacture, and mass production processes. It can be easily performed, and has an effect that the development process can be shortened, the mass production start-up period can be shortened, and the yield can be improved.

【図面の簡単な説明】 第１図は本発明に係るICの配線間の接続法の説明図であ
って（ａ）は正面図、（ｂ）は（ａ）のＸ−Ｘ断面図、
第２図、第３図はそれぞれ本発明の他の実施例を示す
図、第４図は切欠き溝加工の実験結果を示す図、第５図
は第４図のＸ−Ｘ断面図、第６図は第４図の結果を説明
するためのグラフ、第７図は第１図（ａ）のＹ−Ｙ断面
図、第８図は第７図のＺ−Ｚ断面図、第９図は被加工面
の段差をなくす加工方法の実施例を示す図、第10図は前
記実施例による加工結果を示す第１図（ａ）のＹ−Ｙ断
面図である。 １……絶縁膜又は保護膜、2a,2b,2c……配線、3a,3b…
…接続用穴、４……接続用埋込み金属及び配線金属、５
……短絡防止用切欠き溝、６……表面段差、７……スパ
ッタによる側壁付着金属、８……段差のエッジ部、９…
…集束イオンビーム。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view of a method of connecting wirings of an IC according to the present invention, (a) is a front view, (b) is a sectional view taken along line XX of (a),
2 and 3 are views showing another embodiment of the present invention, FIG. 4 is a view showing an experimental result of notch groove machining, and FIG. 5 is a sectional view taken along line XX in FIG. 6 is a graph for explaining the results of FIG. 4, FIG. 7 is a sectional view taken along line YY of FIG. 1 (a), FIG. 8 is a sectional view taken along line ZZ of FIG. 7, and FIG. FIG. 10 is a view showing an embodiment of a processing method for eliminating a step on the surface to be processed, and FIG. 10 is a sectional view taken along the line YY in FIG. 1 (a) showing the processing results according to the embodiment. 1 ... Insulating film or protective film, 2a, 2b, 2c ... Wiring, 3a, 3b ...
… Connection holes, 4… Connection metal and wiring metal, 5
...... Short cut prevention groove, 6 …… Surface step, 7 …… Spitting side wall metal, 8 …… Step edge, 9 ・ ・ ・
… Focused ion beam.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高橋 貴彦 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (56)参考文献 特開 昭61−224342（ＪＰ，Ａ) 特開 昭59−96746（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takahiko Takahashi 2326 Imai, Ome City, Tokyo Inside Hitachi Device Development Center (56) References JP-A 61-224342 (JP, A) JP-A 59- 96746 (JP, A)

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】IC素子の表面から該IC素子の内部で上層の
配線層を横切って該上層の配線層の下に形成した下層配
線に達する穴を介して前記下層配線に電気的に接続する
配線膜を前記IC素子の表面に有し、該IC素子の表面の側
から前記上層の配線層を横切る前記穴の周辺に設けた切
欠きにより前記上層の配線層から前記穴の内部で前記下
層配線と電気的に接続する部分を切り離して前記下層配
線と前記上層の配線層とを電気的に切断したことを特徴
とするIC素子。1. An electrical connection is made from the surface of an IC element to the lower layer wiring through a hole that traverses an upper wiring layer inside the IC element and reaches a lower layer wiring formed under the upper wiring layer. A wiring film is provided on the surface of the IC element, and a notch provided around the hole crossing the wiring layer of the upper layer from the side of the surface of the IC element is cut from the wiring layer of the upper layer to the lower layer inside the hole. An IC device characterized in that the lower wiring and the upper wiring layer are electrically cut by cutting off a portion electrically connected to the wiring. 【請求項２】IC素子の内部の上層の配線層の下に形成し
た下層配線の所望の部分に電気的に接続する新たな配線
膜を前記IC素子上に付加形成する方法であって、前記上
層の配線層の上に形成された絶縁膜に第１のエネルギビ
ームを照射して該絶縁膜と前記上層の配線層に穴をあけ
て前記下層配線の所望の部分を露出させ、材料ガス雰囲
気中で前記穴の内部と前記IC素子上に第２のエネルギビ
ームを照射して金属膜を析出させて前記下層配線の所望
の部分に電気的に接続する配線膜を前記IC素子上に形成
し、前記上層の配線層の前記穴の周辺に切欠きを形成し
て前記上層の配線層から前記穴の内部で前記下層配線と
電気的に接続する部分を切り離すことにより前記下層配
線と前記上層の配線層とを電気的に切断することを特徴
とするIC素子における配線形成方法。2. A method of additionally forming on the IC element a new wiring film electrically connected to a desired portion of a lower layer wiring formed under an upper wiring layer inside the IC element, comprising: The insulating film formed on the upper wiring layer is irradiated with a first energy beam to form a hole in the insulating film and the upper wiring layer to expose a desired portion of the lower wiring, and a material gas atmosphere is formed. In the inside of the hole and on the IC element, a second energy beam is irradiated to deposit a metal film to form a wiring film electrically connected to a desired portion of the lower layer wiring on the IC element. , Forming a notch around the hole in the upper wiring layer to separate the portion electrically connected to the lower wiring inside the hole from the upper wiring layer by cutting the lower wiring and the upper wiring. In the IC element characterized by electrically disconnecting the wiring layer Wiring formation method. 【請求項３】前記切欠きの形成を集束エネルギビームに
よって行なうことを特徴とする特許請求の範囲第２項記
載のIC素子における配線接続方法。3. The wiring connection method for an IC element according to claim 2, wherein the notch is formed by a focused energy beam.
JP61303719A 1986-06-18 1986-12-22 IC element and wiring connection method in IC element Expired - Fee Related JPH084089B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP61303719A JPH084089B2 (en) 1986-12-22 1986-12-22 IC element and wiring connection method in IC element
US07/134,460 US4900695A (en) 1986-12-17 1987-12-17 Semiconductor integrated circuit device and process for producing the same
US07/584,180 US6753253B1 (en) 1986-06-18 1990-09-18 Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61303719A JPH084089B2 (en) 1986-12-22 1986-12-22 IC element and wiring connection method in IC element

Publications (2)

Publication Number Publication Date
JPS63157438A JPS63157438A (en) 1988-06-30
JPH084089B2 true JPH084089B2 (en) 1996-01-17

Family

ID=17924437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61303719A Expired - Fee Related JPH084089B2 (en) 1986-06-18 1986-12-22 IC element and wiring connection method in IC element

Country Status (1)

Country Link
JP (1) JPH084089B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2647188B2 (en) * 1989-03-20 1997-08-27 株式会社東芝 Method for manufacturing semiconductor device
JPH0732958B2 (en) * 1989-07-14 1995-04-12 株式会社東芝 Laser processing method
JP2567952B2 (en) * 1989-09-05 1996-12-25 株式会社日立製作所 LSI repair wiring method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5996746A (en) * 1982-11-26 1984-06-04 Hitachi Ltd Semiconductor device and manufacture thereof
JPS60245227A (en) * 1984-05-21 1985-12-05 Seiko Instr & Electronics Ltd Pattern film forming method
JPS61224342A (en) * 1985-03-29 1986-10-06 Hitachi Ltd Correction for lsi aluminum wiring and device thereof

Also Published As

Publication number Publication date
JPS63157438A (en) 1988-06-30

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