JPH08339684A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPH08339684A
JPH08339684A JP8121453A JP12145396A JPH08339684A JP H08339684 A JPH08339684 A JP H08339684A JP 8121453 A JP8121453 A JP 8121453A JP 12145396 A JP12145396 A JP 12145396A JP H08339684 A JPH08339684 A JP H08339684A
Authority
JP
Japan
Prior art keywords
power supply
supply voltage
word line
row address
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8121453A
Other languages
Japanese (ja)
Inventor
Keiken Kei
桂顯 慶
Soo-In Cho
秀仁 趙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH08339684A publication Critical patent/JPH08339684A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a semiconductor memory by eliminating the need of a boosting circuit and a high-voltage generating circuit for driving word lines by obtaining a word line driving voltage by supplying an external power supply voltage to a word line driver. SOLUTION: When a prescribed row address is transmitted from a row address buffer, a row address decoder 2 decodes the row address and one word line WL is selected out of a large number of word lines in accordance with the decoded row address. An external power supply voltage is supplied to an internal power supply voltage generating circuit 8 and a word line driver 4 and the circuit converts the supplied voltage into an external power supply voltage and outputs the external power supply voltage to an internal circuit. The word line driver 4 which receives the external power supply voltage transmits the inputted external power supply voltage to the selected work line WL in accordance with the output of the decoder 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体メモリのワ
ードライン駆動に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to word line driving of a semiconductor memory.

【０００２】[0002]

【従来の技術】半導体メモリは高集積化と低消費電力化
が進められる傾向にあり、その中で特に、消費電力を抑
えるために、チップ外部から入力される外部電源電圧を
内部電源電圧に変換する内部電源電圧発生回路を内部で
使用している。この内部電源電圧発生回路に関しては、
多数の論文や特許出願を通じて広く知られている。2. Description of the Related Art Semiconductor memories tend to be highly integrated and have low power consumption. In particular, in order to suppress power consumption, an external power supply voltage input from outside the chip is converted into an internal power supply voltage. The internal power supply voltage generating circuit is used internally. Regarding this internal power supply voltage generation circuit,
It is widely known through numerous papers and patent applications.

【０００３】半導体メモリの代表格であるＤＲＡＭやＳ
ＲＡＭにおいて、ワードライン駆動電圧は、通常、例え
ばメモリセルを構成するアクセストランジスタのしきい
値電圧より高くなければならない。従って、内部電源電
圧よりも高い電圧を昇圧発生してワードライン駆動に用
いるようにしている。図１に、ワードライン駆動電圧と
して昇圧回路の出力電圧を使用する半導体メモリの関係
部分のブロック図を示し、図２に、ワードライン駆動電
圧として高電圧発生回路の出力電圧を使用する半導体メ
モリの関係部分のブロック図を示す。DRAM and S, which are typical semiconductor memories,
In a RAM, the word line drive voltage must usually be higher than the threshold voltage of the access transistors that make up a memory cell, for example. Therefore, a voltage higher than the internal power supply voltage is generated and used for word line driving. FIG. 1 is a block diagram of a related portion of a semiconductor memory that uses an output voltage of a booster circuit as a word line driving voltage, and FIG. 2 shows a block diagram of a semiconductor memory that uses an output voltage of a high voltage generating circuit as a word line driving voltage. The block diagram of a related part is shown.

【０００４】図１において、ローアドレス(ROW ADDRES
S) はローアドレスデコーダ２に入力され、このローア
ドレスデコーダ２の出力がワードラインドライバ４へ入
力される。外部電源電圧(EXTERNAL SUPPLY VOLTAGE) は
内部電源電圧発生回路８に入力され、この内部電源電圧
発生回路８の出力がローアドレスストローブ信号バーＲ
ＡＳで制御される昇圧回路６へ入力される。ワードライ
ンドライバ４は、ローアドレスデコーダ２の出力に従っ
て昇圧回路６の出力電圧を駆動し、ワードラインＷＬへ
提供する。メモリセルアレイ１０において、多数のメモ
リセルは多数のワードラインＷＬと多数のビットライン
対ＢＬ，バーＢＬとの間に配列されており、各メモリセ
ルは、ワードラインＷＬにゲートが接続されたアクセス
トランジスタ１２と、このアクセストランジスタ１２を
介してビットラインと接続されるストレージキャパシタ
１４と、から構成されている。ワードラインドライバ４
の出力は、このメモリセルアレイ１０内の多数のワード
ラインＷＬへ選択的に提供される。In FIG. 1, row address (ROW ADDRES
S) is input to the row address decoder 2, and the output of the row address decoder 2 is input to the word line driver 4. The external power supply voltage (EXTERNAL SUPPLY VOLTAGE) is input to the internal power supply voltage generation circuit 8, and the output of the internal power supply voltage generation circuit 8 is the row address strobe signal bar R.
It is input to the booster circuit 6 controlled by AS. The word line driver 4 drives the output voltage of the booster circuit 6 according to the output of the row address decoder 2 and supplies it to the word line WL. In the memory cell array 10, a large number of memory cells are arranged between a large number of word lines WL and a large number of bit line pairs BL, BL, and each memory cell has an access transistor whose gate is connected to the word line WL. 12 and a storage capacitor 14 connected to the bit line via the access transistor 12. Word line driver 4
Is selectively provided to a large number of word lines WL in the memory cell array 10.

【０００５】所定のローアドレスがローアドレスバッフ
ァ（図示略）から伝達されれば、ローアドレスデコーダ
２が該ローアドレスをデコーディングし、それによって
多数のワードライン中の１本が選択される。一方、外部
電源電圧が内部電源電圧発生回路８に入力されることで
内部電源電圧発生回路８が外部電源電圧を変換して内部
電源電圧を出力し、この内部電源電圧がローアドレスス
トローブ信号バーＲＡＳによりエネーブルされる昇圧回
路６により昇圧される。そして、ワードラインドライバ
４が、ローアドレスデコーダ２の出力に応じて昇圧回路
６からの昇圧電圧を選択ワードラインＷＬへ提供するこ
とになる。このようにして昇圧電圧がワードライン電圧
として選択ワードラインＷＬに印加されれば、選択ワー
ドラインＷＬに接続のメモリセルに記憶されたデータが
対応ビットラインへ伝達される。このデータはセンスア
ンプ回路（図示略）で増幅され、入出力ライン及びデー
タライン（図示略）を通じて読み出される。これによ
り、１ビットのデータ読出動作が完了する。When a predetermined row address is transmitted from a row address buffer (not shown), the row address decoder 2 decodes the row address, so that one of many word lines is selected. On the other hand, when the external power supply voltage is input to internal power supply voltage generation circuit 8, internal power supply voltage generation circuit 8 converts the external power supply voltage and outputs the internal power supply voltage. This internal power supply voltage is applied to row address strobe signal bar RAS. The voltage is boosted by the booster circuit 6 that is enabled by the. Then, the word line driver 4 provides the boosted voltage from the booster circuit 6 to the selected word line WL according to the output of the row address decoder 2. When the boosted voltage is applied to the selected word line WL as the word line voltage in this manner, the data stored in the memory cell connected to the selected word line WL is transmitted to the corresponding bit line. This data is amplified by a sense amplifier circuit (not shown) and read through an input / output line and a data line (not shown). This completes the 1-bit data read operation.

【０００６】図２の構成は、昇圧回路６が高電圧発生回
路１２に置き換えられることを除いて図１の構成と同様
であり、また、図２の回路の動作は、昇圧回路６に代え
て高電圧発生回路１２の出力電圧がワードライン駆動電
圧として使用される点を除いて図１の回路の動作と同様
である。その違いは、図１に示す昇圧回路６が、ワード
ラインＷＬのエネーブル時のみ、即ちローアドレススト
ローブ信号バーＲＡＳの活性化時にのみ動作して昇圧電
圧を出力するのに対し、図２に示す高電圧発生回路１６
はパワーオンで常時高電圧を出力する点にある。The configuration of FIG. 2 is the same as that of FIG. 1 except that the booster circuit 6 is replaced by a high voltage generating circuit 12, and the operation of the circuit of FIG. The operation is similar to that of the circuit of FIG. 1 except that the output voltage of the high voltage generating circuit 12 is used as the word line driving voltage. The difference is that the booster circuit 6 shown in FIG. 1 operates and outputs the boosted voltage only when the word line WL is enabled, that is, when the row address strobe signal bar RAS is activated, whereas the booster circuit shown in FIG. Voltage generation circuit 16
Is that it always outputs a high voltage when the power is turned on.

【０００７】[0007]

【発明が解決しようとする課題】昇圧回路６や高電圧発
生回路１２の出力電圧をワードライン駆動電圧として使
用する半導体メモリでは、これら内部電源電圧を昇圧す
るための昇圧回路６や高電圧発生回路１６をチップ内に
付加回路として別途に必要とする。従ってその分がチッ
プ面積の増加につながっており、これは、更に高集積化
の進められるメモリにとって好ましくない。また、この
昇圧回路６や高電圧発生回路１２が設けてあると、ワー
ドライン選択時にはアクティブ電流(active current)が
消費され、またワードライン非選択時にはスタンバイ電
流(standby current) が消費されるので、メモリの消費
電力増大につながっている。In a semiconductor memory that uses the output voltage of the booster circuit 6 or the high voltage generator circuit 12 as a word line drive voltage, the booster circuit 6 or the high voltage generator circuit for boosting these internal power supply voltages is used. 16 is separately required as an additional circuit in the chip. Therefore, that amount leads to an increase in the chip area, which is not preferable for a memory with higher integration. Further, when the booster circuit 6 and the high voltage generating circuit 12 are provided, an active current is consumed when the word line is selected, and a standby current is consumed when the word line is not selected. This has led to an increase in memory power consumption.

【０００８】そこで本発明では、より高集積化が可能
で、また消費電力のより少ない半導体メモリを提供する
ことにある。Therefore, the present invention is to provide a semiconductor memory which can be highly integrated and consumes less power.

【０００９】[0009]

【課題を解決するための手段】この目的のために本発明
によれば、内部電源電圧よりも高い電圧をワードライン
駆動電圧として使用する半導体メモリにおいて、外部電
源電圧をワードラインドライバへ提供してワードライン
駆動電圧とすることを特徴とする。即ち、多数のビット
ラインと多数のワードラインとの間にマトリックス形態
で配列された多数のメモリセルと、内部回路用の内部電
源電圧を発生する内部電源電圧発生手段と、ワードライ
ンを選択するためのワードライン選択手段と、このワー
ドライン選択手段の出力に応じて内部電源電圧より高い
ワードライン駆動電圧を選択ワードラインへ供給するた
めのワードラインドライバと、を備えた半導体メモリに
おいて、外部電源電圧をワードライン駆動電圧としてワ
ードラインドライバに提供するものである。To this end, according to the present invention, an external power supply voltage is provided to a word line driver in a semiconductor memory using a voltage higher than an internal power supply voltage as a word line drive voltage. It is characterized by using a word line drive voltage. That is, a large number of memory cells arranged in a matrix between a large number of bit lines and a large number of word lines, an internal power supply voltage generating means for generating an internal power supply voltage for an internal circuit, and a word line for selecting. And a word line driver for supplying a word line driving voltage higher than the internal power supply voltage to the selected word line according to the output of the word line selection means. Is provided to the word line driver as a word line drive voltage.

【００１０】[0010]

【発明の実施の形態】以下、本発明の実施形態につき図
３を参照して詳細に説明する。尚、共通部分には同じな
符号を付してある。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. The common parts are given the same reference numerals.

【００１１】この例の半導体メモリでは、ローアドレス
がローアドレスデコーダ２に入力され、ローアドレスデ
コーダ２の出力がワードラインドライバ４へ入力されて
いる。そして、外部電源電圧は、内部電源電圧発生回路
８とワードラインドライバ４とにそれぞれ入力されてい
る。メモリセルアレイ１０において、多数のメモリセル
は多数のワードラインＷＬと多数のビットライン対Ｂ
Ｌ，バーＢＬとの間に配列され、各メモリセルは、ワー
ドラインＷＬにゲートが接続されたアクセストランジス
タ１２と、このアクセストランジスタ１２を介してビッ
トラインに接続されるストレージキャパシタ１４と、か
ら構成される。ワードラインドライバ４の出力は、この
メモリセルアレイ１０内の多数のワードラインＷＬへ選
択的に提供される。In the semiconductor memory of this example, the row address is input to the row address decoder 2 and the output of the row address decoder 2 is input to the word line driver 4. Then, the external power supply voltage is input to the internal power supply voltage generation circuit 8 and the word line driver 4, respectively. In the memory cell array 10, many memory cells include many word lines WL and many bit line pairs B.
Each memory cell is arranged between L and bar BL, and each memory cell includes an access transistor 12 having a gate connected to a word line WL, and a storage capacitor 14 connected to a bit line via the access transistor 12. To be done. The output of the word line driver 4 is selectively provided to many word lines WL in the memory cell array 10.

【００１２】所定のローアドレスがローアドレスバッフ
ァ（図示略）から伝達されれば、ローアドレスデコーダ
２がそのローアドレスをデコーディングし、これに従っ
て多数のワードライン中１本のワードラインＷＬが選択
される。外部電源電圧は内部電源電圧発生回路８及びワ
ードラインドライバ４へそれぞれ提供され、内部電源電
圧発生回路８では、外部電源電圧を内部電源電圧に変換
して内部回路へ出力する。内部電源電圧は外部電源電圧
より低く設定され、例えば、外部電源電圧が５Ｖであれ
ば内部電源電圧は３．３Ｖである。When a predetermined row address is transmitted from a row address buffer (not shown), the row address decoder 2 decodes the row address, and one word line WL is selected from a number of word lines according to the decoded row address. It The external power supply voltage is provided to the internal power supply voltage generation circuit 8 and the word line driver 4, respectively, and the internal power supply voltage generation circuit 8 converts the external power supply voltage into the internal power supply voltage and outputs it to the internal circuit. The internal power supply voltage is set lower than the external power supply voltage. For example, if the external power supply voltage is 5V, the internal power supply voltage is 3.3V.

【００１３】一方、外部電源電圧を受けるワードライン
ドライバ４は、ローアドレスデコーダ２の出力に応じ
て、入力される外部電源電圧を選択ワードラインＷＬへ
伝達する。即ち、外部電源電圧がワードライン駆動電圧
として使用され、選択ワードラインＷＬに接続したメモ
リセルの記憶データが対応ビットラインへ送られる。伝
達されたデータはセンスアンプ回路（図示略）で増幅さ
れ、入出力ライン及びデータライン（図示略）を通じて
読出されることになる。このようにして１ビットのデー
タ読出動作が完了する。On the other hand, the word line driver 4 receiving the external power supply voltage transmits the input external power supply voltage to the selected word line WL according to the output of the row address decoder 2. That is, the external power supply voltage is used as the word line driving voltage, and the storage data of the memory cell connected to the selected word line WL is sent to the corresponding bit line. The transmitted data is amplified by a sense amplifier circuit (not shown) and read out through an input / output line and a data line (not shown). In this way, the 1-bit data read operation is completed.

【００１４】以上、ＤＲＡＭなどのダイナミック形メモ
リセルをもつメモリを例に説明したが、ＳＲＡＭなどの
スタティック形メモリセルをもつメモリでも同様に実施
可能であることは、容易に理解されよう。Although a memory having dynamic memory cells such as DRAM has been described above as an example, it will be easily understood that a memory having static memory cells such as SRAM can be similarly implemented.

【００１５】[0015]

【発明の効果】本発明による半導体メモリでは、ワード
ライン駆動用に昇圧回路や高電圧発生回路を使用せずと
もすむため、その分、高集積化に有利である。しかも、
半導体メモリの活性時や非活性時に昇圧回路や高電圧発
生回路によるアクティブ電流及びスタンドバイ電流が消
費されないことになるので、消費電力を抑制することが
可能である。In the semiconductor memory according to the present invention, it is not necessary to use a booster circuit or a high voltage generation circuit for driving a word line, which is advantageous for high integration. Moreover,
Since the active current and the standby current due to the booster circuit and the high voltage generation circuit are not consumed when the semiconductor memory is activated or deactivated, it is possible to suppress power consumption.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来例の半導体メモリを示す要部ブロック図。FIG. 1 is a block diagram of a main part showing a conventional semiconductor memory.

【図２】他の従来例の半導体メモリを示す要部ブロック
図。FIG. 2 is a principal block diagram showing another conventional semiconductor memory.

【図３】本発明による半導体メモリを示す要部ブロック
図。FIG. 3 is a principal block diagram showing a semiconductor memory according to the present invention.

【符号の説明】[Explanation of symbols]

２ ローデコーダ ４ ワードラインドライバ ８ 内部電源電圧発生回路 2 row decoder 4 word line driver 8 internal power supply voltage generation circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 内部電源電圧よりも高い電圧をワードラ
イン駆動電圧として使用する半導体メモリにおいて、外
部電源電圧をワードラインドライバへ提供してワードラ
イン駆動電圧とするようにしたことを特徴とする半導体
メモリ。1. A semiconductor memory that uses a voltage higher than an internal power supply voltage as a word line drive voltage, wherein an external power supply voltage is provided to a word line driver to be used as the word line drive voltage. memory. 【請求項２】 ダイナミック形メモリセルををもつ請求
項１記載の半導体メモリ。2. The semiconductor memory according to claim 1, having dynamic memory cells. 【請求項３】 スタティック形メモリセルをもつ請求項
１記載の半導体メモリ。3. The semiconductor memory according to claim 1, which has a static memory cell.
JP8121453A 1995-05-17 1996-05-16 Semiconductor memory Pending JPH08339684A (en)

Applications Claiming Priority (2)

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KR1019950012273A KR0164816B1 (en) 1995-05-17 1995-05-17 Semiconductor memory using word line driving voltage
KR1995P12273 1995-05-17

Publications (1)

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JPH08339684A true JPH08339684A (en) 1996-12-24

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KR (1) KR0164816B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008059734A (en) * 2006-08-31 2008-03-13 Hynix Semiconductor Inc Semiconductor memory device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100765439B1 (en) * 2006-04-11 2007-10-11 경북대학교 산학협력단 Sram utilizing dual-boosted cell bias technique
US7936615B2 (en) 2007-02-27 2011-05-03 Samsung Electronics Co., Ltd. Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62178013A (en) * 1986-01-31 1987-08-05 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62178013A (en) * 1986-01-31 1987-08-05 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008059734A (en) * 2006-08-31 2008-03-13 Hynix Semiconductor Inc Semiconductor memory device

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KR960042725A (en) 1996-12-21
KR0164816B1 (en) 1999-02-01

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