JPH08335606A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08335606A JPH08335606A JP16139995A JP16139995A JPH08335606A JP H08335606 A JPH08335606 A JP H08335606A JP 16139995 A JP16139995 A JP 16139995A JP 16139995 A JP16139995 A JP 16139995A JP H08335606 A JPH08335606 A JP H08335606A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- film
- electrode
- auxiliary wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップスケ−ルパッケ
−ジ（ＣＳＰ）タイプの半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip scale package (CSP) type semiconductor device.
【０００２】[0002]
【従来の技術】パッケ−ジした半導体装置としては、リ
−ドフレ−ムのダイパットに半導体チップを搭載し、半
導体チップの電極とリ−ドフレ−ムのインナ−リ−ドと
をワイヤ−ボンディングし、半導体チップをリ−ドフレ
−ムと共にアウタ−リ−ドを除いて樹脂で封止した構造
が周知されている。しかし、かかるパッケ−ジ構造で
は、リ−ドフレ−ムのアウタ−リ−ドのピッチをはんだ
付け精度上かなり広くする必要があり、パッケ−ジの大
型化が避けられず高密度化に不利である。2. Description of the Related Art As a packaged semiconductor device, a semiconductor chip is mounted on a die pad of a lead frame, and an electrode of the semiconductor chip and an inner lead of the lead frame are wire bonded. A structure in which a semiconductor chip is sealed with a resin except a lead frame and an outer lead is well known. However, in such a package structure, it is necessary to make the outer lead pitch of the lead frame considerably wide in terms of soldering accuracy, and it is inevitable that the package becomes large in size, which is disadvantageous to high density. is there.
【０００３】そこで、図４の（イ）または（ロ）に示す
ように、半導体チップ１’の電極１１’に接続される内
側電極２１’と被実装回路板の導体端に接続される外側
電極２２’とこれらの電極間にまたがる引き回し導体２
３’とからなるプリント配線パタ−ンを設けたチップサ
イズの補助配線板片２’〔図４の（イ）においては引き
回し導体２３’が埋設配線され、図４の（ロ）において
は引き回し導体２３’が表面に配線されている〕を半導
体チップ１’の電極１１’側の面にあてがい、該補助配
線板片２’の内側電極２１’と半導体チップ１’の電極
１１’とを金属バンプ２２１’を介して接続し、補助配
線板片２’と半導体チップ１’との間の間隙並びに半導
体チップ外面を樹脂３’で封止することが提案されてい
る（特開平６−７７２９３号公報、特開平５−８２５８
６号公報等）。Therefore, as shown in FIG. 4A or 4B, the inner electrode 21 'connected to the electrode 11' of the semiconductor chip 1'and the outer electrode connected to the conductor end of the mounted circuit board. 22 'and the lead conductor 2 extending between these electrodes
3'is a chip-sized auxiliary wiring board piece 2'provided with a printed wiring pattern (in FIG. 4A, the leading conductor 23 'is embedded and in FIG. 4B, the leading conductor is embedded. 23 'is wired on the surface] to the surface of the semiconductor chip 1'on the side of the electrode 11', and the inner electrode 21 'of the auxiliary wiring board piece 2'and the electrode 11' of the semiconductor chip 1'are metal bumps. It has been proposed to connect via 221 'and seal the gap between the auxiliary wiring board piece 2'and the semiconductor chip 1'and the outer surface of the semiconductor chip with a resin 3' (JP-A-6-77293). JP-A-5-8258
No. 6, etc.).
【０００４】この半導体装置での樹脂封止においては、
補助配線板片２’と半導体チップ１’との間並びに半
導体チップ外面を一挙にトランスファモ−ルド法（トラ
ンスファ−成形機の金型のキャビティに補助配線板片
２’付き半導体チップをセットし、タブレットをトラン
スファ−成形機のポットに入れ、このタブレットを加熱
により可塑化すると共にプランジャ−で加圧し、スプ−
ル、ランナ−並びにゲ−トを経てその可塑化樹脂を金型
キャビティに圧入する方法）により樹脂封止するか、
補助配線板片２’と半導体チップ１’との間を接着樹脂
の介在のもとで金属バンブ接続して金属バンブ接続と共
に補助配線板片２’と半導体チップ１’との間を樹脂封
止し、次いで、ポッティング、キャスティング等により
半導体チップ外面側を樹脂封止している（特開平６−７
７２９３号公報、特開平５−８２５８６号公報等）。In the resin sealing of this semiconductor device,
Between the auxiliary wiring board piece 2'and the semiconductor chip 1'and on the outer surface of the semiconductor chip, the transfer molding method (the semiconductor chip with the auxiliary wiring board piece 2'is set in the cavity of the die of the transfer molding machine, Put the tablet in the pot of the transfer molding machine, plasticize the tablet by heating and pressurize with a plunger to spread the tablet.
Resin, the plasticized resin is press-fitted into the mold cavity through a mold, a runner, and a gate).
A metal bump connection is made between the auxiliary wiring board piece 2'and the semiconductor chip 1'through the interposition of an adhesive resin, and a metal bump connection is performed, and at the same time, the auxiliary wiring board piece 2'and the semiconductor chip 1'are resin-sealed. Then, the outer surface of the semiconductor chip is resin-sealed by potting, casting or the like (Japanese Patent Laid-Open No. 6-7).
7293, JP-A-5-82586, etc.).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記
の場合は、サイズ変更に伴う金型交換の手間やカルやラ
ンナ−での樹脂ロスのために樹脂ロス量が多いといった
不利があり、のキャスティングの場合もサイズ変更に
伴う金型交換の手間の問題があり、のポッティングの
場合は、無加圧であるのでボイドが発生し易いといった
問題がある。上記樹脂封止の半導体装置において、半導
体チップに使用時での発熱量が大なる、例えば、マイク
ロプロセッサ−やＡＳＩＣタイプのチップを使用する場
合、樹脂に多量の無機質フィラ−を添加して放熱性をア
ップすることが要求されるが、無機質フィラ−の多量添
加のもとでは樹脂の高粘性化が避けられず、トランスフ
ァ成形、ポッティング、キャスティング等の成形では、
封止性能の低下、作業性の低下等を免れ得ない。However, in the above case, there is a disadvantage that the amount of resin loss is large due to the time and effort of exchanging the mold due to the size change and the resin loss at the cull and runner. Also in this case, there is a problem of changing the size of the mold, and in the case of potting, there is a problem that voids are likely to occur because no pressure is applied. In the above-mentioned resin-sealed semiconductor device, a semiconductor chip generates a large amount of heat when used. For example, when a microprocessor or an ASIC type chip is used, a large amount of inorganic filler is added to the resin to improve heat dissipation. However, it is inevitable that the resin becomes highly viscous under the addition of a large amount of inorganic filler, and transfer molding, potting, casting, etc.
Inevitable deterioration of sealing performance and workability.
【０００６】本発明の目的は、半導体チップの電極に接
続される内側電極と被実装回路板の導体端に接続される
外側電極とこれらの電極間にまたがる引き回し導体とか
らなる配線パタ−ンを有するチップサイズの補助配線板
片と半導体チップの電極とを金属バンプを介し接続し、
封止材で封止する半導体装置において、信頼性、放熱性
に優れた封止を簡易な作業で低コストにて行い得るＣＳ
Ｐ半導体装置を提供することにある。An object of the present invention is to provide a wiring pattern comprising an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes. The chip-sized auxiliary wiring board pieces and the electrodes of the semiconductor chip are connected via metal bumps,
In a semiconductor device which is sealed with a sealing material, CS which can perform sealing with excellent reliability and heat dissipation by a simple operation at a low cost
It is to provide a P semiconductor device.
【０００７】[0007]
【課題を解決するための手段】本発明に係る半導体装置
は、半導体チップの電極に接続される内側電極と被実装
回路板の導体端に接続される外側電極とこれらの電極間
にまたがる引き回し導体とからなる配線パタ−ンを設け
た補助配線板片の内側電極側と半導体チップの電極とを
金属バンプを介して接続し、補助配線板片と半導体チッ
プとの間に封止樹脂を介在させ、半導体チップの電極側
とは反対側の全面若しくは周囲部及び半導体チップの側
面並びに上記補助配線板片の端部にわたって熱接着性の
シ−トまたはフィルムを熱圧着したことを特徴とする構
成であり、熱接着性のシ−トまたはフィルムに基材の片
面に熱圧着性層を有する複合体を使用し、この熱圧着性
層において熱圧着することもできる。また、熱接着性の
シ−トまたはフィルムには７０重量％以上のシリカ、ア
ルミナ等の無機質フィラ−を含有するもの、若しくは、
室温で２．５Ｗ／ｍＫ以上の熱伝導率を有するものを使
用することが好ましい。A semiconductor device according to the present invention is directed to an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes. The inner electrode side of the auxiliary wiring board piece provided with a wiring pattern consisting of and the electrodes of the semiconductor chip are connected via metal bumps, and a sealing resin is interposed between the auxiliary wiring board piece and the semiconductor chip. A heat-adhesive sheet or film is thermocompression-bonded over the entire surface of the side opposite to the electrode side of the semiconductor chip or the side surface of the semiconductor chip and the end of the auxiliary wiring board piece. It is also possible to use a composite having a thermocompression bonding layer on one surface of the substrate in a heat-adhesive sheet or film, and perform thermocompression bonding in this thermocompression bonding layer. Further, the heat-adhesive sheet or film contains 70% by weight or more of an inorganic filler such as silica or alumina, or
It is preferable to use a material having a thermal conductivity of 2.5 W / mK or more at room temperature.
【０００８】以下、図面を参照しつつ本発明の構成につ
いて説明する。図１は本発明に係る半導体装置の一例を
示す説明図である。図１において、１は半導体チップで
ある。２は補助配線板片を示し、半導体チップ１の電極
１１に接続される内側電極２１と被実装回路板の導体端
に接続される外側電極２２とこれらの電極間にまたがる
引き回し導体２３とからなる配線パタ−ンをプラスック
絶縁層２４，２５に設けた構成であり、内側電極２１は
絶縁層２４の内側電極用孔２１２に充填された金属２１
３により構成され、この充填金属２１３の端面には金属
バンプ２１１が予め形成され、補助配線板片２の内側電
極側２１と半導体チップ１の電極１１とを金属バンプ２
１１を介し接続してある。The structure of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing an example of a semiconductor device according to the present invention. In FIG. 1, reference numeral 1 is a semiconductor chip. Reference numeral 2 denotes an auxiliary wiring board piece, which is composed of an inner electrode 21 connected to the electrode 11 of the semiconductor chip 1, an outer electrode 22 connected to the conductor end of the mounted circuit board, and a lead conductor 23 extending between these electrodes. The wiring pattern is provided in the plastic insulating layers 24 and 25, and the inner electrode 21 is the metal 21 filled in the inner electrode hole 212 of the insulating layer 24.
3, a metal bump 211 is formed in advance on the end surface of the filling metal 213, and the inner electrode side 21 of the auxiliary wiring board piece 2 and the electrode 11 of the semiconductor chip 1 are connected to each other by the metal bump 2
It is connected via 11.
【０００９】３は半導体チップ１と補助配線板片２との
間を封止せる樹脂である。この樹脂封止には、半導体チ
ップ側または補助配線板片側に熱可塑性樹脂液を塗布
し、または半導体チップと補助配線板片との間に熱可塑
性樹脂シ−トまたはフィルム（例えば、熱融着性ポリイ
ミドフィルム）を介在させて半導体チップと補助配線板
片との金属バンプ接続を行うと共にその接続時の熱で熱
可塑性樹脂を溶融させて半導体チップと補助配線板片と
の間を接着させる方法、同金属バンプ接続後に半導体チ
ップと補助配線板片との間隙に硬化性の液状樹脂（例え
ば、液状エポキシ樹脂）を注入する方法等を使用でき
る。Reference numeral 3 is a resin that seals between the semiconductor chip 1 and the auxiliary wiring board piece 2. For this resin encapsulation, a thermoplastic resin liquid is applied to the semiconductor chip side or the auxiliary wiring board piece side, or a thermoplastic resin sheet or film (for example, heat fusion bonding) is provided between the semiconductor chip and the auxiliary wiring board piece. Bump connection between a semiconductor chip and an auxiliary wiring board piece through a conductive polyimide film), and the thermoplastic resin is melted by the heat of the connection to bond the semiconductor chip and the auxiliary wiring board piece. A method of injecting a curable liquid resin (for example, a liquid epoxy resin) into the gap between the semiconductor chip and the auxiliary wiring board piece after connecting the metal bumps can be used.
【００１０】４は半導体チップ１の裏面（半導体チップ
の電極側とは反対側の面）及び半導体チップ１の側面並
びに補助配線板片２の端部にわたって熱圧着した熱接着
性のシ−トまたはフィルムフィルムである。この熱接着
性のシ−トまたはフィルムフィルム４は、図２の（イ）
に示すように半導体チップ１の裏面周囲部（この裏面周
囲部の面積は全裏面の面積の３０％以上）及び半導体チ
ップ１の側面並びに補助配線板片２の端部にわたって熱
圧着してもよい。Reference numeral 4 denotes a heat-adhesive sheet which is thermocompression bonded to the back surface of the semiconductor chip 1 (the surface opposite to the electrode side of the semiconductor chip), the side surface of the semiconductor chip 1 and the end portion of the auxiliary wiring board piece 2. It is a film. This heat-adhesive sheet or film film 4 is shown in FIG.
As shown in FIG. 5, the periphery of the back surface of the semiconductor chip 1 (the area of the periphery of the back surface is 30% or more of the total back surface area), the side surface of the semiconductor chip 1 and the end portion of the auxiliary wiring board piece 2 may be thermocompression bonded. .
【００１１】この熱接着性のシ−トまたはフィルムに
は、例えば、熱可塑性ポリイミド、シリコ−ン樹脂、ア
クリル樹脂、オレフィン樹脂、エポキシ樹脂等を使用で
き、特に、熱可塑性ポリイミドの使用が耐熱信頼性の観
点から好ましい。また、実質的に非熱接着性の支持シ−
トまたはフィルムに熱接着性層を塗布若しくはラミネ−
トにより積層した複合体を使用することもでき、その支
持シ−トまたはフィルムとしては、例えば、ポリイミド
フィルム、ポリエチレンテレフタレ−トフィルム、ポリ
エ−テルイミドフィルム、ポリエ−テルサルホンフィル
ム、ポリフェニレンサルファイドフィルム、ポリエ−テ
ルエ−テルケトンフィルム等を使用できる。For the heat-adhesive sheet or film, for example, thermoplastic polyimide, silicone resin, acrylic resin, olefin resin, epoxy resin or the like can be used. In particular, the use of thermoplastic polyimide is heat resistant and reliable. It is preferable from the viewpoint of sex. Also, a substantially non-heat-adhesive support sheet
Coating or laminating a heat-adhesive layer on the film or film
It is also possible to use a composite laminated by a sheet, as the supporting sheet or film, for example, a polyimide film, polyethylene terephthalate film, polyether imide film, polyethylene sulfone film, polyphenylene sulfide film, Polyether ether ketone film or the like can be used.
【００１２】上記熱圧着性シ−トまたはフィルムには、
半導体チップ裏面側の放熱性を高くするために、熱伝導
率を２．５ｗ／m・K以上、好ましくは、５．０ｗ／m・K以
上とすることが有効であ。例えば、熱接着性のシ−トま
たはフィルム、熱接着性層または非熱接着性のシ−トま
たはフィルムに無機質フィラ−、例えば、シリカ、アル
ミナ、酸化チタン、炭酸カルシウム、銀燐片状フィラ−
等を高充填することが有効である。上記熱圧着性シ−ト
またはフィルムには、必要に応じ、シランやチタネ−ト
系のカップリング剤や表面調整剤、シリコ−ン樹脂やア
クリルゴム等のゴム成分、各種顔料等を添加することも
できる。The above-mentioned thermocompression-bondable sheet or film includes
In order to improve the heat dissipation on the back side of the semiconductor chip, it is effective to set the thermal conductivity to 2.5 w / m · K or more, preferably 5.0 w / m · K or more. For example, a heat-adhesive sheet or film, a heat-adhesive layer or a non-heat-adhesive sheet or film with an inorganic filler such as silica, alumina, titanium oxide, calcium carbonate, silver flaky filler.
It is effective to highly fill the same. If necessary, a silane or titanate coupling agent or a surface modifier, a rubber component such as silicone resin or acrylic rubber, various pigments, etc. may be added to the thermocompression-bonding sheet or film. You can also
【００１３】上記補助配線板片２の大きさは、半導体チ
ップ１の平面寸法（通常、３ｍｍ〜２０ｍｍ角）にほぼ
等しいか、半導体チップ１の平面寸法の２００％以下、
好ましくは、１３０％以下とされる。上記外側電極２
２，２２相互間の間隔につては、被実装回路基板にはん
だ付けする際でのはんだブリッジを防止するために、上
記補助配線板片２の平面寸法内でできるだけ広くするこ
とが要求され、通常ほぼ等間隔とされる。上記補助配線
板片２は図２の（ロ）に示すように多層構造とすること
もできる。図２の（ロ）において、半導体チップ１の一
の電極１１とこの電極１１に導通させるべき被実装回路
基板の導体端１１０の対が一の層の引き回し導体２３に
対応され、この引き回し導体２３からその半導体チップ
電極１１に臨む孔２１２が絶縁積層ａに設けられ、この
孔２１２に金属２１３が充填され、その充填金属２１３
の頂上面に金属バンプ２１１が形成されてその一の引き
回し導体２３に対する内側電極２１が形成されている。
また、その一の引き回し導体２３からその一の半導体チ
ップ電極１１に導通させるべき被実装回路基板の一の導
体端１１０に臨む孔２２１が絶縁積層ａに設けられ、こ
の孔２２１に金属２２２が充填されてその一の引き回し
導体２３に対する外側電極２２が形成され、その充填金
属２２２の頂上面がはんだバンプ２２３を介して被実装
配線板の導体端に接続される。図２の（ロ）において、
３は半導体チップ１と補助配線板片２との間を封止せる
樹脂を、４は半導体チップの裏面及び半導体チップの側
面並びに補助配線板片２の端部にわたって熱圧着した熱
接着性のシ−トまたはフィルムをそれぞれ示している。The size of the auxiliary wiring board piece 2 is substantially equal to the plane size of the semiconductor chip 1 (usually 3 mm to 20 mm square), or 200% or less of the plane size of the semiconductor chip 1.
It is preferably 130% or less. The outer electrode 2
The distance between 2 and 22 is required to be as wide as possible within the plane dimension of the auxiliary wiring board piece 2 in order to prevent a solder bridge at the time of soldering to a mounted circuit board. Almost equally spaced. The auxiliary wiring board piece 2 may have a multi-layer structure as shown in FIG. In FIG. 2B, a pair of the electrode 11 of the semiconductor chip 1 and the conductor end 110 of the mounted circuit board to be electrically connected to the electrode 11 corresponds to the lead conductor 23 of the one layer. A hole 212 facing the semiconductor chip electrode 11 is provided in the insulating laminated body a, and the hole 212 is filled with a metal 213.
A metal bump 211 is formed on the top surface of the inner electrode 21 and the inner electrode 21 for the one leading conductor 23 is formed.
Further, a hole 221 facing the one conductor end 110 of the mounted circuit board to be electrically connected to the one semiconductor chip electrode 11 from the one lead conductor 23 is provided in the insulating laminated body a, and the hole 221 is filled with the metal 222. Then, the outer electrode 22 for the one lead conductor 23 is formed, and the top surface of the filling metal 222 is connected to the conductor end of the mounted wiring board via the solder bump 223. In FIG. 2B,
Reference numeral 3 denotes a resin that seals between the semiconductor chip 1 and the auxiliary wiring board piece 2; -Representing a sheet or a film, respectively.
【００１４】本発明に係る半導体装置は、次のようにし
て製造することができる。まず、図３の（イ）に示すよ
うに、絶縁支持フィルム２４の片面に引き回し導体２３
を印刷形成する。この引き回し導体２３の印刷形成に
は、金属箔積層合成樹脂フィルムの金属箔を所定の引き
回しパタ−ンに化学エッチングする方法を使用すること
が好ましい。この金属箔積層合成樹脂フィルムには、合
成樹脂フィルムに銅箔を融着した二層基材、銅箔を熱可
塑性または熱硬化性接着剤で合成樹脂フィルムに接着し
た三層基材等を使用でき。この合成樹脂フィルムの材質
の選定にあたっては、ワイヤ−バンブ法で金属バンプを
形成する場合の耐熱性、めっき法により金属バンプを形
成する場合の耐薬品性が考慮され、例えば、ポリイミド
フィルム、ポリエチレンテレフタレ−トフィルム、ポリ
エ−テルイミドフィルム、ポリエ−テルサルホンフィル
ム、ポリフェニレンサルファイドフィルム、ポリエ−テ
ルエ−テルケトンフィルム等を使用できる。この合成樹
脂フィルムの厚みは、通常１０〜１５０μｍとされる。The semiconductor device according to the present invention can be manufactured as follows. First, as shown in FIG. 3A, the conductor 23 is routed to one side of the insulating support film 24.
To print. It is preferable to use a method of chemically etching the metal foil of the metal foil laminated synthetic resin film into a predetermined routing pattern for the printed formation of the routing conductor 23. This metal foil laminated synthetic resin film uses a two-layer base material in which copper foil is fused to the synthetic resin film, a three-layer base material in which copper foil is adhered to the synthetic resin film with a thermoplastic or thermosetting adhesive, etc. I can. In selecting the material of this synthetic resin film, heat resistance when forming metal bumps by the wire-bumping method and chemical resistance when forming metal bumps by the plating method are taken into consideration. A tarate film, a polyetherimide film, a polyethersulfone film, a polyphenylene sulfide film, a polyetheretherketone film and the like can be used. The thickness of this synthetic resin film is usually 10 to 150 μm.
【００１５】このようにして引き回し導体２３を印刷形
成したのちは、図３の（ロ）に示すように絶縁支持フィ
ルム２４に内側電極用孔２１２を穿設する。この穿孔に
は、一般に、ドリル加工、レ−ザ−エッチング加工等を
使用でき、特に、ポリイミドフィルムの場合は、アルカ
リエッチング等の湿式穿孔法を使用することが可能であ
る。また、二層基材型ポリイミドフィルムの場合は、感
光性ポリイミドを使用し、露光により穿孔することもで
きる。After the lead-out conductor 23 is formed by printing in this way, an inner electrode hole 212 is formed in the insulating support film 24 as shown in FIG. For this perforation, generally, a drilling process, a laser etching process or the like can be used, and particularly in the case of a polyimide film, a wet perforation method such as alkali etching can be used. In the case of a two-layer substrate type polyimide film, a photosensitive polyimide may be used and it may be perforated by exposure.
【００１６】内側電極用孔２１２を穿孔したのちは、図
３の（ハ）に示すように、孔２１２の底面の導体２３に
金属を絶縁フィルム２４をめっきマスクとしてめっき
し、孔２１２に金属２１３を充填し、内側電極２１を形
成する。金属には、例えば、金、銀、ニッケル、銅、パ
ラジウム等を使用できる。このようにして内側電極用孔
２１２に金属２１３を充填したのちは、図３の（ニ）に
示すように充填金属面上に高さ数１０μｍの金属バンプ
２１１を形成する。この金属バンプ２１１の形成には、
ワイヤ−ボンダ−を用いて金線、銅線またははんだ線の
先端を溶融球状化させ、溶融球状化金属を充填金属面に
溶着させる方法を使用できる。金線を使用する場合、銅
の引き回し導体２３と金との接触を防止するために、充
填金属２１３の上層はニッケルとすることが好ましい。
充填金属面上に湿式めっき法で金属を盛り上げる方法に
よって金属バンプを形成することもできる。特に、金属
バンプ２１１の表面または全体を、半導体チップの電極
材であるアルミニウムと強固・安定に金属間結合する金
を使用することが好ましい。After forming the inner electrode hole 212, as shown in FIG. 3C, the conductor 23 on the bottom surface of the hole 212 is plated with a metal by using the insulating film 24 as a plating mask, and the hole 212 is filled with the metal 213. To form the inner electrode 21. As the metal, for example, gold, silver, nickel, copper, palladium or the like can be used. After the inner electrode hole 212 is filled with the metal 213 in this manner, a metal bump 211 having a height of several tens of μm is formed on the filled metal surface as shown in FIG. To form this metal bump 211,
It is possible to use a method in which the tip of a gold wire, a copper wire or a solder wire is melted into a spherical shape by using a wire bonder, and the molten spheroidized metal is welded to the filling metal surface. When a gold wire is used, it is preferable that the upper layer of the filling metal 213 be nickel in order to prevent contact between the copper routing conductor 23 and the gold.
It is also possible to form metal bumps on the filling metal surface by a method of raising metal by wet plating. In particular, it is preferable to use gold that firmly and stably bonds metal between the surface or the whole of the metal bump 211 and aluminum which is the electrode material of the semiconductor chip.
【００１７】ワイヤ−ボンダ−を用いて金属バンプを形
成する場合、孔２１２周辺が溶融金属に対する濡れ性の
低い合成樹脂面であるから、溶融金属の孔周囲への付着
を防止して充填金属面上に接触角の大なる球状の金属バ
ンプを整然と形成できる。また、めっき法により金属バ
ンプ２１１を形成する場合は、電解めっき、無電解めっ
きの何れの場合でも、充填金属２１３の露出端面を核と
して金属バンプを整然と形成できる。When forming a metal bump using a wire bonder, since the periphery of the hole 212 is a synthetic resin surface having low wettability with respect to the molten metal, the molten metal is prevented from adhering to the periphery of the hole and the filled metal surface is prevented. Spherical metal bumps with a large contact angle can be formed in an orderly manner. Further, when the metal bumps 211 are formed by the plating method, the metal bumps can be formed orderly by using the exposed end face of the filling metal 213 as a nucleus in both electrolytic plating and electroless plating.
【００１８】このようにして金属バンプ２１１を形成し
たのちは、図３の（ホ）に示すように、引き回し導体２
３の印刷形成面に樹脂２５をカバ−コ−トし、更に、図
３の（ヘ）に示すように、このカバ−コ−ト絶縁層２５
に外側電極用孔２２１を穿設し、図３の（ト）に示すよ
うに、この孔２２１に上記したワイヤ−ボンダ−により
はんだ２２２を充填して外側電極を形成する。而るのち
は、図３の（チ）に示すように、内側電極２１の金属バ
ンプ２１１を半導体チップ１の電極１１に一致させるよ
うにアライメントして、ホットバ−やパルスヒ−ト等の
一括圧着接続またはシングルポイントボンダ−による個
別熱圧着接続で半導体チップ１の電極１１と補助配線板
片２の内側電極２１とを金属バンプ２１１を介して金属
間接合し、半導体チップ１と補助配線板片２とを電気的
並びに機械的に接合する。シングルポイントボンダ−に
よる個別熱圧着接続を行う場合、超音波接合を併用して
熱圧着温度を低くすることもできる。金属バンプ２１１
にはんだバンプを使用し、補助配線板片２と半導体チッ
プ１との接合をリフロ−法により行うことも可能であ
る。After the metal bumps 211 are formed in this way, as shown in FIG.
The resin 25 is coated on the printed surface of No. 3 and further, as shown in FIG.
An outer electrode hole 221 is formed in the hole 221 and, as shown in FIG. 3G, the hole 221 is filled with the solder 222 by the wire bonder to form the outer electrode. After that, as shown in FIG. 3C, the metal bumps 211 of the inner electrodes 21 are aligned so as to be aligned with the electrodes 11 of the semiconductor chip 1 and are collectively pressure-bonded by a hot bar or a pulse heat. Alternatively, the electrodes 11 of the semiconductor chip 1 and the inner electrodes 21 of the auxiliary wiring board pieces 2 are metal-to-metal bonded via the metal bumps 211 by individual thermocompression bonding using a single point bonder, and the semiconductor chip 1 and the auxiliary wiring board pieces 2 are connected to each other. Are electrically and mechanically joined. When performing individual thermocompression bonding using a single point bonder, ultrasonic bonding can be used together to lower the thermocompression bonding temperature. Metal bump 211
It is also possible to use a solder bump and to bond the auxiliary wiring board piece 2 and the semiconductor chip 1 by the reflow method.
【００１９】このようにして、補助配線板片２に半導体
チップ１を搭載したのちは、図３の（チ）に示すよう
に、半導体チップ１と補助配線板片２との間を液状樹脂
３、例えば、液状エポキシ樹脂の注入により封止する。
この樹脂注入による封止に代え、上記半導体チップと補
助配線板片との金属バンプ接続に先立ち、半導体チップ
側または補助配線板片側に熱可塑性樹脂液を塗布し、ま
たは熱可塑性樹脂シ−トまたはフィルム（例えば、熱融
着性ポリイミドフィルム）をラミネ−トし、あるいは半
導体チップと補助配線板片との間に熱可塑性樹脂シ−ト
またはフィルムを介在させて半導体チップと補助配線板
片との金属バンプ接続を行うと共にその接続時の熱で熱
可塑性樹脂層または熱可塑性樹脂シ−トまたはフィルム
を溶融させて半導体チップと補助配線板片との間を熱可
塑性樹で封止することもできる。半導体チップと補助配
線板片との間の封止に使用する樹脂の材質には、半導体
チップ並びに補助配線板片に対する密着力、絶縁性、腐
食性イオンレベルの要件を満たすものが選定されること
は云うまでもない。After mounting the semiconductor chip 1 on the auxiliary wiring board piece 2 in this manner, as shown in FIG. 3C, the liquid resin 3 is provided between the semiconductor chip 1 and the auxiliary wiring board piece 2. , For example, by injection of liquid epoxy resin.
Instead of this resin injection sealing, prior to metal bump connection between the semiconductor chip and the auxiliary wiring board piece, a thermoplastic resin liquid is applied to the semiconductor chip side or the auxiliary wiring board piece side, or a thermoplastic resin sheet or Laminating a film (for example, a heat-fusible polyimide film), or interposing a thermoplastic resin sheet or film between the semiconductor chip and the auxiliary wiring board piece, the semiconductor chip and the auxiliary wiring board piece It is also possible to perform the metal bump connection and to melt the thermoplastic resin layer or the thermoplastic resin sheet or film by the heat at the time of connection to seal between the semiconductor chip and the auxiliary wiring board piece with the thermoplastic resin. . The resin material used for sealing between the semiconductor chip and the auxiliary wiring board piece should be selected so as to meet the requirements for adhesion, insulation, and corrosive ion level to the semiconductor chip and auxiliary wiring board piece. Needless to say.
【００２０】このようにして半導体チップと補助配線板
片との間を封止したのちは、図３の（リ）に示すよう
に、半導体チップ１の電極側とは反対側の全面若しくは
周囲部及び半導体チップ１の側面並びに上記補助配線板
片２の端部にわたって熱接着性のシ−トまたはフィルム
４を熱圧着し、半導体チップ１の外面側を封止する。最
後に図１に示す、外側電極２２の充填金属端面上にはん
だバンプ２２３を形成し、これにて半導体装置のパッケ
−ジ工程までの製作を終了する。After the space between the semiconductor chip and the auxiliary wiring board piece is sealed in this way, as shown in FIG. 3L, the entire surface of the semiconductor chip 1 on the side opposite to the electrode side or the peripheral portion. Then, a heat-adhesive sheet or film 4 is thermocompression bonded over the side surface of the semiconductor chip 1 and the end portion of the auxiliary wiring board piece 2 to seal the outer surface side of the semiconductor chip 1. Finally, solder bumps 223 are formed on the end face of the filled metal of the outer electrode 22 shown in FIG. 1, and the manufacturing up to the package step of the semiconductor device is completed.
【００２１】上記半導体装置の製造手順は、適宜変更で
きることは云うまでもない。例えば、カバ−コ−トを施
したのち、外側電極を形成する前に、半導体チップを接
合し、半導体チップと補助配線板片との間を封止し、し
かるのち、カバ−コ−トに外側電極を形成することも可
能である。なお、上記の実施例では、金属バンプを補助
配線板片の内側電極側に予め形成しているが、半導体チ
ップの電極側に予め形成しておくことも可能である。ま
た、補助配線板片には、引き回し導体２３を絶縁層内に
埋設配線したものを使用しているが、引き回し導体を絶
縁層の内側表面に配線したものを使用することもでき
る。It goes without saying that the manufacturing procedure of the semiconductor device can be changed appropriately. For example, after applying the cover coat and before forming the outer electrode, the semiconductor chips are joined and the gap between the semiconductor chip and the auxiliary wiring board piece is sealed, and then the cover coat is formed. It is also possible to form the outer electrode. In the above embodiment, the metal bump is formed in advance on the inner electrode side of the auxiliary wiring board piece, but it may be formed in advance on the electrode side of the semiconductor chip. Further, the auxiliary wiring board piece is one in which the lead-out conductor 23 is embedded and wired in the insulating layer, but it is also possible to use the one in which the lead-out conductor is provided on the inner surface of the insulating layer.
【００２２】本発明に係る半導体装置は合成樹脂支持フ
ィルムに上記した補助配線板片の配線パタ−ンを長さ方
向に多数箇、縦列にて予め形成しておき、このフィルム
を走行させつつ上記の作業を順次に行うフィルム・キャ
リア方式により製造することが生産能率上有利である。In the semiconductor device according to the present invention, a plurality of wiring patterns of the above-mentioned auxiliary wiring board pieces are preliminarily formed in a longitudinal direction in a longitudinal direction on a synthetic resin supporting film, and while the film is running, the above-mentioned wiring patterns are formed. It is advantageous in terms of production efficiency to manufacture by the film carrier method in which the above work is sequentially performed.
【００２３】[0023]
【作用】補助配線板片２と半導体チップ１との間が図３
の（チ）に示すように、封止樹脂３で接着されただけで
は、加熱・冷却のヒ−トサイクルのもとで補助配線板片
２と半導体チップ１との間のコ−ナに熱応力が集中し、
この箇所に剥離が生じこの剥離箇所を起点として封止樹
脂層３と半導体チップ１との接着界面の剥離が進行して
いき、補助配線板片の電極と半導体チップの電極との導
通不良が発生し易い。しかしながら、本発明に係る半導
体装置においては、半導体チップ１の裏面及び半導体チ
ップ１の側面並びに上記補助配線板片２の端部にわたっ
て熱接着性のシ−ト４を熱圧着しており、補助配線板片
と半導体チップとの間のコ−ナでの熱応力集中剥離を抑
制でき、ヒ−トサイクルのもとでも、後述する実施例と
比較例との熱衝撃試験の対比から確認できる通り、補助
配線板片の電極と半導体チップの電極との導通不良の発
生をよく防止できる。また、熱接着性シ−トと補助配線
板片との熱圧着界面、熱接着性シ−トと半導体チップと
の熱圧着界面のために水密封止性も充分にアップされ
る。従って、トランスファモ−ルド法、キャスティング
法に頼ることなく、充分に信頼性のある封止を保証でき
る。The operation between the auxiliary wiring board piece 2 and the semiconductor chip 1 is shown in FIG.
As shown in (h) of FIG. 3, if the sealing resin 3 is only adhered, heat is applied to the corner between the auxiliary wiring board piece 2 and the semiconductor chip 1 under the heating / cooling heat cycle. Stress is concentrated,
Peeling occurs at this location, and the peeling of the adhesive interface between the sealing resin layer 3 and the semiconductor chip 1 proceeds from this peeling location as a starting point, causing a defective conduction between the electrode of the auxiliary wiring board piece and the electrode of the semiconductor chip. Easy to do. However, in the semiconductor device according to the present invention, the heat-adhesive sheet 4 is thermocompression-bonded to the back surface of the semiconductor chip 1, the side surface of the semiconductor chip 1, and the end portion of the auxiliary wiring board piece 2 to form an auxiliary wiring. It is possible to suppress the thermal stress concentration delamination at the corner between the plate piece and the semiconductor chip, and even under a heat cycle, as can be confirmed from the comparison of the thermal shock test of the example and the comparative example described later, It is possible to prevent the occurrence of defective conduction between the electrode of the auxiliary wiring board piece and the electrode of the semiconductor chip. Further, the water-tight sealing property is sufficiently improved due to the thermocompression bonding interface between the thermoadhesive sheet and the auxiliary wiring board piece and the thermocompression bonding interface between the thermal adhesive sheet and the semiconductor chip. Therefore, a sufficiently reliable sealing can be guaranteed without resorting to the transfer mold method or the casting method.
【００２４】さらに、半導体チップの裏面及び半導体チ
ップの側面並びに上記補助配線板片の端部にわたって熱
圧着する熱接着性シ−トを無機質フィラ−の添加により
パッケ−ジの放熱性を確保でき、無機質フィラ−の多量
添加のもとでも、トランスファモ−ルド法、キャスティ
ング法とは異なり、樹脂の粘性増加・流動性低下に起因
するパッケ−ジ不良（例えば、ボイドの発生）、作業性
低下等の不具合なく、高放熱性のパッケ−ジが可能とな
る。Further, by adding an inorganic filler to the heat-adhesive sheet for thermocompression bonding over the back surface of the semiconductor chip, the side surface of the semiconductor chip and the end portion of the auxiliary wiring board piece, the heat dissipation of the package can be secured. Even when a large amount of inorganic filler is added, unlike the transfer molding method and casting method, poor packaging (for example, generation of voids) due to increased viscosity and decreased fluidity of resin, reduced workability, etc. A package with high heat dissipation can be achieved without any problems.
【００２５】[0025]
〔実施例１〕厚み６０μｍのポリイミドフィルムを支持
フィルムとする補助配線板片（チップよりもやや大）の
内側電極に高さ２０μｍの金バンプを形成し、厚み０．
３７５ｍｍ、一辺の長さが１５．０ｍｍの正方形の信頼
評価用半導体チップを補助配線板片に接続し、これらの
間を液状エポキシ樹脂の注入により封止した。熱接着性
フィルムには、平均粒径２０μｍのアルミナ球状フィラ
−を７０重量％充填した厚み２００μｍの熱可塑性ポリ
イミドフィルム（熱伝導率８．５Ｗ／ｍＫ）を使用し、
この熱接着性フィルムを半導体チップの全裏面及び半導
体チップの側面並びに上記補助配線板片の端部にわたっ
て熱圧着した。 〔実施例２〕実施例１に対し、熱接着性フィルムに平均
粒径１５μｍのシリカ粉末を８０重量％充填した厚み２
００μｍの熱可塑性ポリイミドフィルム（熱伝導率８．
０Ｗ／ｍＫ）を使用した以外、実施例１に同じとした。 〔実施例３〕実施例１に対し、熱接着性フィルムに銀燐
片状フィラ−を３０重量％充填した厚み２００μｍのシ
リコン系熱接着フィルム（熱伝導率５．３Ｗ／ｍＫ）を
使用した以外、実施例１に同じとした。 〔比較例〕実施例に対し、熱接着性フィルムの使用を省
略した。Example 1 A gold bump having a height of 20 μm was formed on an inner electrode of an auxiliary wiring board piece (slightly larger than a chip) using a polyimide film having a thickness of 60 μm as a supporting film, and a thickness of 0.
A square semiconductor chip for reliability evaluation having a length of 375 mm and a side length of 15.0 mm was connected to an auxiliary wiring board piece, and a space between them was sealed by injection of a liquid epoxy resin. As the heat-adhesive film, a thermoplastic polyimide film (thermal conductivity: 8.5 W / mK) having a thickness of 200 μm, which is filled with 70% by weight of an alumina spherical filler having an average particle diameter of 20 μm, is used.
The thermoadhesive film was thermocompression bonded over the entire back surface of the semiconductor chip, the side surface of the semiconductor chip, and the end portion of the auxiliary wiring board piece. [Example 2] In comparison with Example 1, the heat-adhesive film was filled with 80% by weight of silica powder having an average particle size of 15 μm, and the thickness was 2
00 μm thermoplastic polyimide film (heat conductivity 8.
The same as in Example 1 except that 0 W / mK) was used. [Example 3] In contrast to Example 1, except that a 200 μm thick silicon-based heat-adhesive film (thermal conductivity 5.3 W / mK) obtained by filling the heat-adhesive film with 30% by weight of silver flaky filler was used. The same as in Example 1. [Comparative Example] The use of the heat-adhesive film was omitted as compared with the examples.
【００２６】これらの実施例及び比較例につき、１５０
℃〜−５０℃の熱衝撃試験１０００サインクル後での導
通不良率を測定したところ（試料数１０００箇）、実施
例１では０．１％、実施例２では０．３％、実施例３で
は０．５％と低かったのにたいし、比較例では４０％に
も達し、本発明に係る半導体装置において、熱接着性の
シ−トまたはフィルムが封止の信頼性向上に大きく寄与
していることが確認された。For these examples and comparative examples, 150
When the conduction failure rate was measured after 1000 sicles of the thermal shock test of 1000 ° C. to −50 ° C. (1000 samples), it was 0.1% in Example 1, 0.3% in Example 2, and 3 in Example 3. Although it was as low as 0.5%, it reached 40% in the comparative example, and in the semiconductor device according to the present invention, the heat-adhesive sheet or film greatly contributes to the improvement of sealing reliability. Was confirmed.
【００２７】[0027]
【発明の効果】本発明に係る半導体装置においては、半
導体チップ外面側の封止を熱接着性シ−トまたはフィル
ムの熱圧着で行っているにもかかわらず、熱衝撃に対し
充分安定に封止できる。また、熱接着性シ−トまたはフ
ィルムへの無機質フィラ−の多量充填により半導体チッ
プに放熱性に優れたパッケ−ジを優れた作業性で施すこ
とができる。従って、本発明によれば良好なチップスケ
−ルパッケ−ジの半導体装置を提供できる。In the semiconductor device according to the present invention, even though the outer surface of the semiconductor chip is sealed by a heat-adhesive sheet or a thermocompression bonding of a film, it is sufficiently stable against thermal shock. Can be stopped. In addition, the heat-adhesive sheet or the film is filled with a large amount of the inorganic filler, so that the semiconductor chip can be provided with a package having excellent heat dissipation with excellent workability. Therefore, according to the present invention, a good semiconductor device having a chip scale package can be provided.
【図１】本発明に係る半導体装置の一実施例を説明図で
ある。FIG. 1 is an explanatory diagram of an embodiment of a semiconductor device according to the present invention.
【図２】本発明に係る半導体装置の上記とは別の互いに
異なる実施例の要部を示す説明図である。FIG. 2 is an explanatory diagram showing a main part of a different embodiment of the semiconductor device according to the present invention, which is different from the above embodiments.
【図３】本発明に係る半導体装置を製造する場合の作業
手順を示す説明図である。FIG. 3 is an explanatory diagram showing a work procedure for manufacturing a semiconductor device according to the present invention.
【図４】互いに異なる従来のチップサイズの半導体装置
を示す説明図である。FIG. 4 is an explanatory diagram showing semiconductor devices having different conventional chip sizes.
１ 半導体チップ １１ 半導体チップの電極 ２ 補助配線板片 ２１ 内側電極 ２１１ 金属バンプ ２２ 外側電極 ２３ 引き回し導体 ３ 樹脂 ４ 熱接着性シ−トまたはフィルム 1 Semiconductor Chip 11 Electrode of Semiconductor Chip 2 Auxiliary Wiring Board Piece 21 Inner Electrode 211 Metal Bump 22 Outer Electrode 23 Leading Conductor 3 Resin 4 Thermal Adhesive Sheet or Film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉尾 信彦 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 (72)発明者 薄井 英之 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 (72)発明者 伊藤 久貴 大阪府茨木市下穂積１丁目１番２号 日東 電工株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuhiko Yoshio 1-2-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Hideyuki Usui 1-2-1 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Co., Ltd. (72) Inventor Hisaki Ito 1-2, Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation
Claims (5)
と被実装回路板の導体端に接続される外側電極とこれら
の電極間にまたがる引き回し導体とからなる配線パタ−
ンを設けた補助配線板片の内側電極側と半導体チップの
電極とを金属バンプを介して接続し、補助配線板片と半
導体チップとの間を樹脂で封止し、半導体チップの電極
側とは反対側の全面若しくは周囲部及び半導体チップの
側面並びに上記補助配線板片の端部にわたって熱接着性
のシ−トまたはフィルムを熱圧着したことを特徴とする
半導体装置。1. A wiring pattern comprising an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes.
The inner electrode side of the auxiliary wiring board piece provided with the semiconductor chip and the electrode of the semiconductor chip are connected via a metal bump, and the space between the auxiliary wiring board piece and the semiconductor chip is sealed with resin, and the electrode side of the semiconductor chip is connected. Is a semiconductor device in which a heat-adhesive sheet or film is thermocompression-bonded over the entire surface or the peripheral portion on the opposite side, the side surface of the semiconductor chip, and the end portion of the auxiliary wiring board piece.
片面に熱圧着性層を有する複合体を使用し、この熱圧着
性層において熱圧着した請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a composite having a thermocompression bonding layer on one surface of a base material is used for a thermoadhesive sheet or film, and the thermocompression bonding layer is used for thermocompression bonding.
量％以上の無機質フィラ−を含有する請求項１または２
記載の半導体装置。3. A heat-adhesive sheet or film containing 70% by weight or more of an inorganic filler.
13. The semiconductor device according to claim 1.
２．５Ｗ／ｍＫ以上の熱伝導率を有する請求項１記載乃
至３記載の半導体装置。4. The semiconductor device according to claim 1, wherein the heat-adhesive sheet or film has a thermal conductivity of 2.5 W / mK or more at room temperature.
平面寸法にほぼ等しいか、半導体チップの平面寸法の２
００％以下である請求項１記載乃至４記載の半導体装
置。5. The size of the auxiliary wiring board piece is approximately equal to the plane dimension of the semiconductor chip, or 2 the plane dimension of the semiconductor chip.
The semiconductor device according to any one of claims 1 to 4, wherein the content is 00% or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16139995A JPH08335606A (en) | 1995-06-05 | 1995-06-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16139995A JPH08335606A (en) | 1995-06-05 | 1995-06-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08335606A true JPH08335606A (en) | 1996-12-17 |
Family
ID=15734362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16139995A Pending JPH08335606A (en) | 1995-06-05 | 1995-06-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08335606A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6175151B1 (en) | 1997-01-23 | 2001-01-16 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| KR100345075B1 (en) * | 1999-12-16 | 2002-07-20 | 주식회사 하이닉스반도체 | Chip size package |
| US6469382B1 (en) | 2000-01-28 | 2002-10-22 | Nec Corporation | Semiconductor device substrate and method of manufacturing semiconductor device |
-
1995
- 1995-06-05 JP JP16139995A patent/JPH08335606A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6175151B1 (en) | 1997-01-23 | 2001-01-16 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| US6414382B1 (en) | 1997-01-23 | 2002-07-02 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device and method of manufacturing the same, mounted board, and electronic instrument |
| US6646338B2 (en) | 1997-01-23 | 2003-11-11 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| KR100345075B1 (en) * | 1999-12-16 | 2002-07-20 | 주식회사 하이닉스반도체 | Chip size package |
| US6469382B1 (en) | 2000-01-28 | 2002-10-22 | Nec Corporation | Semiconductor device substrate and method of manufacturing semiconductor device |
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