JP2000269269A - Semiconductor mounting substrate, semiconductor device and manufacture thereof - Google Patents
Semiconductor mounting substrate, semiconductor device and manufacture thereofInfo
- Publication number
- JP2000269269A JP2000269269A JP6904199A JP6904199A JP2000269269A JP 2000269269 A JP2000269269 A JP 2000269269A JP 6904199 A JP6904199 A JP 6904199A JP 6904199 A JP6904199 A JP 6904199A JP 2000269269 A JP2000269269 A JP 2000269269A
- Authority
- JP
- Japan
- Prior art keywords
- conductive bump
- semiconductor
- connection terminal
- bump
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子のフリ
ップチップ実装用の基板と、半導体素子がフリップチッ
プ実装された半導体装置、およびそのような半導体装置
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for flip-chip mounting a semiconductor element, a semiconductor device on which a semiconductor element is flip-chip mounted, and a method for manufacturing such a semiconductor device.
【０００２】[0002]
【従来の技術】従来から、無線カードあるいは携帯電話
等の移動通信機器においては、半導体チップやコンデン
サ、抵抗のような多数の電子部品が基板に搭載・実装さ
れた半導体装置（マルチチップモジュール）が使用され
ている。そして、これら半導体チップ等の実装には、フ
リップチップ接続の技術が用いられている。2. Description of the Related Art Conventionally, in a mobile communication device such as a wireless card or a mobile phone, a semiconductor device (multi-chip module) in which a large number of electronic components such as a semiconductor chip, a capacitor, and a resistor are mounted and mounted on a substrate. It is used. For mounting these semiconductor chips and the like, flip-chip connection technology is used.
【０００３】フリップチップ接続は、半導体チップを配
線基板に対して電極端子形成面を下向き（以下、フェー
スダウンと示す。）にして搭載し、半導体チップの電極
端子と配線基板の接続端子とを突起電極（バンプ）を介
して接続する方法である。バンプとしては、金、はん
だ、銅などのバンプが用いられ、特に材料コストが安
く、形成および端子との接合が容易なバンプとして、銅
バンプが有望視されている。すなわち、配線基板の接続
端子上に、電気メッキ、印刷等の方法で銅バンプを形成
することが行なわれている。通常、配線基板の接続端子
は銅で構成されているので、バンプと接続端子とは一体
化される。In flip-chip connection, a semiconductor chip is mounted on a wiring board with an electrode terminal forming surface facing downward (hereinafter, referred to as face-down), and the electrode terminals of the semiconductor chip and the connection terminals of the wiring board are projected. This is a method of connecting via electrodes (bumps). As the bump, a bump made of gold, solder, copper, or the like is used. In particular, a copper bump is promising as a bump having a low material cost and being easy to form and join with a terminal. That is, copper bumps are formed on connection terminals of a wiring board by a method such as electroplating or printing. Normally, since the connection terminals of the wiring board are made of copper, the bumps and the connection terminals are integrated.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな銅バンプによりフリップチップ接続された半導体装
置では、金バンプを使用したものに比べて、材料コスト
が安くバンプの形成並びに端子との接合が容易で、接続
時間の短縮が可能である反面、以下に示す問題があっ
た。すなわち、半導体チップのアルミニウムから成る電
極端子と銅バンプとの接合後の抵抗値（初期抵抗値）
が、数１０ｍΩ（５０ｍΩ程度）と高くなるものがあ
り、携帯電話等の移動通信機器に安定して用いることが
難しかった。However, in a semiconductor device which is flip-chip connected by such a copper bump, the material cost is lower and the formation of the bump and the bonding to the terminal are easier than those using a gold bump. Although the connection time can be shortened, there are the following problems. That is, the resistance value (initial resistance value) after bonding between the electrode terminal made of aluminum of the semiconductor chip and the copper bump.
However, in some cases, it is as high as several tens of mΩ (about 50 mΩ), and it has been difficult to stably use the mobile communication device such as a mobile phone.
【０００５】そして、本発明者が、半導体チップのＡｌ
電極端子と銅バンプとの接合界面を観察したところ、コ
ンタクト抵抗値が数１０ｍΩと高いものでは、平らで滑
らかな銅バンプの先端面が、電極上に形成された酸化Ａ
ｌの膜を介してＡｌ電極に圧接されており、銅バンプと
Ａｌ電極端子とが直接接触していないことがわかった。
これに対して、コンタクト抵抗値が数ｍΩと低いもので
は、銅バンプの表面が光沢がなくて荒れており、このよ
うな銅バンプが、半導体チップのＡｌ電極端子と酸化膜
を介することなく直接接触し、合金層が形成されている
ことがわかった。[0005] Then, the present inventor has proposed that the semiconductor chip Al
Observation of the bonding interface between the electrode terminal and the copper bump revealed that when the contact resistance value was as high as several tens of mΩ, the flat and smooth tip end of the copper bump formed the oxide A formed on the electrode.
It was found that the copper bump and the Al electrode terminal were not in direct contact with each other because the electrode was in pressure contact with the Al electrode via the film l.
On the other hand, when the contact resistance is as low as several mΩ, the surface of the copper bump is dull and rough, and such a copper bump is directly formed without passing through the Al electrode terminal of the semiconductor chip and the oxide film. It came into contact, and it was found that an alloy layer had been formed.
【０００６】本発明はこのような知見に鑑みてなされた
もので、半導体素子の電極端子とバンプとの接合部（界
面）のコンタクト抵抗値が低く、電気特性の良好なフリ
ップチップ実装型半導体装置と、その製造方法、および
このような低い電気抵抗値を可能とする半導体素子のフ
リップチップ実装用基板を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of such findings, and has a low contact resistance value at a junction (interface) between an electrode terminal of a semiconductor element and a bump, and a flip-chip mounted semiconductor device having good electric characteristics. It is another object of the present invention to provide a method for manufacturing the same, and a flip-chip mounting substrate for a semiconductor element which enables such a low electric resistance value.
【０００７】[0007]
【課題を解決するための手段】本発明の第１の発明の半
導体実装用基板は、絶縁基板と、前記絶縁基板の少なく
とも一方の主面に配設された接続端子および配線層と、
前記接続端子上に一体に形成された導電性バンプとを備
え、前記絶縁基板の前記接続端子形成面上に、前記導電
性バンプを介して、半導体素子が搭載・接続される半導
体実装用基板において、前記導電性バンプの前記半導体
素子の電極端子に当接される面が、微小な凹凸を有する
粗面となっていることを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor mounting substrate comprising: an insulating substrate; connecting terminals and a wiring layer disposed on at least one main surface of the insulating substrate;
A conductive bump integrally formed on the connection terminal, wherein the semiconductor element is mounted and connected on the connection terminal formation surface of the insulating substrate via the conductive bump. The surface of the conductive bump contacting the electrode terminal of the semiconductor element is a rough surface having minute irregularities.
【０００８】本発明の第２の発明の半導体装置は、少な
くとも一方の主面に配線層および接続端子を有する配線
基板と、前記配線基板の前記接続端子上に一体に形成さ
れた導電性バンプと、前記配線基板の前記接続端子形成
面上にフェースダウンで搭載され、前記導電性バンプを
介して接続された半導体素子と、前記配線基板と半導体
素子との間隙部に形成された樹脂充填層とを備え、前記
導電性バンプが前記半導体素子の電極端子と、酸化膜を
介することなく直接接触し、接合一体化していることを
特徴とする。According to a second aspect of the present invention, there is provided a semiconductor device having a wiring board having a wiring layer and a connection terminal on at least one main surface, and a conductive bump integrally formed on the connection terminal of the wiring board. A semiconductor element mounted face-down on the connection terminal forming surface of the wiring board and connected via the conductive bumps; and a resin filling layer formed in a gap between the wiring board and the semiconductor element. Wherein the conductive bumps are in direct contact with the electrode terminals of the semiconductor element without an oxide film interposed therebetween to be integrally joined.
【０００９】本発明の第３の発明の半導体装置の製造方
法は、少なくとも一方の主面に配線層および接続端子を
有する配線基板の前記接続端子上に、メッキにより導電
性バンプを形成する工程と、前記配線基板の前記接続端
子形成面上に半導体素子をフェースダウンで搭載し、該
半導体素子の電極端子と前記接続端子とを、前記導電性
バンプを介して接続するフリップチップ接続工程と、前
記配線基板と半導体素子との間隙部を充填する樹脂充填
層を形成する工程とを備え、前記導電性バンプの形成工
程で、メッキ液の組成を調整することにより、粗面化さ
れた表面を有する導電性バンプを形成し、かつフリップ
チップ接続工程で、前記導電性バンプの粗面化された表
面により、前記半導体素子の電極端子上に形成された酸
化膜を破壊し、該導電性バンプを前記電極端子に接触さ
せて接合することを特徴とする。A method of manufacturing a semiconductor device according to a third aspect of the present invention includes the steps of: forming a conductive bump by plating on the connection terminal of a wiring board having a wiring layer and a connection terminal on at least one main surface; A flip-chip connecting step of mounting a semiconductor element face down on the connection terminal forming surface of the wiring substrate, and connecting an electrode terminal of the semiconductor element and the connection terminal via the conductive bump; Forming a resin-filled layer that fills a gap between the wiring board and the semiconductor element, wherein the step of forming the conductive bump has a roughened surface by adjusting the composition of a plating solution. Forming a conductive bump, and in a flip chip connection step, destroying an oxide film formed on an electrode terminal of the semiconductor element by a roughened surface of the conductive bump; Characterized by joining the conductive bump is brought into contact with the electrode terminals.
【００１０】ここで、粗面化された表面を有する導電性
バンプを形成するには、導電性バンプの形成工程で、例
えば、光沢剤を含まないメッキ液を用いてメッキを行な
う方法が採られる。Here, in order to form a conductive bump having a roughened surface, a method of performing plating using, for example, a plating solution containing no brightener in a step of forming the conductive bump is employed. .
【００１１】本発明の第４の発明の半導体装置の製造方
法は、少なくとも一方の主面に配線層および接続端子を
有する配線基板の前記接続端子上に、導電性バンプを形
成する工程と、前記導電性バンプの表面をエッチングに
より粗面化する工程と、前記配線基板の前記接続端子形
成面上に半導体素子をフェースダウンで搭載し、前記導
電性バンプの粗面化された表面により、前記半導体素子
の電極端子上に形成された酸化膜を破壊し、該導電性バ
ンプを前記電極端子に接触させて接合する工程と、前記
配線基板と半導体素子との間隙部を充填するに樹脂充填
層を形成する工程とを備えたことを特徴とする。According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a conductive bump on the connection terminal of a wiring board having a wiring layer and a connection terminal on at least one main surface; Roughening the surface of the conductive bump by etching; mounting a semiconductor element face down on the connection terminal forming surface of the wiring board; and forming the semiconductor by the roughened surface of the conductive bump. Destroying an oxide film formed on the electrode terminals of the device, contacting the conductive bumps with the electrode terminals and joining them, and filling a gap between the wiring board and the semiconductor device with a resin filling layer. And a step of forming.
【００１２】本発明において、導電性バンプとしては、
銅バンプを使用することが望ましいが、銅バンプ上にニ
ッケルメッキが施されたバンプにおいても、Ｎｉメッキ
層の表面を粗面化することによって、同様な効果を上げ
ることができる。銅バンプの形成は、銅の電解メッキ、
または銅粒子を主成分とするペーストを接続端子上に印
刷塗布する方法により行なうことができる。In the present invention, as the conductive bump,
Although it is desirable to use a copper bump, a similar effect can be obtained also in a bump in which a nickel plating is applied on a copper bump by roughening the surface of the Ni plating layer. Copper bumps are formed by electrolytic plating of copper,
Alternatively, it can be performed by a method of printing and applying a paste containing copper particles as a main component on the connection terminal.
【００１３】そして、このような導電性バンプの粗面の
粗さ（表面粗さＲ）は、粗面の微小な凹凸により、半導
体素子の電極端子上の酸化膜を容易に破砕し、かつバン
プの先端面と電極端子との間で十分な接触面積が確保さ
れるように、 0.5± 0.3μmとすることが望ましい。The roughness (surface roughness R) of the rough surface of the conductive bump is such that the oxide film on the electrode terminal of the semiconductor element is easily crushed due to the minute unevenness of the rough surface. It is desirable that the thickness be 0.5 ± 0.3 μm so that a sufficient contact area is secured between the tip surface of the electrode and the electrode terminal.
【００１４】本発明においては、導電性バンプの半導体
素子の電極端子に当接される面が、微小な凹凸を有する
粗面となっているので、このようなバンプの先端面を、
半導体素子のＡｌ電極端子に圧接する（例えば、バンプ
１個当り150gf の圧力をかけながら 150℃で40秒間加
熱）と、粗面の微小な凹凸が、Ａｌ電極端子上に形成さ
れた薄い酸化Ａｌ膜を破壊するため、バンプがＡｌ電極
に直接接触し、導電性の高い合金層が形成される。その
結果、半導体素子のＡｌ電極端子と導電性バンプとの接
合部のコンタクト抵抗値（初期抵抗値）が、数ｍΩに低
減される。In the present invention, since the surface of the conductive bump which is in contact with the electrode terminal of the semiconductor element is a rough surface having minute irregularities, the tip surface of such a bump is
When pressed against the Al electrode terminal of the semiconductor element (for example, heated at 150 ° C. for 40 seconds while applying a pressure of 150 gf per bump), fine irregularities on the rough surface are formed on the thin Al oxide terminal. In order to break the film, the bump directly contacts the Al electrode, and a highly conductive alloy layer is formed. As a result, the contact resistance value (initial resistance value) at the junction between the Al electrode terminal of the semiconductor element and the conductive bump is reduced to several mΩ.
【００１５】また、本発明において、樹脂充填層は、半
導体素子と配線基板とのフリップチップ接続部を接着・
固定する機能を有する。この樹脂充填層の形成は、フリ
ップチップ接続工程の前に行ない、配線基板のバンプ形
成面上に樹脂充填層を形成した後、その上に半導体素子
を搭載し、フリップチップ接続を行なっても良いが、半
導体素子を配線基板上に搭載し、バンプを介して接合し
た後、配線基板と半導体素子との間隙部に液状の樹脂を
注入・充填し、硬化させるように構成しても良い。In the present invention, the resin-filled layer is used for bonding and connecting the flip-chip connection portion between the semiconductor element and the wiring board.
Has the function of fixing. This resin-filled layer may be formed before the flip-chip connection step, and after forming the resin-filled layer on the bump formation surface of the wiring board, a semiconductor element may be mounted thereon and flip-chip connection may be performed. However, after the semiconductor element is mounted on the wiring board and bonded via bumps, a liquid resin may be injected and filled into the gap between the wiring board and the semiconductor element, and may be cured.
【００１６】さらに、このような樹脂充填層を、樹脂中
に直径 5μm 程度の金属粒子（例えば金粒子）が含有さ
れた異方性導電ペーストにより形成することができる。
充填用樹脂として金粒子を含む異方性導電ペーストを使
用する場合には、これを配線基板のバンプ形成面上に塗
布した後、フリップチップ接続を行なうことにより、導
電性バンプと半導体素子のＡｌ電極端子との間に金粒子
が挟み込まれて、Ａｌ−Ａｕ接合が形成されるので、バ
ンプ接合部のコンタクト抵抗値がさらに低減される。Further, such a resin-filled layer can be formed of an anisotropic conductive paste containing metal particles (for example, gold particles) having a diameter of about 5 μm in the resin.
When an anisotropic conductive paste containing gold particles is used as a filling resin, the paste is applied on the bump forming surface of the wiring board, and then the conductive bump is connected to the Al of the semiconductor element by flip-chip connection. Since the gold particles are interposed between the electrode terminals and the Al-Au junction is formed, the contact resistance value of the bump junction is further reduced.
【００１７】[0017]
【発明の実施の形態】以下、本発明の実施例を図面に基
づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１８】図１は、本発明の半導体実装用基板の一実
施例を示す断面図であり、図２は、半導体装置の実施例
を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor mounting substrate according to the present invention, and FIG. 2 is a sectional view showing an embodiment of a semiconductor device.
【００１９】図１において、符号１は、エポキシ樹脂含
浸ガラスクロス基板のような絶縁基板を示し、この絶縁
基板１の少なくとも一方の主面に、銅の蒸着・パターニ
ングや銅箔のフォトエッチング等の方法で、接続パッド
２ａおよび配線層２が形成されている。また、接続パッ
ド２ａ上に、銅バンプ３が一体に形成されている。この
銅バンプ３において、半導体チップの電極端子に当接さ
れる面である上面は、表面粗さ（Ｒ）が約 0.5μm の粗
面３ａとなっている。In FIG. 1, reference numeral 1 denotes an insulating substrate such as an epoxy resin-impregnated glass cloth substrate. At least one main surface of the insulating substrate 1 is formed by vapor deposition and patterning of copper or photo etching of copper foil. By the method, the connection pad 2a and the wiring layer 2 are formed. Further, the copper bumps 3 are integrally formed on the connection pads 2a. In this copper bump 3, the upper surface, which is the surface that comes into contact with the electrode terminals of the semiconductor chip, is a rough surface 3a having a surface roughness (R) of about 0.5 μm.
【００２０】実施例の半導体装置は、このような実装用
配線基板の接続パッド２ａ形成面に、半導体チップ４が
フリップチップ実装された構造となっている。すなわ
ち、図２に示すように、配線基板の接続パッド２ａ形成
面上に、半導体チップ４がフェースダウンに搭載され、
接続パッド２ａ上に形成された銅バンプ３が、半導体チ
ップ４のＡｌ電極端子４ａに圧接されている。このと
き、銅バンプ３の粗面３ａが、加圧により、半導体チッ
プ４のＡｌ電極端子４ａ上に形成された薄い酸化Ａｌ膜
（図示を省略。）を破壊し、銅バンプ３とＡｌ電極端子
４ａとが直接接触するので、電気的に良好な接合部が形
成されている。さらに、このように搭載・実装された半
導体チップ４と配線基板との間の間隙部には、エポキシ
樹脂等の絶縁樹脂の充填層５が形成されている。The semiconductor device of the embodiment has a structure in which the semiconductor chip 4 is flip-chip mounted on the connection pad 2a forming surface of such a wiring board for mounting. That is, as shown in FIG. 2, the semiconductor chip 4 is mounted face down on the connection pad 2a forming surface of the wiring board,
The copper bumps 3 formed on the connection pads 2a are pressed against the Al electrode terminals 4a of the semiconductor chip 4. At this time, the rough surface 3a of the copper bump 3 breaks the thin Al oxide film (not shown) formed on the Al electrode terminal 4a of the semiconductor chip 4 by pressing, and the copper bump 3 and the Al electrode terminal 4a is in direct contact, so that an electrically good joint is formed. Further, a filling layer 5 of an insulating resin such as an epoxy resin is formed in a gap between the semiconductor chip 4 mounted and mounted in this way and the wiring board.
【００２１】このような半導体装置を製造する方法の実
施例を、以下に示す。An embodiment of a method for manufacturing such a semiconductor device will be described below.
【００２２】第１の実施例のプロセスフローを、図３に
示す。FIG. 3 shows a process flow of the first embodiment.
【００２３】第１の実施例では、少なくとも一方の主面
に、銅の接続パッドおよび配線層がそれぞれ形成された
ガラス−エポキシ配線基板の主面に、まずフォトレジス
ト層を積層・形成する。フォトレジストとしては、例え
ばデュポン社製のドライフィルム（厚さ50μm ）を使用
し、このドライフィルムを、真空ラミネータにより60
℃、25秒間の条件でラミネートする。In the first embodiment, a photoresist layer is first laminated and formed on the main surface of a glass-epoxy wiring board on which copper connection pads and wiring layers are formed on at least one main surface. As a photoresist, for example, a dry film (thickness: 50 μm) manufactured by DuPont is used.
Laminate at 25 ° C for 25 seconds.
【００２４】次いで、こうして配線基板上に積層された
フォトレジスト層の上に、露光用マスクを重ね合わせた
後、露光機にセットし、例えば35mJの紫外線を照射して
露光する。続いて、必要に応じてオーブンに入れて加熱
する（60℃で 6分間）ことにより、硬化を完全なものと
した後、炭酸ナトリウム水溶液をスプレイして現像す
る。Then, after an exposure mask is superimposed on the photoresist layer thus laminated on the wiring substrate, the exposure mask is set, and exposure is performed by irradiating, for example, 35 mJ of ultraviolet rays. Subsequently, if necessary, the solution is placed in an oven and heated (at 60 ° C. for 6 minutes) to complete the curing, and then developed by spraying with an aqueous solution of sodium carbonate.
【００２５】次に、こうして所定のフォトレジストパタ
ーンが積層・形成された配線基板に対して、超音波洗
浄、脱脂、純水での洗浄等のメッキ前処理を行なう。具
体的には、例えば純水で 3分間超音波洗浄してから、洗
浄液で50℃ 5分間脱脂し、純水で洗浄した後、ソフトエ
ッチング液に浸漬して 1分間超音波洗浄し、純水で洗浄
する。さらに、希硫酸で30秒間超音波洗浄する。Next, a pre-plating process such as ultrasonic cleaning, degreasing, and cleaning with pure water is performed on the wiring substrate on which the predetermined photoresist pattern is laminated and formed. Specifically, for example, after ultrasonic cleaning with pure water for 3 minutes, degreased with a cleaning solution at 50 ° C. for 5 minutes, washed with pure water, immersed in a soft etching solution and ultrasonically cleaned for 1 minute, Wash with. Further, ultrasonic cleaning is performed with dilute sulfuric acid for 30 seconds.
【００２６】次いで、メッキ槽に入れ、光沢剤を含まな
いメッキ液を用いて電解メッキを行ない、配線基板の接
続パッド上に、粗面化された表面を有する銅バンプを形
成する。ここで、メッキ液の組成は、ＣｕＳＯ4 （５Ｈ
2 Ｏ） 58.9g/l、89％Ｈ2 ＳＯ4 225g/l、1mol/lＨＣｌ
1.4ml、ＣＬＸ−Ｃ（メルテックス社製のレベラー）20
ml/lとし、逆メッキを15mAで 1分間行なった後、電解メ
ッキを50mAで40分間行ない、最後に純水で洗浄する。Next, the resultant is placed in a plating bath, and electrolytic plating is performed using a plating solution containing no brightener to form a copper bump having a roughened surface on the connection pad of the wiring board. Here, the composition of the plating solution is CuSO 4 (5H
2 O) 58.9 g / l, 89% H 2 SO 4 225 g / l, 1 mol / l HCl
1.4 ml, CLX-C (Meltex leveler) 20
After performing reverse plating at 15 mA for 1 minute at 50 ml / l, perform electrolytic plating at 50 mA for 40 minutes, and finally wash with pure water.
【００２７】こうして、配線基板の接続パッド上に、粗
面化された表面（表面粗さ（Ｒ）約0.5μm ）を有す
る、例えば直径75μm 、高さ30μm の銅バンプが形成さ
れる。次に、防錆剤液への浸漬次いで純水洗浄の後処理
を行なった後、水酸化ナトリウム水溶液により、ドライ
フィルム（フォトレジストパターン）を剥離する。In this manner, copper bumps having a roughened surface (surface roughness (R) of about 0.5 μm), for example, a diameter of 75 μm and a height of 30 μm are formed on the connection pads of the wiring board. Next, after immersion in a rust inhibitor solution and post-treatment of washing with pure water, the dry film (photoresist pattern) is peeled off with an aqueous sodium hydroxide solution.
【００２８】次いで、得られた実装用の配線基板の銅バ
ンプ形成面に、エポキシ系の封止用樹脂を塗布した後、
その上に半導体チップをフェースダウンにして搭載し、
Ａｌ電極端子を銅バンプの粗面化された上面に当接させ
る。そして、加圧しながら加熱し、銅バンプを半導体チ
ップの電極端子に直接接触させて接合する。加熱・加圧
力は、例えばバンプ１個当り150gf の圧力をかけなが
ら、 150℃で40秒間加熱するものとする。Next, an epoxy-based sealing resin is applied to the copper bump forming surface of the obtained wiring board for mounting.
Mount the semiconductor chip face down on it,
The Al electrode terminal is brought into contact with the roughened upper surface of the copper bump. Then, heating is performed while applying pressure, and the copper bumps are brought into direct contact with the electrode terminals of the semiconductor chip for bonding. The heating and pressing force is, for example, heating at 150 ° C. for 40 seconds while applying a pressure of 150 gf per bump.
【００２９】このように構成される第１の実施例におい
ては、配線基板の接続パッド上に銅バンプを形成する工
程で、光沢剤を含まないメッキ液を用いて電解メッキを
行なっているので、表面が滑らかではなく粗面化された
銅バンプが形成される。そして、このような銅バンプ
が、半導体チップのＡｌ電極端子に圧接され、加熱・加
圧により、銅バンプの粗面化された表面が、半導体チッ
プのＡｌ電極端子上に形成された薄いＡｌ酸化膜を破壊
してＡｌ電極端子と直接接触するので、コンタクト抵抗
値（初期抵抗値）が数ｍΩと低く、電気的に良好な接合
部が形成される。In the first embodiment configured as described above, in the step of forming copper bumps on the connection pads of the wiring board, electrolytic plating is performed using a plating solution containing no brightener. Copper bumps having a rough surface instead of a smooth surface are formed. Then, such a copper bump is pressed against the Al electrode terminal of the semiconductor chip, and the roughened surface of the copper bump is heated and pressed to form a thin Al oxide formed on the Al electrode terminal of the semiconductor chip. Since the film is broken and comes into direct contact with the Al electrode terminal, the contact resistance value (initial resistance value) is as low as several mΩ, and an electrically good junction is formed.
【００３０】本発明の製造方法の第２の実施例のプロセ
スフローを、図４に示す。FIG. 4 shows a process flow of a second embodiment of the manufacturing method of the present invention.
【００３１】第２の実施例では、光沢剤を含む通常の組
成のメッキ液を用いて電解メッキを行ない、配線基板の
接続パッド上に、表面が滑らかな銅バンプを形成した
後、ソフトエッチングを行ない、バンプの表面を粗面化
（表面粗さ 0.5μm 程度）する。In the second embodiment, electrolytic plating is performed using a plating solution having a normal composition containing a brightener, and a copper bump having a smooth surface is formed on a connection pad of a wiring board, followed by soft etching. Then, the surface of the bump is roughened (surface roughness is about 0.5 μm).
【００３２】ソフトエッチングの条件は、例えば過硫酸
ソーダを主成分とするソフトエッチング液（三菱ガス化
学社製 NPE-300；含有量98％以上）等に30秒間常温で漬
ける方法が採られる。その他の工程は、第１の実施例と
同一であるので、説明を省略する。As a condition of the soft etching, for example, a method of immersing in a soft etching solution containing sodium persulfate as a main component (NPE-300 manufactured by Mitsubishi Gas Chemical Company; content: 98% or more) at room temperature for 30 seconds is employed. The other steps are the same as those of the first embodiment, and the description is omitted.
【００３３】このように構成される第２の実施例におい
ては、電解メッキによる銅バンプ形成後のソフトエッチ
ング工程で、バンプの表面が粗面化されるので、このよ
うな銅バンプが半導体チップのＡｌ電極端子に圧接され
るとき、加圧により、銅バンプの粗面化された上面が、
半導体チップの電極端子上に形成されたＡｌ酸化膜を破
壊して、Ａｌ電極端子と直接接触する。したがって、コ
ンタクト抵抗値が数ｍΩと低く、電気的に良好な接合部
が形成される。また、電解メッキにより形成される銅バ
ンプの高さにばらつきがなく、一定の高さのバンプを安
定して形成することができるので、より良好な接合部が
得られる。In the second embodiment constructed as described above, the surface of the bump is roughened in the soft etching step after the formation of the copper bump by electrolytic plating. When pressed against the Al electrode terminal, the roughened upper surface of the copper bump is
The Al oxide film formed on the electrode terminal of the semiconductor chip is destroyed and comes into direct contact with the Al electrode terminal. Accordingly, the contact resistance is as low as several mΩ, and an electrically good junction is formed. In addition, since the height of the copper bump formed by the electrolytic plating does not vary and a bump having a constant height can be formed stably, a better joint can be obtained.
【００３４】なお、これらの実施例では、樹脂充填層を
形成するための封止用樹脂として、絶縁性のエポキシ樹
脂が使用されているが、エポキシ樹脂中に直径 5μm 程
度の金粒子が含有された異方性導電ペーストを用いて、
樹脂充填層を形成しても良い。異方性導電ペーストを使
用する場合には、これを配線基板のバンプ形成面上に塗
布した後、フリップチップ実装工程を行なうことによ
り、銅バンプと半導体チップのＡｌ電極端子との間に金
粒子が挟み込まれる。その結果、Ａｌ−Ａｕ接合が形成
され、バンプ接合部のコンタクト抵抗値がさらに低減さ
れる。In these examples, an insulating epoxy resin is used as a sealing resin for forming the resin-filled layer, but gold particles having a diameter of about 5 μm are contained in the epoxy resin. Using an anisotropic conductive paste,
A resin-filled layer may be formed. When using an anisotropic conductive paste, after applying it on the bump forming surface of the wiring board, a flip chip mounting process is performed, so that gold particles are present between the copper bumps and the Al electrode terminals of the semiconductor chip. Is sandwiched. As a result, an Al-Au junction is formed, and the contact resistance value of the bump junction is further reduced.
【００３５】[0035]
【発明の効果】以上の説明から明らかなように、本発明
の実装用基板によれば、半導体素子の電極端子との接合
部（界面）のコンタクト抵抗値を、 1ｍΩ程度に低くす
ることができる。そして、このような実装用基板に半導
体素子をフリップチップ接続した半導体装置によれば、
半導体素子の電極端子とバンプとの接合部のコンタクト
抵抗値が低減され、良好な電気特性が実現される。さら
に、本発明の製造方法によれば、前記したような低い抵
抗値を有するフリップチップ接続部を有する半導体装置
を得ることができる。As is apparent from the above description, according to the mounting substrate of the present invention, the contact resistance at the junction (interface) with the electrode terminal of the semiconductor element can be reduced to about 1 mΩ. . According to a semiconductor device in which a semiconductor element is flip-chip connected to such a mounting substrate,
The contact resistance at the junction between the electrode terminal of the semiconductor element and the bump is reduced, and good electrical characteristics are realized. Further, according to the manufacturing method of the present invention, it is possible to obtain a semiconductor device having a flip-chip connection portion having a low resistance value as described above.
【図１】本発明の半導体実装用基板の一実施例の概略構
成を示す断面図。FIG. 1 is a cross-sectional view illustrating a schematic configuration of an embodiment of a semiconductor mounting substrate according to the present invention.
【図２】本発明の半導体装置の一実施例を概略的に示す
断面図FIG. 2 is a cross-sectional view schematically showing one embodiment of the semiconductor device of the present invention.
【図３】本発明の半導体装置の製造方法の第１の実施例
のプロセスを示すフロー図。FIG. 3 is a flowchart showing a process of the first embodiment of the method for manufacturing a semiconductor device of the present invention.
【図４】本発明の半導体装置の製造方法の第２の実施例
のプロセスを示すフロー図。FIG. 4 is a flowchart showing a process of a second embodiment of the method of manufacturing a semiconductor device according to the present invention.
１………絶縁基板 ２ａ………接続パッド ２………配線層 ３………銅バンプ ３ａ………粗面 ４………半導体チップ ４ａ……Ａｌ電極端子 ５………樹脂充填層 DESCRIPTION OF SYMBOLS 1 ... Insulating board 2a ... Connection pad 2 ... Wiring layer 3 ... Copper bump 3a ... Rough surface 4 ... Semiconductor chip 4a ... Al electrode terminal 5 ... Resin filling layer
Claims (6)
端子および配線層と、 前記接続端子上に一体に形成された導電性バンプとを備
え、 前記絶縁基板の前記接続端子形成面上に、前記導電性バ
ンプを介して、半導体素子が搭載・接続される半導体実
装用基板において、 前記導電性バンプの前記半導体素子の電極端子に当接さ
れる面が、微小な凹凸を有する粗面となっていることを
特徴とする半導体実装用基板。An insulating substrate, comprising: an insulating substrate; a connection terminal and a wiring layer disposed on at least one main surface of the insulating substrate; and a conductive bump integrally formed on the connection terminal. On the connection terminal forming surface of the semiconductor mounting substrate on which a semiconductor element is mounted and connected via the conductive bump, a surface of the conductive bump that is in contact with an electrode terminal of the semiconductor element is A substrate for semiconductor mounting, characterized by having a rough surface having minute irregularities.
が、 0.5± 0.3μm であることを特徴とする請求項１記
載の半導体実装用基板。2. The roughness (R) of the rough surface of the conductive bump.
2. The semiconductor mounting substrate according to claim 1, wherein the thickness is 0.5 ± 0.3 μm. 3.
続端子を有する配線基板と、 前記配線基板の前記接続端子上に一体に形成された導電
性バンプと、 前記配線基板の前記接続端子形成面上にフェースダウン
で搭載され、前記導電性バンプを介して接続された半導
体素子と、 前記配線基板と半導体素子との間隙部に形成された樹脂
充填層とを備え、 前記導電性バンプが前記半導体素子の電極端子と、酸化
膜を介することなく直接接触し、接合一体化しているこ
とを特徴とする半導体装置。3. A wiring board having a wiring layer and a connection terminal on at least one main surface; a conductive bump integrally formed on the connection terminal of the wiring board; and a connection terminal formation surface of the wiring board. A semiconductor element mounted face-down on the top and connected via the conductive bumps; and a resin filling layer formed in a gap between the wiring board and the semiconductor element, wherein the conductive bumps are formed of the semiconductor. A semiconductor device, which is in direct contact with an electrode terminal of an element without an intervening oxide film and is integrally joined.
続端子を有する配線基板の前記接続端子上に、メッキに
より導電性バンプを形成する工程と、 前記配線基板の前記接続端子形成面上に半導体素子をフ
ェースダウンで搭載し、該半導体素子の電極端子と前記
接続端子とを、前記導電性バンプを介して接続するフリ
ップチップ接続工程と、 前記配線基板と半導体素子との間隙部を充填する樹脂充
填層を形成する工程とを備え、 前記導電性バンプの形成工程で、メッキ液の組成を調整
することにより、粗面化された表面を有する導電性バン
プを形成し、 かつフリップチップ接続工程で、前記導電性バンプの粗
面化された表面により、前記半導体素子の電極端子上に
形成された酸化膜を破壊し、該導電性バンプを前記電極
端子に接触させて接合することを特徴とする半導体装置
の製造方法。4. A step of forming a conductive bump by plating on the connection terminal of a wiring board having a wiring layer and a connection terminal on at least one main surface; and forming a semiconductor on the connection terminal formation surface of the wiring board. A flip-chip connection step of mounting the element face down and connecting the electrode terminal of the semiconductor element and the connection terminal via the conductive bump; and a resin filling a gap between the wiring board and the semiconductor element. Forming a filling layer, by forming a conductive bump having a roughened surface by adjusting the composition of the plating solution in the conductive bump forming step, and in the flip chip connecting step. The oxide film formed on the electrode terminal of the semiconductor element is destroyed by the roughened surface of the conductive bump, and the conductive bump is brought into contact with the electrode terminal to make contact therewith. The method of manufacturing a semiconductor device which is characterized in that.
続端子を有する配線基板の前記接続端子上に、導電性バ
ンプを形成する工程と、 前記導電性バンプの表面をエッチングにより粗面化する
工程と、 前記配線基板の前記接続端子形成面上に半導体素子をフ
ェースダウンで搭載し、前記導電性バンプの粗面化され
た表面により、前記半導体素子の電極端子上に形成され
た酸化膜を破壊し、該導電性バンプを前記電極端子に接
触させて接合する工程と、 前記配線基板と半導体素子との間隙部を充填するに樹脂
充填層を形成する工程とを備えたことを特徴とする半導
体装置の製造方法。5. A step of forming a conductive bump on the connection terminal of a wiring substrate having a wiring layer and a connection terminal on at least one main surface, and a step of roughening the surface of the conductive bump by etching. Mounting a semiconductor element face down on the connection terminal forming surface of the wiring substrate, and destroying an oxide film formed on an electrode terminal of the semiconductor element by the roughened surface of the conductive bump. And a step of contacting and joining the conductive bump to the electrode terminal, and a step of forming a resin filling layer to fill a gap between the wiring substrate and the semiconductor element. Device manufacturing method.
から成り、かつこの樹脂充填層を前記配線基板の導電性
バンプ形成面に形成した後、前記フリップチップ接続工
程を行なうことを特徴とする請求項４または５記載の半
導体装置の製造方法。6. The method according to claim 1, wherein the resin-filled layer is made of an anisotropic conductive paste, and the flip-chip connecting step is performed after the resin-filled layer is formed on the conductive bump forming surface of the wiring board. 6. The method for manufacturing a semiconductor device according to claim 4, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6904199A JP2000269269A (en) | 1999-03-15 | 1999-03-15 | Semiconductor mounting substrate, semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6904199A JP2000269269A (en) | 1999-03-15 | 1999-03-15 | Semiconductor mounting substrate, semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000269269A true JP2000269269A (en) | 2000-09-29 |
Family
ID=13391117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6904199A Pending JP2000269269A (en) | 1999-03-15 | 1999-03-15 | Semiconductor mounting substrate, semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000269269A (en) |
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| US6885104B2 (en) * | 1998-10-05 | 2005-04-26 | Kulicke & Soffa Investments, Inc. | Semiconductor copper bond pad surface protection |
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| JP2002324819A (en) * | 2001-04-24 | 2002-11-08 | Matsushita Electric Works Ltd | Ic mounting board and method for manufacturing the same |
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| WO2004097904A2 (en) * | 2003-04-24 | 2004-11-11 | Power-One Limited | System and method of reducing die attach stress and strain |
| WO2004097904A3 (en) * | 2003-04-24 | 2005-01-06 | Power One Ltd | System and method of reducing die attach stress and strain |
| US6946744B2 (en) * | 2003-04-24 | 2005-09-20 | Power-One Limited | System and method of reducing die attach stress and strain |
| DE10353676B4 (en) * | 2003-11-17 | 2007-11-29 | Siemens Ag | Method of making an ultrathin module with rough contacts |
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| US8987901B2 (en) | 2007-11-01 | 2015-03-24 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
| JP2009130095A (en) * | 2007-11-22 | 2009-06-11 | Dainippon Printing Co Ltd | Part built-in wiring board, and manufacturing method for part built-in wiring board |
| JP2011054890A (en) * | 2009-09-04 | 2011-03-17 | Ebara Corp | Bump forming method and bonding method |
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