JPH08320741A - Stand-by and operation control circuit - Google Patents
Stand-by and operation control circuitInfo
- Publication number
- JPH08320741A JPH08320741A JP7149741A JP14974195A JPH08320741A JP H08320741 A JPH08320741 A JP H08320741A JP 7149741 A JP7149741 A JP 7149741A JP 14974195 A JP14974195 A JP 14974195A JP H08320741 A JPH08320741 A JP H08320741A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reference voltage
- terminal
- standby
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Amplifiers (AREA)
- Power Sources (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、携帯機器等に好適な待
機／動作制御回路に係り、特に待機時の消費電流を低減
させた待機／動作制御回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standby / operation control circuit suitable for portable equipment and the like, and more particularly to a standby / operation control circuit having reduced standby current consumption.
【０００２】[0002]
【従来の技術】動作時に正常電圧を印加し、待機時に消
費電流を低減させた回路として、図６に示す回路があ
る。図６において、１は増幅器等の被制御回路であっ
て、信号入力端子１１、信号出力端子１２、電源端子１
３、接地端子１４、基準電圧端子１５、およびスイッチ
端子１６を有する。この被制御回路１は、スイッチ端子
１６が低レベル電圧になると、基準電圧端子１５が高イ
ンピーダンスに切り替り、待機状態になる回路である。2. Description of the Related Art As a circuit in which a normal voltage is applied during operation and current consumption is reduced during standby, there is a circuit shown in FIG. In FIG. 6, reference numeral 1 denotes a controlled circuit such as an amplifier, which has a signal input terminal 11, a signal output terminal 12, and a power supply terminal 1.
3, a ground terminal 14, a reference voltage terminal 15, and a switch terminal 16. The controlled circuit 1 is a circuit in which when the switch terminal 16 has a low level voltage, the reference voltage terminal 15 switches to high impedance and enters a standby state.
【０００３】２は制御信号を入力することによって、被
制御回路１のスイッチ端子１６やスイッチＳ１を制御す
る制御回路である。Ｒ１、Ｒ２は基準電圧端子１５に印
加する基準電圧を設定するための抵抗、Ｃ１はその基準
電圧端子１５に印加する基準電圧を安定化させる（例え
ば車載用機器ではエンジンノイズが電源電圧に重畳され
てその電源電圧が不安定となる。）ためのコンデンサで
ある。Reference numeral 2 is a control circuit for controlling the switch terminal 16 and the switch S1 of the controlled circuit 1 by inputting a control signal. R1 and R2 are resistors for setting the reference voltage applied to the reference voltage terminal 15, and C1 stabilizes the reference voltage applied to the reference voltage terminal 15 (for example, engine noise is superposed on the power supply voltage in in-vehicle equipment). The power supply voltage becomes unstable.)
【０００４】この図６に示す回路では、待機時には、制
御回路２によってスイッチＳ１がオフに制御され、且つ
被制御回路１のスイッチ端子１６が低レベル電圧に設定
される。このときは、上記したように被制御回路１は基
準電圧端子１５が高インピーダンスとなるので待機状態
となり消費電流が低減が図られ、また基準電圧発生のた
めの抵抗Ｒ２には電流が流れず、抵抗Ｒ１にもコンデン
サＣ１の電圧が電源電圧Ｖｃｃに達した以後は電流が流
れず、消費電流の低減が図られる。In the circuit shown in FIG. 6, during standby, the control circuit 2 controls the switch S1 to be turned off, and the switch terminal 16 of the controlled circuit 1 is set to a low level voltage. At this time, as described above, the controlled circuit 1 enters the standby state because the reference voltage terminal 15 has a high impedance, and the current consumption is reduced, and no current flows through the resistor R2 for generating the reference voltage. No current flows through the resistor R1 after the voltage of the capacitor C1 reaches the power supply voltage Vcc, and the consumption current is reduced.
【０００５】次に、動作時には、制御回路２によってス
イッチＳ１がオンに制御され、且つ被制御回路１のスイ
ッチ端子１６に高レベル電圧が印加する。このときは、
被制御回路１は動作状態となり、基準電圧端子１５の電
圧は、電源電圧Ｖｃｃからこれを抵抗Ｒ１、Ｒ２の分割
比で分割した基準電圧に切り替わる。このように、被制
御回路１が待機状態を解除されて動作を開始する。Next, in operation, the switch S1 is controlled to be turned on by the control circuit 2, and a high level voltage is applied to the switch terminal 16 of the controlled circuit 1. At this time,
The controlled circuit 1 enters the operating state, and the voltage of the reference voltage terminal 15 is switched from the power supply voltage Vcc to the reference voltage obtained by dividing the power supply voltage Vcc by the division ratio of the resistors R1 and R2. In this way, the controlled circuit 1 is released from the standby state and starts operating.
【０００６】図７は従来の別の回路例を示す図である。
図６の回路におけるものと同一のものには同一の符号を
付している。図６の回路と異なるところは、抵抗Ｒ２に
スイッチは接続せず、抵抗Ｒ１と電源との間にスイッチ
Ｓ２を接続した点である。このため、待機時に抵抗Ｒ
１、Ｒ２が電源から完全に分離されてその部分の消費電
流が零となり、また基準電圧端子１５に印加する電圧が
接地電位となる。動作時は、基準電圧端子１５の電圧
が、接地電位から電源電圧Ｖｃｃを抵抗Ｒ１、Ｒ２の分
割比で分割した基準電圧に切り替わる。FIG. 7 is a diagram showing another conventional circuit example.
The same components as those in the circuit of FIG. 6 are designated by the same reference numerals. The difference from the circuit of FIG. 6 is that the switch is not connected to the resistor R2, but the switch S2 is connected between the resistor R1 and the power supply. Therefore, the resistance R
1 and R2 are completely separated from the power supply, the current consumption in that portion becomes zero, and the voltage applied to the reference voltage terminal 15 becomes the ground potential. During operation, the voltage of the reference voltage terminal 15 is switched from the ground potential to the reference voltage obtained by dividing the power supply voltage Vcc by the division ratio of the resistors R1 and R2.
【０００７】[0007]
【発明が解決しようとする課題】ところが、上記した図
６、図７に示した回路では、待機状態から動作状態に切
り替わるとき、被制御回路１の基準電圧端子１５の電圧
が正規の基準電圧に達するまでに時間がかかり、その間
その基準電圧が変動し続け、被制御回路１の正常動作が
開始するまで時間かかかる、すなわち、制御回路２に印
加した制御信号に対する応答性が良くないという問題が
ある。However, in the circuits shown in FIGS. 6 and 7 described above, when the standby state is switched to the operating state, the voltage of the reference voltage terminal 15 of the controlled circuit 1 becomes the normal reference voltage. It takes a long time to reach the reference voltage, and the reference voltage keeps fluctuating during that time, and it takes time for the controlled circuit 1 to start normal operation, that is, the response to the control signal applied to the control circuit 2 is not good. is there.
【０００８】本発明の目的は、待機状態から動作状態に
切り替わるとき、これが迅速に行われ、基準電圧端子の
電圧が瞬時に正規の基準電圧に達するようにした待機／
動作制御回路を提供することである。It is an object of the present invention that when switching from the standby state to the operating state, this is done quickly so that the voltage at the reference voltage terminal instantly reaches the normal reference voltage.
It is to provide an operation control circuit.
【０００９】[0009]
【課題を解決するための手段】第１の発明の待機／動作
制御回路は、電源電圧に比例した基準電圧を発生する基
準電圧発生回路と、上記基準電圧が入力される基準電圧
端子、及び内部回路の待機／動作の切り替えを行う制御
信号が入力されるスイッチ端子を有する被制御回路と、
該被制御回路の上記スイッチ端子に上記制御信号を送る
制御回路とを具備する待機／動作制御回路において、上
記被制御回路の上記基準電圧端子と電源との間、及び上
記基準電圧端子と接地との間に各々コンデンサを接続し
て構成した基準電圧安定化回路と、上記基準電圧発生回
路を電源、接地から分離するスイッチ手段とを具備し、
上記制御回路が、上記被制御回路と上記スイッチ手段に
対して待機のための制御信号を送ることより、上記被制
御回路を待機状態にするとともに上記スイッチ手段によ
り上記基準電圧発生回路を上記電源、接地から分離し、
且つ動作のための制御信号を送ることにより上記被制御
回路を動作状態にするとともに上記スイッチ手段により
上記基準電圧発生回路を上記電源、接地に接続するよう
構成した。A standby / operation control circuit according to a first aspect of the present invention includes a reference voltage generation circuit for generating a reference voltage proportional to a power supply voltage, a reference voltage terminal to which the reference voltage is input, and an internal circuit. A controlled circuit having a switch terminal to which a control signal for switching standby / operation of the circuit is input;
A standby / operation control circuit comprising: a control circuit that sends the control signal to the switch terminal of the controlled circuit, wherein a standby / operation control circuit is provided between the reference voltage terminal of the controlled circuit and a power supply, and between the reference voltage terminal and ground. A reference voltage stabilizing circuit configured by connecting a capacitor between each of them, and a switch means for separating the reference voltage generating circuit from a power source and ground.
The control circuit sends a control signal for standby to the controlled circuit and the switch means to put the controlled circuit in a standby state and the switch means to drive the reference voltage generating circuit to the power supply, Isolated from ground,
Further, the control circuit for operation is sent to bring the controlled circuit into the operating state, and the switch means connects the reference voltage generating circuit to the power supply and ground.
【００１０】第２の発明は、第１の発明において、上記
スイッチ手段を半導体素子で構成し、該半導体素子を待
機時に遮断状態となり動作時に内部抵抗が所定値となる
よう上記制御回路で制御し、上記スイッチ手段が上記基
準電圧発生回路を兼用するように構成した。According to a second aspect of the present invention, in the first aspect, the switch means is composed of a semiconductor element, and the semiconductor element is cut off during standby and is controlled by the control circuit so that the internal resistance becomes a predetermined value during operation. The switch means also serves as the reference voltage generating circuit.
【００１１】第３の発明は、第１の発明において、上第
記被制御回路がスイッチ端子の電流の供給／遮断により
内部回路の待機／動作を切り替える回路であって、該ス
イッチ端子への電流の供給／遮断が、上記スイッチ手段
により制御されるように構成した。A third aspect of the present invention is the circuit according to the first aspect, wherein the controlled circuit switches the standby / operation of the internal circuit by supplying / cutting off the current at the switch terminal. The supply / interruption of is controlled by the switch means.
【００１２】[0012]
【作用】第１の発明によれば、待機時に基準電圧発生回
路が電源から分離されるとともに被制御回路が待機状態
となり、消費電流の低減が図られる。待機時から動作時
に切り替わるとき、被制御回路の基準電圧端子の電圧が
基準電圧安定化回路により印加されている電圧から基準
電圧発生回路で決る電圧に変化するが、後者の電圧に落
ち着くまので時間は極めて短く、その切り替わりが迅速
に行われる。According to the first aspect of the present invention, the reference voltage generating circuit is separated from the power supply during standby, and the controlled circuit enters the standby state, thereby reducing current consumption. When switching from standby mode to operating mode, the voltage of the reference voltage terminal of the controlled circuit changes from the voltage applied by the reference voltage stabilization circuit to the voltage determined by the reference voltage generation circuit. Is extremely short, and the switching is quick.
【００１３】第２の発明によれば、スイッチ手段が基準
電圧発生回路を兼用するので、回路構成が単純化され
る。According to the second aspect of the invention, since the switch means also serves as the reference voltage generating circuit, the circuit structure is simplified.
【００１４】第３の発明によれば、スイッチ手段が同時
に被制御回路のスイッチ端子を制御するので、この点で
も回路構成が単純化される。According to the third aspect of the invention, the switch means simultaneously controls the switch terminals of the controlled circuit, so that the circuit configuration is simplified also in this respect.
【００１５】[0015]
【実施例】以下、本発明について説明する。図１はその
原理説明のための図である。前述した図６、図７の回路
におけるものと同一のものには同一の符号を付した。The present invention will be described below. FIG. 1 is a diagram for explaining the principle. The same components as those in the circuits of FIGS. 6 and 7 described above are designated by the same reference numerals.
【００１６】本発明では、基準電圧端子１５に印加する
基準電圧を決める抵抗Ｒ１、Ｒ２（基準電圧発生回路）
に対して、スイッチＳ３、Ｓ４（スイッチ手段）を各々
直列接続するとともに、そのスイッチＳ３と抵抗Ｒ１の
直列回路、スイッチＳ４と抵抗Ｒ２の直列回路に、各々
コンデンサＣ２、Ｃ３（基準電圧安定化回路）を並列接
続している。このコンデンサＣ２、Ｃ３は電源電圧Ｖｃ
ｃに混入するノイズを吸収してその電源電圧Ｖｃｃを安
定化させ、基準電圧端子１５に印加する基準電圧を安定
化させるためのものである。上記スイッチＳ３、Ｓ４は
制御回路２によって制御されている。In the present invention, the resistors R1 and R2 (reference voltage generating circuit) for determining the reference voltage applied to the reference voltage terminal 15 are used.
On the other hand, switches S3 and S4 (switch means) are connected in series, and capacitors C2 and C3 (reference voltage stabilizing circuit) are respectively connected to the series circuit of the switch S3 and the resistor R1 and the series circuit of the switch S4 and the resistor R2. ) Are connected in parallel. The capacitors C2 and C3 have a power supply voltage Vc
This is for absorbing noise mixed in c to stabilize the power supply voltage Vcc, and to stabilize the reference voltage applied to the reference voltage terminal 15. The switches S3 and S4 are controlled by the control circuit 2.
【００１７】この図１に示す回路では、制御回路２によ
り待機のための制御信号を送ることで、基準電圧端子１
５が高インピーダンスとなり、被制御回路１の内部機能
が停止しする。また、スイッチＳ３、Ｓ４がオフする。
以上から消費電流がほぼ零となる。In the circuit shown in FIG. 1, the control circuit 2 sends a control signal for standby to the reference voltage terminal 1.
5 becomes a high impedance, and the internal function of the controlled circuit 1 stops. Further, the switches S3 and S4 are turned off.
From the above, the current consumption becomes almost zero.
【００１８】次に、制御回路２より動作のための制御信
号を送ることで、被制御回路１が機能を開始するととも
に、スイッチＳ３、Ｓ４がオンし、基準電圧端子１５に
抵抗Ｒ１、Ｒ２で決る基準電圧が入力し、動作状態とな
る。Next, by sending a control signal for operation from the control circuit 2, the controlled circuit 1 starts to function, the switches S3 and S4 are turned on, and the resistors R1 and R2 are connected to the reference voltage terminal 15 by the resistors R1 and R2. A predetermined reference voltage is input, and the device enters the operating state.
【００１９】ここで、待機状態から動作状態への移行直
前には、基準電圧端子１５の電位は、コンデンサＣ２、
Ｃ３により電源電圧Ｖｃｃを分割した電圧（抵抗Ｒ１、
Ｒ２で決る基準電圧にほぼ等しい電圧）であるので、動
作状態への移行時にその電圧が変動することはなく、極
めて速やかに抵抗Ｒ１、Ｒ２で決る基準電圧に到達す
る。このため、被制御回路１は瞬時に正常動作を開始す
る。Immediately before the transition from the standby state to the operating state, the potential of the reference voltage terminal 15 changes to the capacitor C2,
A voltage obtained by dividing the power supply voltage Vcc by C3 (resistor R1,
Since the voltage is almost equal to the reference voltage determined by R2), the voltage does not fluctuate during the transition to the operating state, and reaches the reference voltage determined by the resistors R1 and R2 very quickly. Therefore, the controlled circuit 1 instantly starts normal operation.
【００２０】図２は本発明の第１の実施例を示す図であ
る。ここでは、図１に示した被制御回路１として、電流
入力の有無により待機状態／動作状態が切り替えられる
被制御回路４を使用するものである。４１は入力端子、
４２は出力端子、４３は電源端子、４４は接地端子、４
５は基準電圧端子、４６は電流端子（スイッチ端子に相
当する）である。この電流端子４６には、ｐｎｐトラン
ジスタＱ１、Ｑ２からなるカレントミラー回路の当該ト
ランジスタＱ２のコレクタが接続されている。また、ト
ランジスタＱ１のコレクタはスイッチＳ３に接続されて
いる。さらに、抵抗Ｒ１、Ｒ２の共通接続点と基準電源
端子４５との間には抵抗Ｒ３が接続されている。FIG. 2 is a diagram showing a first embodiment of the present invention. Here, as the controlled circuit 1 shown in FIG. 1, the controlled circuit 4 whose standby state / operating state is switched depending on the presence / absence of current input is used. 41 is an input terminal,
42 is an output terminal, 43 is a power supply terminal, 44 is a ground terminal, 4
Reference numeral 5 is a reference voltage terminal, and 46 is a current terminal (corresponding to a switch terminal). The collector of the transistor Q2 of the current mirror circuit composed of the pnp transistors Q1 and Q2 is connected to the current terminal 46. The collector of the transistor Q1 is connected to the switch S3. Further, a resistor R3 is connected between the common connection point of the resistors R1 and R2 and the reference power supply terminal 45.
【００２１】この第１の実施例では、制御端子３に入力
する信号によりスイッチＳ３、Ｓ４をオフさせたとき、
トランジスタＱ１、Ｑ２がオフとなり、被制御回路４は
電流端子４６への電流が絶たれて待機状態となり、基準
電圧端子４５が高インピーダンスとなる。次に、制御端
子３に入力する信号を切り替えてスイッチＳ３、Ｓ４を
オンさせると、トランジスタＱ１、Ｑ２もオンして、被
制御回路４は電流端子４６に電流が供給されて動作状態
となり、また基準電圧端子４５には基準電圧が印加す
る。In the first embodiment, when the switches S3 and S4 are turned off by the signal input to the control terminal 3,
The transistors Q1 and Q2 are turned off, the current to the current terminal 46 is cut off, and the controlled circuit 4 enters the standby state, and the reference voltage terminal 45 becomes high impedance. Next, when the signals input to the control terminal 3 are switched to turn on the switches S3 and S4, the transistors Q1 and Q2 are also turned on, and the controlled circuit 4 is supplied with current to the current terminal 46 to be in an operating state. A reference voltage is applied to the reference voltage terminal 45.
【００２２】図３は第２の実施例を示す図である。これ
は、第１の実施例におけるスイッチＳ３をｐチャンネル
ＦＥＴＱ３、スイッチＳ４をｎチャンネルＦＥＴＱ４に
置換し、さらにｐチャンネルＦＥＴＱ３の制御のために
抵抗Ｒ４とｎチャンネルＦＥＴＱ５を設け、制御端子３
に入力する制御信号を抵抗Ｒ５、Ｒ６で分圧して、ＦＥ
ＴＱ４、Ｑ５のゲートに入力させるようにしたものであ
る。FIG. 3 is a diagram showing a second embodiment. This is because the switch S3 in the first embodiment is replaced with a p-channel FET Q3, the switch S4 is replaced with an n-channel FET Q4, and a resistor R4 and an n-channel FET Q5 are further provided for controlling the p-channel FET Q3, and a control terminal 3 is provided.
The control signal input to is divided by resistors R5 and R6,
The input is made to the gates of TQ4 and Q5.
【００２３】この第２の実施例の回路では、制御端子３
を低レベル電圧にすることによりＦＥＴＱ４、Ｑ５がオ
フし、そのＦＥＴＱ５のオフによりＦＥＴＱ３もオフし
て、トランジスタＱ１、Ｑ２がオフし、被制御回路４は
待機状態となり、抵抗Ｒ１、Ｒ２の電流は零となる。ま
た、制御端子３を高レベル電圧にすることによりＦＥＴ
Ｑ４、Ｑ５がオンし、そのＦＥＴＱ５のオンによりＦＥ
ＴＱ３もオンして、トランジスタＱ１、Ｑ２がオンし動
作状態となる。In the circuit of the second embodiment, the control terminal 3
To a low level voltage turns off the FETs Q4 and Q5, turning off the FET Q5 also turns off the FET Q3, turning off the transistors Q1 and Q2, the controlled circuit 4 enters a standby state, and the currents of the resistors R1 and R2 are It becomes zero. In addition, by setting the control terminal 3 to a high level voltage, the FET
Q4 and Q5 turn on, and FE is turned on by turning on the FET Q5.
TQ3 is also turned on and the transistors Q1 and Q2 are turned on to be in an operating state.
【００２４】図４は第３の実施例を示す図である。これ
は、第２の実施例におけるトランジスタＱ１、Ｑ２をお
のおのｐチャンネルＦＥＴＱ６、Ｑ７に置換するととも
に、基準電圧発生回路の抵抗Ｒ１とスイッチＳ３の機能
をこのＦＥＴＱ６により、抵抗Ｒ２とスイッチＳ４の機
能をｎチャンネルＦＥＴＱ８で実現したものである。他
は第２の実施例のものと同じである。FIG. 4 is a diagram showing a third embodiment. This replaces the transistors Q1 and Q2 in the second embodiment with the p-channel FETs Q6 and Q7, respectively, and the functions of the resistor R1 and the switch S3 of the reference voltage generating circuit are changed to the functions of the resistor R2 and the switch S4 by the FET Q6. This is realized by the n-channel FET Q8. Others are the same as those of the second embodiment.
【００２５】この第３の実施例の回路では、制御端子３
を低レベル電圧にすることによりＦＥＴＱ５〜Ｑ８がオ
フし、待機状態となる。また、制御端子３を高レベル電
圧にすることによりＦＥＴＱ５がオンし、そのＦＥＴＱ
５のオンによりＦＥＴＱ６、Ｑ７もオンして動作状態と
なる。また、ＦＥＴＱ８もオンする。基準電圧端子４５
に印加する基準電圧は、ＦＥＴＱ６とＱ８の内部抵抗に
よって電源電圧Ｖｃｃを分圧した電圧となる。In the circuit of the third embodiment, the control terminal 3
The FETs Q5 to Q8 are turned off by setting the voltage to a low level voltage to enter the standby state. Further, by turning the control terminal 3 to a high level voltage, the FET Q5 is turned on, and the FET Q5 is turned on.
When the switch 5 is turned on, the FETs Q6 and Q7 are also turned on to be in an operating state. Further, the FET Q8 also turns on. Reference voltage terminal 45
The reference voltage applied to is a voltage obtained by dividing the power supply voltage Vcc by the internal resistance of the FETs Q6 and Q8.
【００２６】図５は第４の実施例を示す図である。これ
は、図２に示した第１の実施例のスイッチＳ３をｐｎｐ
トランジスタＱ９により、スイッチＱ４をｎｐｎトラン
ジスタＱ１０により実現し、トランジスタＱ９を駆動す
るためにｎｐｎトランジスタＱ１１を設けたものであ
る。抵抗Ｒ７はトランジスタＱ１１のバイアス用、抵抗
Ｒ８はトランジスタＱ１０のバイアス用である。FIG. 5 is a diagram showing a fourth embodiment. This is because the switch S3 of the first embodiment shown in FIG.
The switch Q4 is realized by the transistor Q9 by the npn transistor Q10, and the npn transistor Q11 is provided to drive the transistor Q9. The resistor R7 is for biasing the transistor Q11, and the resistor R8 is for biasing the transistor Q10.
【００２７】この第４の実施例の回路では、制御端子３
を低レベル電圧にすることによりトランジスタＱ１、Ｑ
２、Ｑ９〜Ｑ１１のすべてがオフし、待機状態となる。
また、制御端子３を高レベル電圧にすることによりそれ
らがすべてオンし、動作状態となる。In the circuit of the fourth embodiment, the control terminal 3
To a low level voltage, the transistors Q1 and Q
2. All of Q9 to Q11 are turned off, and a standby state is set.
Further, by setting the control terminal 3 to a high level voltage, all of them are turned on and become in the operating state.
【００２８】[0028]
【発明の効果】以上説明したように、第１の発明によれ
ば、基準電圧安定化回路を電源と接地間に直列接続され
る２個のコンデンサで構成し、その２個のコンデンサの
共通接続点を被制御回路の基準電圧端子接続したので、
その基準電圧端子に接続される基準電圧発生回路の抵抗
素子の遮断→接続時、その基準電圧端子に印加する電圧
が大きく変化することはなく、待機状態から動作状態に
移行するとき被制御回路の内部の直流電圧が迅速に所定
値に落ち着くようになる。また、第２の発明によれば、
スイッチ手段が基準電圧発生回路を兼用するので、回路
構成が単純化される。さらに第３の発明によれば、スイ
ッチ手段が同時に被制御回路のスイッチ端子を制御する
ので、この点でも回路構成が単純化される。As described above, according to the first aspect of the invention, the reference voltage stabilizing circuit is composed of two capacitors connected in series between the power supply and the ground, and the two capacitors are commonly connected. Since the point was connected to the reference voltage terminal of the controlled circuit,
Interruption of the resistance element of the reference voltage generation circuit connected to the reference voltage terminal → When connecting, the voltage applied to the reference voltage terminal does not change significantly, and when the standby circuit shifts to the operating state The internal DC voltage quickly settles to a predetermined value. According to the second invention,
Since the switch means also serves as the reference voltage generating circuit, the circuit configuration is simplified. Further, according to the third aspect, the switch means simultaneously controls the switch terminals of the controlled circuit, so that the circuit configuration is simplified also in this respect.
【図１】 本発明の原理説明のための待機／動作制御回
路の回路図である。FIG. 1 is a circuit diagram of a standby / operation control circuit for explaining the principle of the present invention.
【図２】 第１の実施例の待機／動作制御回路の回路図
である。FIG. 2 is a circuit diagram of a standby / operation control circuit according to a first embodiment.
【図３】 第２の実施例の待機／動作制御回路の回路図
である。FIG. 3 is a circuit diagram of a standby / operation control circuit according to a second embodiment.
【図４】 第３の実施例の待機／動作制御回路の回路図
である。FIG. 4 is a circuit diagram of a standby / operation control circuit according to a third embodiment.
【図５】 第４の実施例の待機／動作制御回路の回路図
である。FIG. 5 is a circuit diagram of a standby / operation control circuit according to a fourth embodiment.
【図６】 従来の待機／動作制御回路の回路図である。FIG. 6 is a circuit diagram of a conventional standby / operation control circuit.
【図７】 従来の別の例の待機／動作制御回路の回路図
である。FIG. 7 is a circuit diagram of another conventional standby / operation control circuit.
１、４：被制御回路、２：制御回路、３：制御端子。 1, 4: controlled circuit, 2: control circuit, 3: control terminal.
Claims (3)
準電圧発生回路と、上記基準電圧が入力される基準電圧
端子、及び内部回路の待機／動作の切り替えを行う制御
信号が入力されるスイッチ端子を有する被制御回路と、
該被制御回路の上記スイッチ端子に上記制御信号を送る
制御回路とを具備する待機／動作制御回路において、 上記被制御回路の上記基準電圧端子と電源との間、及び
上記基準電圧端子と接地との間に各々コンデンサを接続
して構成した基準電圧安定化回路と、 上記基準電圧発生回路を電源、接地から分離するスイッ
チ手段とを具備し、 上記制御回路が、上記被制御回路と上記スイッチ手段に
対して待機のための制御信号を送ることより、上記被制
御回路を待機状態にするとともに上記スイッチ手段によ
り上記基準電圧発生回路を上記電源、接地から分離し、
且つ動作のための制御信号を送ることにより上記被制御
回路を動作状態にするとともに上記スイッチ手段により
上記基準電圧発生回路を上記電源、接地に接続すること
を特徴とする待機／動作制御回路。1. A reference voltage generation circuit for generating a reference voltage proportional to a power supply voltage, a reference voltage terminal to which the reference voltage is input, and a switch to which a control signal for switching standby / operation of an internal circuit is input. A controlled circuit having a terminal,
A standby / operation control circuit comprising: a control circuit that sends the control signal to the switch terminal of the controlled circuit, wherein the control circuit sends a control signal between the reference voltage terminal and a power source, and between the reference voltage terminal and ground. And a switch means for separating the reference voltage generating circuit from a power source and ground, wherein the control circuit includes the controlled circuit and the switch means. By sending a control signal for standby to, the controlled circuit is placed in a standby state and the reference voltage generating circuit is separated from the power source and ground by the switch means,
A standby / operation control circuit characterized in that the controlled circuit is activated by sending a control signal for operation and the reference voltage generating circuit is connected to the power supply and ground by the switch means.
該半導体素子を待機時に遮断状態となり動作時に内部抵
抗が所定値となるよう上記制御回路で制御し、上記スイ
ッチ手段が上記基準電圧発生回路を兼用するようにした
ことを特徴とする請求項１に記載の待機／動作制御回
路。2. The switch means comprises a semiconductor element,
2. The semiconductor device is controlled by the control circuit so that the semiconductor element is cut off during standby and the internal resistance becomes a predetermined value during operation, and the switch means also functions as the reference voltage generation circuit. The described standby / operation control circuit.
給／遮断により内部回路の待機／動作を切り替える回路
であって、該スイッチ端子への電流の供給／遮断が、上
記スイッチ手段により制御されるようにしたことを特徴
とする請求項１に記載の待機／動作制御回路。3. The controlled circuit is a circuit for switching standby / operation of an internal circuit by supplying / cutting off a current at a switch terminal, and supplying / cutting off a current to the switch terminal is controlled by the switch means. The standby / operation control circuit according to claim 1, wherein the standby / operation control circuit is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14974195A JP3332131B2 (en) | 1995-05-25 | 1995-05-25 | Standby / operation control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14974195A JP3332131B2 (en) | 1995-05-25 | 1995-05-25 | Standby / operation control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08320741A true JPH08320741A (en) | 1996-12-03 |
| JP3332131B2 JP3332131B2 (en) | 2002-10-07 |
Family
ID=15481778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14974195A Expired - Fee Related JP3332131B2 (en) | 1995-05-25 | 1995-05-25 | Standby / operation control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3332131B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1264392A2 (en) * | 2000-02-29 | 2002-12-11 | Brandt Cooking | Switching power supply |
| US8055923B2 (en) | 2007-09-12 | 2011-11-08 | Denso Corporation | Electronic control unit and signal monitoring circuit |
| JP2020030737A (en) * | 2018-08-24 | 2020-02-27 | 株式会社東芝 | Constant voltage circuit |
-
1995
- 1995-05-25 JP JP14974195A patent/JP3332131B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1264392A2 (en) * | 2000-02-29 | 2002-12-11 | Brandt Cooking | Switching power supply |
| US8055923B2 (en) | 2007-09-12 | 2011-11-08 | Denso Corporation | Electronic control unit and signal monitoring circuit |
| JP2020030737A (en) * | 2018-08-24 | 2020-02-27 | 株式会社東芝 | Constant voltage circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3332131B2 (en) | 2002-10-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4371841A (en) | Circuit arrangement for eliminating turn-on and turn-off clicks in an amplifier | |
| JPH10271680A (en) | Power supply circuit | |
| JP3332131B2 (en) | Standby / operation control circuit | |
| JPH04315207A (en) | Power supply circuit | |
| JP2752405B2 (en) | DC power supply | |
| US5757940A (en) | Electric volume controller | |
| JP3859924B2 (en) | Oscillator circuit | |
| JP2984001B2 (en) | Low voltage controlled backup electronics with delayed switch off | |
| US5936390A (en) | Control circuit | |
| JP2615526B2 (en) | Tuner IC | |
| JPH04285999A (en) | Driving circuit for piezoelectric buzzer | |
| JPS5829628Y2 (en) | filter control circuit | |
| JP2690788B2 (en) | Semiconductor device | |
| JPS6240807A (en) | Muting circuit | |
| JPH029371Y2 (en) | ||
| JPS6122345Y2 (en) | ||
| JP2531826Y2 (en) | Power save circuit | |
| JP2710334B2 (en) | Power amplifier | |
| JPH0690523A (en) | Bilateral constant-current circuit | |
| JPH10200389A (en) | Load driving circuit | |
| JPH0542482Y2 (en) | ||
| KR100201254B1 (en) | Power selectively-supply circuit | |
| JPH064162A (en) | Standby circuit | |
| JPH0722935A (en) | Switching circuit | |
| JP2002217693A (en) | Hysteresis circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20020702 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080726 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100726 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110726 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120726 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120726 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130726 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |