JPH08288340A - High density semiconductor device and integrated circuit chip therefor - Google Patents

High density semiconductor device and integrated circuit chip therefor

Info

Publication number
JPH08288340A
JPH08288340A JP7091009A JP9100995A JPH08288340A JP H08288340 A JPH08288340 A JP H08288340A JP 7091009 A JP7091009 A JP 7091009A JP 9100995 A JP9100995 A JP 9100995A JP H08288340 A JPH08288340 A JP H08288340A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit chip
semiconductor device
electrode
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7091009A
Other languages
Japanese (ja)
Inventor
Norio Nitta
法生 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP7091009A priority Critical patent/JPH08288340A/en
Publication of JPH08288340A publication Critical patent/JPH08288340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16137—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To realize a mounting part in which the impedance is lowered at a wiring mounting part in order to reduce the high frequency loss at the mounting part between high frequency high function integrated circuit chips. CONSTITUTION: A ball bump 12 is arranged on an electrode pad 11 provided oh the side face of an integrated circuit chip 13 and bonded to the electrode pad 11 provided on the side face of an adjacent integrated circuit chip or an inner lead. Since the wiring between integrated circuit chips has substantially the same height as the collapsed ball bump, i.e., bonding material, the impedance is decreased while minimizing the placement thus realizing high frequency.high density mounting.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は高密度、高周波化半導
体実装に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high density, high frequency semiconductor packaging.

【０００２】[0002]

【従来の技術】集積回路素子の実装は金細線であるボン
ディングワイヤーを用いてボールボンディング法によっ
て行われるのが一般的である。ボールボンディング法は
第１ボンディング箇所から周囲のどの方向へもボンディ
ング装置上の機械的な制約を受けずに自由にボンディン
グワイヤーを第２のボンディング箇所へつなげることが
できるため最も多く使用され、かつ信頼性の高いボンデ
ィング方法となっている。2. Description of the Related Art Generally, an integrated circuit element is mounted by a ball bonding method using a bonding wire which is a fine gold wire. The ball bonding method is most often used and reliable because the bonding wire can be freely connected to the second bonding point from the first bonding point in any direction around the periphery without any mechanical restriction on the bonding apparatus. It is a highly reliable bonding method.

【０００３】このボンディング法では集積回路チップは
回路が構成される面上に外部への電極端子であるパッド
が設けられ、内部配線材料と同じ材料・構成で電極パッ
ドが集積回路チップの外縁に位置する。しかしながら、
ボールボンディング法では、集積回路面電極パッドより
垂直にボンディングワイヤーを取り出すため、パッケー
ジするための空間が垂直取り出し方向に必要となり、垂
直取り出し部分がその大部分を占めるボンディングワイ
ヤー高さと集積回路チップ厚みを足し合わせた高さが薄
型化の限界となる。電子回路として有効であるチップ部
分以外の空間に取り出し用の厚み方向の空間が必要であ
り、これが無駄な空間になる。In this bonding method, the integrated circuit chip is provided with pads, which are electrode terminals to the outside, on the surface where the circuit is formed, and the electrode pad is located at the outer edge of the integrated circuit chip with the same material and structure as the internal wiring material. To do. However,
In the ball bonding method, since the bonding wire is taken out vertically from the integrated circuit surface electrode pad, a space for packaging is required in the vertical taking out direction, and the vertical taking out part occupies most of the bonding wire height and integrated circuit chip thickness. The combined height is the limit for thinning. A space in the thickness direction for taking out is necessary in a space other than the chip portion which is effective as an electronic circuit, and this is a wasted space.

【０００４】また、近年の高速化デバイスの出現により
高周波化実装が要求されてきているが、集積回路面より
電気信号を垂直に取り出し、リードへ接続する本ボール
ボンディング法では回路面での信号による磁界の影響を
受けるとともに（特願平５−１３２９５６号公報参
照）、チップとリードの間のボンディングワイヤーの配
線される空間がパッケージとしての集積度の高密度化を
防げ、パッケージのインピーダンスを大きくして信号伝
達を困難にし、ますます増大する高周波化集積回路実装
にとって大きな壁となってきている。Further, with the advent of high-speed devices in recent years, high-frequency mounting is required, but in the present ball bonding method in which electric signals are taken out vertically from the integrated circuit surface and connected to leads, the signal on the circuit surface is used. In addition to being affected by a magnetic field (see Japanese Patent Application No. 5-132956), the space between the chip and the lead where the bonding wire is wired can prevent the integration density of the package from increasing, and increase the impedance of the package. This makes signal transmission difficult, and is becoming a big barrier to the increasing number of high-frequency integrated circuit packaging.

【０００５】[0005]

【発明が解決しようとする課題】実装箇所での高周波化
にとって課題となるのは配線部分でのインピーダンス特
性である。高周波信号により、自インダクタンスが無視
できなくなるほどリアクタンスが増加し、寄生容量も同
様に無視できなくなる。特性インピーダンスのマッチン
グがとれていない部分では反射が起こって伝達損失が大
きくなりパッケージの外側と信号が交信できなくなる。
本発明では信号電流が流れる集積回路チップ面から高周
波信号の最適な取り出しを行われていない実装部分に着
目した高周波で低損失なチップ・外部リード接続方法を
実現することを目的とする。The problem of high frequency at the mounting location is the impedance characteristic at the wiring portion. Due to the high frequency signal, the reactance increases so much that the self-inductance cannot be ignored, and the parasitic capacitance cannot be ignored either. In a portion where the characteristic impedances are not matched, reflection occurs and transmission loss increases, making it impossible to communicate with the outside of the package.
It is an object of the present invention to realize a high-frequency and low-loss chip / external lead connection method focusing on a mounting portion where a high-frequency signal is not optimally taken out from an integrated circuit chip surface through which a signal current flows.

【０００６】[0006]

【課題を解決するための手段】本発明は上記目的を達成
するために以下の構成を要旨とする。すなわち、 （１）少なくとも側面に電極を有することを特徴とする
集積回路チップ。 （２）集積回路チップ上面および側面の両面に電極があ
ってそれぞれの電極に電気的に接合手段を有することを
特徴とする集積回路チップ。 （３）少なくとも側面に電極を有する集積回路チップで
バンプを介して他の１つまたは複数の少なくとも側面に
電極を有する集積回路チップと接合したことを特徴とす
る半導体装置。 （４）集積回路チップ上面および側面の両面に電極があ
ってそれぞれの電極に電気的接合手段を有する集積回路
チップと、他の１つまたは複数の集積回路チップ上面お
よび側面の両面に電極があってそれぞれの電極に電気的
接合手段を有する集積回路チップをバンプで接合したこ
とを特徴とする半導体装置。 （５）１つまたは複数の少なくとも側面に電極を有する
集積回路チップと他の１つまたは複数の集積回路チップ
上面および側面の両面に電極があってそれぞれの電極に
電気的接合手段を有する集積回路チップをバンプで接合
したことを特徴とする半導体装置。 （６）少なくとも側面に電極を有する集積回路チップと
インナーリードをバンプで接合したことを特徴とする半
導体装置。 （７）集積回路チップ上面および側面の両面に電極があ
ってそれぞれの電極に電気的接合手段を有する集積回路
チップとインナーリードをバンプで接合したことを特徴
とする半導体装置。 （８）バンプがボールバンプであることを特徴とする前
記（３），（４），（５），（６），（７）の何れかに
記載の半導体装置。 （９）バンプが金属であることを特徴とする前記
（３），（４），（５），（６），（７）の何れかに記
載の半導体装置。 （１０）バンプが導電性プラスチックであることを特徴
とする前記（３），（４），（５），（６），（７）の
何れかに記載の半導体装置である。The present invention has the following structures in order to achieve the above object. That is, (1) an integrated circuit chip having an electrode on at least a side surface. (2) An integrated circuit chip characterized in that electrodes are provided on both upper and side surfaces of the integrated circuit chip, and each electrode has a bonding means electrically. (3) A semiconductor device characterized in that an integrated circuit chip having an electrode on at least a side surface is bonded to one or more other integrated circuit chips having an electrode on at least a side surface via a bump. (4) An integrated circuit chip having electrodes on both upper and side surfaces of the integrated circuit chip, each electrode having an electrical connecting means, and one or more other integrated circuit chip having electrodes on both upper and side surfaces. A semiconductor device characterized in that an integrated circuit chip having an electrical bonding means is bonded to each electrode by bumps. (5) An integrated circuit chip having one or more electrodes on at least side surfaces and an integrated circuit chip having electrodes on both upper and side surfaces of another one or more integrated circuit chips, and each electrode having an electrical connection means A semiconductor device in which chips are joined by bumps. (6) A semiconductor device in which an integrated circuit chip having an electrode on at least a side surface and an inner lead are joined by a bump. (7) A semiconductor device characterized in that electrodes are provided on both upper and side surfaces of an integrated circuit chip, and the integrated circuit chip having an electrical connecting means is connected to each electrode by bumps. (8) The semiconductor device according to any one of (3), (4), (5), (6), and (7), wherein the bump is a ball bump. (9) The semiconductor device according to any one of (3), (4), (5), (6), and (7), wherein the bump is a metal. (10) The semiconductor device according to any one of (3), (4), (5), (6), and (7), wherein the bump is made of conductive plastic.

【０００７】以下に本発明を図に基づいて説明する。本
発明は図１に示すように集積回路チップ１３の少なくと
も側面（図１は側面および上面）に電極パッド１１，１
１′を配設せしめ、側面電極パッド１１′にボール１２
を配置し、これを介して図３および図４に示すように接
続先の他の半導体集積回路チップ３１あるいはリード４
１を圧接して接続する。図２は電極パッドを側面と上面
に設け、パッド間配線２１でこれらを接続している集積
回路チップ１３の例である。The present invention will be described below with reference to the drawings. According to the present invention, as shown in FIG. 1, electrode pads 11, 1 are provided on at least a side surface (a side surface and an upper surface in FIG. 1) of an integrated circuit chip 13.
1'is provided, and the ball 12 is provided on the side electrode pad 11 '.
And the other semiconductor integrated circuit chip 31 or the lead 4 to which the connection is made as shown in FIGS.
1 is pressed and connected. FIG. 2 shows an example of the integrated circuit chip 13 in which electrode pads are provided on the side surface and the upper surface and they are connected by the inter-pad wiring 21.

【０００８】本発明では、このような構成でチップを接
続し、集積回路面での電磁界の影響を極力遠ざけること
によって集積回路パッケージ全体の高周波化を図る。さ
らにマイクロストリップ線路として特性インピーダンス
をその経路中で変化させないようにするために回路面と
リード面を一致させる。また、チップ側面どうしを接続
することによってチップ間配線を不要としたマルチチッ
プモジュールを実現する。チップとリードあるいはチッ
プどうしを接続するときにチップまたはリード側面に配
置されたボールを挟みこんで変形し、接続する。In the present invention, the chips are connected in such a configuration, and the influence of the electromagnetic field on the integrated circuit surface is kept as far away as possible, so that the frequency of the entire integrated circuit package is increased. Further, as a microstrip line, the circuit surface and the lead surface are made to coincide so as not to change the characteristic impedance in the path. In addition, a multi-chip module that does not require inter-chip wiring is realized by connecting the side surfaces of the chips. When connecting the chip and the lead or between the chips, the balls arranged on the side surface of the chip or the lead are sandwiched to be deformed and connected.

【０００９】[0009]

【作用】チップ上回路面とリード上面の高さの差をｈと
すると、回路面で発生した高速電磁界の影響を最も受け
にくくなるそれらの位置関係はｈ＝０である。これは、
ｈによって変化するインダクタンスの関係（図５）を見
れば、ｈ＝０の位置が最小のインダクタンスの値を持つ
ことによっても分かる。また、回路チップどうしをつな
いだ場合、通常実装では本来持つべき配線長さによる遅
延時間がなくなる。つまり、隣接するチップどうしがあ
たかも同じチップ上にある集積回路ユニットとして振る
舞うのでＷＳＩ(Wafer Scale Integration）の手法の１
つとしても効果がある。現在ＷＳＩの欠点はウェハ上の
欠陥によって大きな面積でチップを切り出そうとしても
良品が取り出せないところにある。同じ機能を実現する
回路を小さな複数チップで構成しているのが現状であ
る。本実装方法であれば、良品だけのチップをウェハ上
で構成される回路と同一集積度で構成することができ
る。When the height difference between the circuit surface on the chip and the upper surface of the lead is h, the positional relationship between them is the least affected by the high-speed electromagnetic field generated on the circuit surface, and h = 0. this is,
From the relationship of the inductance that changes with h (FIG. 5), it can be seen that the position of h = 0 has the smallest inductance value. Further, when the circuit chips are connected to each other, the delay time due to the wiring length that should be provided in normal mounting is eliminated. In other words, since adjacent chips behave as if they were integrated circuit units on the same chip, WSI (Wafer Scale Integration) method 1
It is also effective as one. Currently, the drawback of WSI is that even if a chip is cut out in a large area due to a defect on the wafer, a good product cannot be taken out. At present, a circuit that realizes the same function is composed of a plurality of small chips. According to this mounting method, only good chips can be formed with the same degree of integration as the circuits formed on the wafer.

【００１０】[0010]

【実施例】実施例を図面に基づいて説明する。ＤＳＰチ
ップに本発明による実装方式を用いた。図４に示すよう
にボール径１５０μｍφの金ボール１２をチップ周囲の
電極１１に配置してインナーリード４１先端をボールに
押しつけることによって接合した。リード４１はあらか
じめ中心より変形させて上方より押さえつけてリード直
線状態になったときにチップ周囲から２０μｍに位置す
るようにした。接合時の治具は３００℃で加熱し、１バ
ンプ当たり５０gfの力が加わるようにし、ボール変形・
接合を行った。通常のトランスファーモールドを行った
後、パッケージされたチップは厚み０．７mmと従来の薄
型パッケージの１mmよりも薄型化することができ、１５
０MHz 以上の安定な動作も確認することができた。イン
ナーリードは１本ずつ押さえてボールを変形させても、
一部分だけ押さえても、本実施例のように全体を押さえ
てもよい。また、パッケージ後の信頼性試験においても
良好であった。Embodiments will be described with reference to the drawings. The mounting method according to the present invention was used for the DSP chip. As shown in FIG. 4, a gold ball 12 having a ball diameter of 150 μm was arranged on the electrode 11 around the chip, and the tip of the inner lead 41 was pressed against the ball to bond them. The lead 41 was previously deformed from the center and pressed from above so that the lead 41 was positioned at 20 μm from the periphery of the chip when it was in a straight line state. The jig during bonding is heated at 300 ° C so that a force of 50 gf is applied to each bump to prevent ball deformation.
Joined. After the normal transfer molding, the packaged chip can be thinner than 0.7mm, which is 1mm of the conventional thin package.
We were able to confirm stable operation above 0 MHz. Even if you press the inner leads one by one to deform the ball,
You may press only one part or you may press the whole like this Example. The reliability test after packaging was also good.

【００１１】[0011]

【発明の効果】チップサイズでの高密度実装が可能とな
るばかりでなく、回路面を同一面上に近く配置しかつチ
ップ間配線を最短化できるため配線部分の損失を最小に
した実装で高周波集積回路を構成することが可能とな
る。EFFECTS OF THE INVENTION Not only high-density mounting in a chip size is possible, but also circuit surfaces are arranged close to each other on the same surface and wiring between chips can be minimized. It becomes possible to configure an integrated circuit.

【図面の簡単な説明】[Brief description of drawings]

【図１】側面に電極を持った集積回路チップと電極パッ
ド上に配置されたボールバンプを持つ半導体集積回路チ
ップの概略図である。FIG. 1 is a schematic view of an integrated circuit chip having an electrode on a side surface and a semiconductor integrated circuit chip having a ball bump arranged on an electrode pad.

【図２】上面の電極パッドに側面の電極パッドが配線さ
れた半導体集積回路チップの概略図である。FIG. 2 is a schematic view of a semiconductor integrated circuit chip in which side surface electrode pads are wired to upper surface electrode pads.

【図３】側面電極を持った集積回路チップどうしの接合
時の位置関係説明概略断面図である。FIG. 3 is a schematic cross-sectional view for explaining the positional relationship when joining integrated circuit chips having side electrodes to each other.

【図４】側面電極を持った集積回路チップとリードとの
接合時の位置関係説明概略断面図である。FIG. 4 is a schematic cross-sectional view illustrating a positional relationship when an integrated circuit chip having a side electrode and a lead are joined together.

【図５】（ａ），（ｂ）は配線面高さｈとインピーダン
スの関係を模式的に示す図である。5A and 5B are diagrams schematically showing a relationship between a wiring surface height h and impedance.

【符号の説明】[Explanation of symbols]

１１ 電極パッド １２ ボールバンプ １３ 集積回路チップ ２１ チップ上のパッド間配線部分 ３１ 接合相手側集積回路チップ ４１ インナーリード ５１ 配線回路（面） 11 Electrode Pad 12 Ball Bump 13 Integrated Circuit Chip 21 Inter-Pad Wiring Part on Chip 31 Joining Integrated Circuit Chip 41 Inner Lead 51 Wiring Circuit (Surface)

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 少なくとも側面に電極を有することを特
徴とする集積回路チップ。1. An integrated circuit chip having an electrode on at least a side surface. 【請求項２】 集積回路チップ上面および側面の両面に
電極があってそれぞれの電極に電気的に接合手段を有す
ることを特徴とする集積回路チップ。2. An integrated circuit chip, characterized in that electrodes are provided on both upper and side surfaces of the integrated circuit chip, and each electrode has a bonding means electrically. 【請求項３】 少なくとも側面に電極を有する集積回路
チップでバンプを介して他の１つまたは複数の少なくと
も側面に電極を有する集積回路チップと接合したことを
特徴とする半導体装置。3. A semiconductor device comprising an integrated circuit chip having an electrode on at least a side surface and a bump integrated with another integrated circuit chip having at least one electrode on at least a side surface via a bump. 【請求項４】 集積回路チップ上面および側面の両面に
電極があってそれぞれの電極に電気的接合手段を有する
集積回路チップと、他の１つまたは複数の集積回路チッ
プ上面および側面の両面に電極があってそれぞれの電極
に電気的接合手段を有する集積回路チップをバンプで接
合したことを特徴とする半導体装置。4. An integrated circuit chip having electrodes on both upper and side surfaces of the integrated circuit chip, each electrode having an electrical connection means, and one or more other integrated circuit chip electrodes on both upper and side surfaces. Therefore, a semiconductor device is characterized in that an integrated circuit chip having an electric bonding means is bonded to each electrode by bumps. 【請求項５】 １つまたは複数の少なくとも側面に電極
を有する集積回路チップと他の１つまたは複数の集積回
路チップ上面および側面の両面に電極があってそれぞれ
の電極に電気的接合手段を有する集積回路チップをバン
プで接合したことを特徴とする半導体装置。5. An integrated circuit chip having one or more electrodes on at least a side surface and electrodes on both the upper surface and the side surface of another one or more integrated circuit chips, each of which has an electrical connection means. A semiconductor device having integrated circuit chips joined by bumps. 【請求項６】 少なくとも側面に電極を有する集積回路
チップとインナーリードをバンプで接合したことを特徴
とする半導体装置。6. A semiconductor device in which an integrated circuit chip having electrodes on at least side surfaces and inner leads are joined by bumps. 【請求項７】 集積回路チップ上面および側面の両面に
電極があってそれぞれの電極に電気的接合手段を有する
集積回路チップとインナーリードをバンプで接合したこ
とを特徴とする半導体装置。7. A semiconductor device, wherein electrodes are provided on both upper and side surfaces of an integrated circuit chip, and the integrated circuit chip having an electric joining means on each electrode and the inner lead are joined by bumps. 【請求項８】 バンプがボールバンプであることを特徴
とする請求項３，４，５，６，７の何れかに記載の半導
体装置。8. The semiconductor device according to claim 3, wherein the bump is a ball bump. 【請求項９】 バンプが金属であることを特徴とする請
求項３，４，５，６，７の何れかに記載の半導体装置。9. The semiconductor device according to claim 3, wherein the bump is made of metal. 【請求項１０】 バンプが導電性プラスチックであるこ
とを特徴とする請求項３，４，５，６，７の何れかに記
載の半導体装置。10. The semiconductor device according to claim 3, wherein the bump is made of conductive plastic.
JP7091009A 1995-04-17 1995-04-17 High density semiconductor device and integrated circuit chip therefor Pending JPH08288340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7091009A JPH08288340A (en) 1995-04-17 1995-04-17 High density semiconductor device and integrated circuit chip therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7091009A JPH08288340A (en) 1995-04-17 1995-04-17 High density semiconductor device and integrated circuit chip therefor

Publications (1)

Publication Number Publication Date
JPH08288340A true JPH08288340A (en) 1996-11-01

Family

ID=14014528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7091009A Pending JPH08288340A (en) 1995-04-17 1995-04-17 High density semiconductor device and integrated circuit chip therefor

Country Status (1)

Country Link
JP (1) JPH08288340A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005062170A (en) * 2003-07-28 2005-03-10 Nippon Denshi Kogyo Kk Electrical connection structure of three dimensional body and integrated body using the same
JP2011104767A (en) * 2009-11-09 2011-06-02 Honeywell Internatl Inc Silicon tab edge mount for a wafer level package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005062170A (en) * 2003-07-28 2005-03-10 Nippon Denshi Kogyo Kk Electrical connection structure of three dimensional body and integrated body using the same
JP2011104767A (en) * 2009-11-09 2011-06-02 Honeywell Internatl Inc Silicon tab edge mount for a wafer level package

Similar Documents

Publication Publication Date Title
US5726489A (en) Film carrier semiconductor device
JP3765952B2 (en) Semiconductor device
US5384488A (en) Configuration and method for positioning semiconductor device bond pads using additional process layers
US6316838B1 (en) Semiconductor device
US6365963B1 (en) Stacked-chip semiconductor device
US6608376B1 (en) Integrated circuit package substrate with high density routing mechanism
US7485490B2 (en) Method of forming a stacked semiconductor package
US8053278B2 (en) Multi-chip package type semiconductor device
US7508054B2 (en) Semiconductor device and a method of manufacturing the same
US6812066B2 (en) Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
JP3022393B2 (en) Semiconductor device, lead frame, and method of manufacturing semiconductor device
US6982485B1 (en) Stacking structure for semiconductor chips and a semiconductor package using it
US9240372B1 (en) Semiconductor die having lead wires formed over a circuit in a shielded area
US5863812A (en) Process for manufacturing a multi layer bumped semiconductor device
US6392305B1 (en) Chip scale package of semiconductor
US5426319A (en) High-frequency semiconductor device including microstrip transmission line
US6340839B1 (en) Hybrid integrated circuit
TW546767B (en) Methods of manufacturing an integrated circuit package and a substrate adapted to receive an integrated circuit chip
JPS61274333A (en) Semiconductor device
JP2574510B2 (en) High frequency semiconductor device
JPH08288340A (en) High density semiconductor device and integrated circuit chip therefor
JPH10335366A (en) Semiconductor device
JP3174238B2 (en) Semiconductor device and method of manufacturing the same
JP2518145B2 (en) Multilayer lead frame with heat sink
US20030057569A1 (en) Semiconductor device

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20030415