JPH08274027A - Semiconductor thin film device - Google Patents
Semiconductor thin film deviceInfo
- Publication number
- JPH08274027A JPH08274027A JP9626595A JP9626595A JPH08274027A JP H08274027 A JPH08274027 A JP H08274027A JP 9626595 A JP9626595 A JP 9626595A JP 9626595 A JP9626595 A JP 9626595A JP H08274027 A JPH08274027 A JP H08274027A
- Authority
- JP
- Japan
- Prior art keywords
- mixed crystal
- buffer layer
- crystal layer
- substrate
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、Ｓｉ基板上にＳｉＧ
ｅ混晶薄膜を形成した半導体薄膜素子に関する。BACKGROUND OF THE INVENTION The present invention relates to SiG on a Si substrate.
The present invention relates to a semiconductor thin film element formed with a mixed crystal thin film.
【０００２】[0002]
【従来の技術】従来、Ｓｉ基板上にＳｉＧｅ混晶層を直
接成長させる方法が種々試みられている。このＳｉＧｅ
混晶層は、分子線エピタキシー（ＭＢＥ）法により、形
成されるもので、数千Å程度の厚さに形成される。2. Description of the Related Art Conventionally, various methods for directly growing a SiGe mixed crystal layer on a Si substrate have been tried. This SiGe
The mixed crystal layer is formed by a molecular beam epitaxy (MBE) method and has a thickness of about several thousand Å.
【０００３】[0003]
【発明が解決しようとする課題】ここで、Ｓｉ基板上に
ＳｉＧｅ混晶層を直接成長させると、両者の格子定数の
違いからそのヘテロ界面にミスフィット転位が発生す
る。また成長様式は２次元的から３次元的になりその表
面は凹凸状になり、混晶層内には転位が多く発生する。
そして、混晶層内に転位が多く発生存在すると電子素子
として使用する事が困難になってくる。また各種電子デ
バイスとして利用するには、ある程度の膜厚が必要であ
り、従来技術での転位の発生しない臨界膜厚程度の厚さ
では、電子デバイスには使用できないという問題があっ
た。When the SiGe mixed crystal layer is directly grown on the Si substrate, misfit dislocations are generated at the hetero interface due to the difference in lattice constant between the two. Further, the growth mode is changed from two-dimensional to three-dimensional, the surface thereof becomes uneven, and many dislocations occur in the mixed crystal layer.
If many dislocations occur in the mixed crystal layer, it becomes difficult to use it as an electronic device. In addition, there is a problem that a certain degree of film thickness is required for use as various electronic devices, and the conventional device cannot be used for electronic devices with a thickness about the critical film thickness at which dislocation does not occur.
【０００４】そこで近年では、ＳｉＧｅ混晶層とＳｉ基
板の間に新しい混晶層（バッファー層）を挿入すること
によって格子不整合に起因する歪みを抑制し、それを仮
の基板と見立てて厚い混晶層を作成することが試みられ
ている。当初は、高品位のバッファー層自体の成長がで
きなかったため結果的にバッファー層には転位が発生
し、続く混晶層中に増殖してしまっていた。近年では、
バッファー層の組成比を段階的に増やして行き、目的の
組成にする事によってＳｉ基板界面で発生した転位をそ
の上の混晶層に伝達しないような方法が取られている。
この方法においては急激に組成を変化させると効果がう
すれるため、組成を大きくするにつれ厚いバッファー層
が必要となってくる。また格子緩和を完全とするために
高い基板温度（７５０℃以上）が必要である。Therefore, in recent years, a new mixed crystal layer (buffer layer) is inserted between the SiGe mixed crystal layer and the Si substrate to suppress the strain due to lattice mismatch, and it is regarded as a temporary substrate and is thick. Attempts have been made to create mixed crystal layers. Initially, the high-quality buffer layer itself could not be grown, and as a result, dislocations occurred in the buffer layer and they grew in the subsequent mixed crystal layer. in recent years,
A method is adopted in which the dislocation generated at the Si substrate interface is not transmitted to the mixed crystal layer thereabove by increasing the composition ratio of the buffer layer stepwise to obtain the desired composition.
In this method, the effect is weakened when the composition is rapidly changed, and thus a thick buffer layer is required as the composition is increased. Further, a high substrate temperature (750 ° C. or higher) is required to complete the lattice relaxation.
【０００５】この発明は、Ｓｉ基板上の混晶層にミスフ
ィット転位がなく、比較的薄いバッファー層で、高品位
なＳｉＧｅ混晶薄膜を比較的低温で形成することができ
る半導体薄膜素子を提供することを目的とする。The present invention provides a semiconductor thin film element capable of forming a high-quality SiGe mixed crystal thin film at a relatively low temperature with a relatively thin buffer layer having no misfit dislocations in the mixed crystal layer on a Si substrate. The purpose is to do.
【０００６】[0006]
【課題を解決するための手段】この発明は、シリコン基
板上に、バッファー層としてＳｉとＧｅを組み合わせた
超格子を形成し、この超格子はそのセルのＳｉとＧｅの
組み合わせを、Ｓｉ基板側から段階的にセルに占めるＧ
ｅの割合を大きくし、このバッファー層の上に作成する
ＳｉＧｅ混晶層のＧｅの組成と同じところで最大とし、
このバッファー層の上にＳｉＧｅ混晶層を形成した半導
体薄膜素子である。According to the present invention, a superlattice in which Si and Ge are combined is formed as a buffer layer on a silicon substrate, and the superlattice is formed by combining the combination of Si and Ge in the cell with the Si substrate side. G gradually occupies the cell
The ratio of e is increased, and it is maximized at the same position as the Ge composition of the SiGe mixed crystal layer formed on this buffer layer.
This is a semiconductor thin film element in which a SiGe mixed crystal layer is formed on this buffer layer.
【０００７】[0007]
【作用】この発明の半導体薄膜素子は、Ｓｉ基板、バッ
ファー層、混晶層の三層で構成され、バッファー層は、
シュードモロフィック成長しているため、その面内の格
子定数はＳｉ基板と同じである。よって、その上に成長
した混晶層は歪みを受け、膜厚が大きくなるにつれてそ
の歪みは大きくなっていき、臨界膜厚に達すると、歪み
の総和のエネルギーが転位が発生するのに必要なエネル
ギーを越えるため、混晶層上に成長した薄膜は転位によ
ってそのエネルギーを解放しようとする。このときエネ
ルギーはＳｉ基板とバッファー層の界面に集中し、ミス
フィット転位や線状転位が発生する。発生した転位は超
格子の界面効果で曲げられ互いに反応するか、超格子界
面でのミスフィット転位と反応し、そこで停止するため
それより上には伝達しない。また反応の確率はかなり高
くたとえ反応しないものがあってもさらに上の超格子界
面によって停止させられる。よってかなりの転位はバッ
ファー層内にとどめられ混晶層中には転位が入らない。The semiconductor thin film element of the present invention comprises three layers of a Si substrate, a buffer layer and a mixed crystal layer.
Since it is pseudomorphically grown, its in-plane lattice constant is the same as that of the Si substrate. Therefore, the mixed crystal layer grown on it receives strain, and the strain increases as the film thickness increases, and when the critical film thickness is reached, the energy of the total strain is necessary for dislocation to occur. Since the energy exceeds the energy, the thin film grown on the mixed crystal layer tries to release the energy by dislocation. At this time, energy is concentrated on the interface between the Si substrate and the buffer layer, and misfit dislocations and linear dislocations are generated. The generated dislocations are bent by the interface effect of the superlattice and react with each other, or react with misfit dislocations at the superlattice interface and stop there, so that they do not propagate above it. Moreover, the probability of reaction is quite high, and even if there is something that does not react, it is stopped by the superlattice interface above. Therefore, a considerable amount of dislocations are retained in the buffer layer and do not enter the mixed crystal layer.
【０００８】[0008]
【実施例】以下、この発明の一実施例について図面を基
にして説明する。この実施例の半導体薄膜素子は、図１
に示すように、Ｓｉ基板１０、バッファー層１２、混晶
層１３の三層で構成されている。バッファー層１２に
は、ＳｉとＧｅを組み合わせた超格子を形成し、この超
格子はそのセルのＳｉとＧｅの組み合わせを、Ｓｉ基板
側から段階的にセルに占めるＧｅの割合を大きくし、こ
のバッファー層１２側では、Ｇｅの割合は、その上に作
成するＳｉＧｅ混晶層１３のＧｅの組成と同じ割合に増
大している。図１では、Ｓｉ1-XＧｅXの、Ｘ＝０．３の
Ｇｅ組成のＳｉＧｅ混晶層１３を、数千Åの厚さに作成
した例を示す。また、バッファー層１２は、模式的に４
層にあらわされているが、実際は多数の層を形成して細
かく段階的にＧｅの割合を多くしていくものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The semiconductor thin film element of this embodiment is shown in FIG.
As shown in FIG. 3, it is composed of three layers of a Si substrate 10, a buffer layer 12, and a mixed crystal layer 13. In the buffer layer 12, a superlattice formed by combining Si and Ge is formed, and this superlattice gradually increases the proportion of Ge in the cell in the combination of Si and Ge in the cell. On the buffer layer 12 side, the proportion of Ge is increased to the same proportion as the composition of Ge of the SiGe mixed crystal layer 13 formed thereon. FIG. 1 shows an example in which the SiGe mixed crystal layer 13 of Si 1-X Ge X having a Ge composition of X = 0.3 is formed to a thickness of several thousand Å. The buffer layer 12 is typically 4
Although it is represented by layers, in reality, a large number of layers are formed to finely and gradually increase the proportion of Ge.
【０００９】実験的には、混晶層１３は、Ｓｉ1-XＧｅX
の、Ｘ＝０．１のＧｅ組成のＳｉＧｅ混晶層１３を、数
千Åの厚さに作成した（臨界膜厚以上）。この半導体薄
膜素子を製造するに際して、先ず、Ｓｉ基板１０を洗浄
し、ＭＢＥ超高真空薄膜作成装置中に導入する。Ｓｉ基
板１０が清浄であることを確認してから、超格子バッフ
ァー層１２を作成する。この時の成長条件は、基板温度
５００〜６００℃で、厚さ４００Å程度に形成する。次
に、上記Ｓｉ1-XＧｅＸのＸ＝０．１の混晶層１３を、
３６００Åの厚さに作成する。この時の基板温度は、５
５０〜６００℃である。Experimentally, the mixed crystal layer 13 is formed of Si 1-x Ge x.
The SiGe mixed crystal layer 13 having a Ge composition of X = 0.1 was formed to a thickness of several thousand Å (more than the critical film thickness). When manufacturing this semiconductor thin film element, first, the Si substrate 10 is washed and introduced into the MBE ultra-high vacuum thin film forming apparatus. After confirming that the Si substrate 10 is clean, the superlattice buffer layer 12 is formed. The growth conditions at this time are such that the substrate temperature is 500 to 600 ° C. and the thickness is about 400 Å. Next, the mixed crystal layer 13 of Si 1-X Ge X with X = 0.1 is
Create a thickness of 3600Å. The substrate temperature at this time is 5
It is 50 to 600 ° C.
【００１０】以上の工程を経て作成された試料の転位の
様子をフォトルミネッセンス法により評価すると、図２
に示すように、Ｓｉと超格子界面に転位が集中し、膜内
の転位は少ないことを示している。またuniaxial stres
sは小さくほぼ最上のＳｉＧｅ混晶層１３は緩和してい
ると思われる。即ち、図２のグラフにおいて、図中Ｄ１
〜Ｄ４の各ピークがＳｉ基板１０中の転位を示し、ブロ
ードなバックグラウンドが小さいことから、転位は、Ｓ
ｉ基板１０の界面近傍のバッファー層１２に存在してい
ると考えられる。さらに、図３のこの実施例の半導体薄
膜素子の断面の電子顕微鏡写真（倍率５００，０００
倍）の模式図に示すように、超格子が形成されたバッフ
ァー層１２に、転位１４が見られるが、ＳｉＧｅ混晶層
１３には、転位１４が見られないことが分かった。When the state of dislocation of the sample produced through the above steps is evaluated by the photoluminescence method, it is shown in FIG.
As shown in, the dislocations are concentrated on the interface between Si and the superlattice, and the dislocations in the film are small. Uniaxial stres
It is considered that s is small and the SiGe mixed crystal layer 13 almost at the top is relaxed. That is, in the graph of FIG.
Since each peak of ~ D4 indicates a dislocation in the Si substrate 10 and a broad background is small, the dislocation is S
It is considered that the i-substrate 10 exists in the buffer layer 12 near the interface. Further, an electron micrograph (magnification: 500,000) of a cross section of the semiconductor thin film element of this example in FIG.
As shown in the schematic diagram of FIG. 2), dislocations 14 are found in the buffer layer 12 in which the superlattice is formed, but dislocations 14 are not found in the SiGe mixed crystal layer 13.
【００１１】この発明の半導体薄膜素子は、抵抗値変化
を利用したセンサー（圧力センサー、磁気センサー、光
センサー等）に用いることができ、さらに、電解効果ト
ランジスタ（ＦＥＴ）、ヘテロバイポーラトランジスタ
（ＨＢＴ）等にも利用可能なものである。The semiconductor thin film element of the present invention can be used for a sensor (pressure sensor, magnetic sensor, optical sensor, etc.) utilizing a change in resistance value, and further, a field effect transistor (FET) and a hetero bipolar transistor (HBT). Etc. can also be used.
【００１２】[0012]
【発明の効果】この発明の半導体薄膜素子は、ＳｉとＧ
ｅを組み合わせた超格子が形成されたバッファー層を設
け、この超格子はそのセルのＳｉとＧｅの組み合わせ
を、Ｓｉ基板側から段階的にセルに占めるＧｅの割合を
大きくし、このバッファー層の上にＳｉＧｅ混晶層を形
成したので、比較的薄いバッファー層で、Ｓｉ基板上の
混晶層にミスフィット転位がなく、高品位なＳｉＧｅ混
晶薄膜を、比較的低温で形成することができ、多数の電
子素子に利用可能なものである。The semiconductor thin film element of the present invention is made of Si and G
A buffer layer in which a superlattice formed by combining e is formed is provided, and this superlattice increases the ratio of Ge in the cell in the combination of Si and Ge in the cell stepwise from the Si substrate side. Since the SiGe mixed crystal layer is formed on the SiGe mixed crystal layer, it is possible to form a high quality SiGe mixed crystal thin film with a relatively thin buffer layer without misfit dislocations in the mixed crystal layer on the Si substrate. It can be used for many electronic devices.
【図１】この発明の半導体薄膜素子の断面図である。FIG. 1 is a sectional view of a semiconductor thin film element of the present invention.
【図２】この発明による半導体薄膜素子のフォトルミネ
ッセンスによる評価グラフである。FIG. 2 is an evaluation graph by photoluminescence of a semiconductor thin film element according to the present invention.
【図３】この発明の一実施例の半導体薄膜素子の断面の
電子顕微鏡写真の模式図である。FIG. 3 is a schematic view of an electron micrograph of a cross section of a semiconductor thin film element according to an example of the present invention.
１０ Ｓｉ基板 １２ バッファー層 １３ 混晶層 10 Si substrate 12 Buffer layer 13 Mixed crystal layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/73 (72)発明者 小幡 勤 富山県上新川郡大沢野町下大久保3158番地 北陸電気工業株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical indication location H01L 29/73 (72) Inventor Tsutomu Obata 3158 Shimookubo, Osawano-cho, Kamishinagawa-gun, Toyama Prefecture Hokuriku Electric Industrial Co., Ltd. In the company
Claims (1)
ＳｉとＧｅを組み合わせた超格子を形成し、この超格子
はそのセルのＳｉとＧｅの組み合わせを、Ｓｉ基板側か
ら段階的にセルに占めるＧｅの割合を大きくし、このバ
ッファー層の上に作成するＳｉＧｅ混晶層のＧｅの組成
と同じところで最大としてバッファー層側に接続する面
とし、このバッファー層の上にＳｉＧｅ混晶層を形成し
た半導体薄膜素子。1. A superlattice in which Si and Ge are combined as a buffer layer is formed on a silicon substrate, and the superlattice is such that the combination of Si and Ge in the cell is gradually occupied in the cell from the Si substrate side. Of the SiGe mixed crystal layer formed on this buffer layer at the same position as the maximum Ge connecting surface to the buffer layer side, and the SiGe mixed crystal layer formed on this buffer layer. Thin film device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9626595A JPH08274027A (en) | 1995-03-29 | 1995-03-29 | Semiconductor thin film device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9626595A JPH08274027A (en) | 1995-03-29 | 1995-03-29 | Semiconductor thin film device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08274027A true JPH08274027A (en) | 1996-10-18 |
Family
ID=14160342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9626595A Pending JPH08274027A (en) | 1995-03-29 | 1995-03-29 | Semiconductor thin film device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08274027A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030058571A (en) * | 2001-12-31 | 2003-07-07 | 주식회사 하이닉스반도체 | A method for manufacturing a semiconductor device |
| KR20040014716A (en) * | 2002-08-10 | 2004-02-18 | 한국전자통신연구원 | Method of manufacturing semiconductor device having oxide layer under active region |
| WO2004064161A1 (en) * | 2003-01-14 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit |
-
1995
- 1995-03-29 JP JP9626595A patent/JPH08274027A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030058571A (en) * | 2001-12-31 | 2003-07-07 | 주식회사 하이닉스반도체 | A method for manufacturing a semiconductor device |
| KR20040014716A (en) * | 2002-08-10 | 2004-02-18 | 한국전자통신연구원 | Method of manufacturing semiconductor device having oxide layer under active region |
| WO2004064161A1 (en) * | 2003-01-14 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit |
| US7084484B2 (en) | 2003-01-14 | 2006-08-01 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
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