JPH08262495A - Thin-film transistor panel - Google Patents

Thin-film transistor panel

Info

Publication number
JPH08262495A
JPH08262495A JP8774995A JP8774995A JPH08262495A JP H08262495 A JPH08262495 A JP H08262495A JP 8774995 A JP8774995 A JP 8774995A JP 8774995 A JP8774995 A JP 8774995A JP H08262495 A JPH08262495 A JP H08262495A
Authority
JP
Japan
Prior art keywords
film transistor
thin film
line
lines
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8774995A
Other languages
Japanese (ja)
Inventor
Yasuo Koshizuka
靖雄 腰塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP8774995A priority Critical patent/JPH08262495A/en
Publication of JPH08262495A publication Critical patent/JPH08262495A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To provide a TFT panel effective for enhancing image quality of an active matrix type LCD, etc., by adding an improvement to the constitution and arrangement of TFT elements, thereby improving the opening rate of pixels. CONSTITUTION: This TFT panel is provided with plural pixel electrodes 5 in correspondence to respective intersected parts where gate lines 3 (row lines) and drain lines 4 (column lines) intersect with each other in a matrix form. The panel is provided with the TFT elements 10 which are arranged at each of the respective pixel electrodes 5 and switch at a size at which the elements are confined within the intersected regions of the gate lines 3 and the drain lines 4. The opening rate is thus increased without narrowing the display area by the pixel electrodes 5. The pixel electrodes 5 are formable in further overlap on the respective gate lines 3 and drain lines 4, by which the opening rate is further increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、薄膜トランジスタ
（ＴＦＴ）をスイッチング素子等に用いたアクティブマ
トリクス形の薄膜トランジスタパネルに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type thin film transistor panel using a thin film transistor (TFT) as a switching element or the like.

【０００２】[0002]

【従来の技術】ＴＶ映像などでは解像度が高く、高精細
マトリクス表示が必要になる。このような場合、走査電
極および表示電極が共に膨大な数になることで、表示映
像の応答速度が遅くなったり、映像コントラストが低下
するなどの弊害を発生する。これを防止するために、マ
トリクス配置された走査ライン（ゲートライン）と表示
ライン（ドレインライン）による各画素ごとに、ＴＦＴ
素子をスイッチング素子やアクティブ素子として設けた
アクティブマトリクス形表示方式がとられる。図５は、
アクティブマトリクス形ＬＣＤに用いられる従来からの
ＴＦＴパネルの一例を示し、図６はその図のIII−III矢
印線によるＴＦＴ素子および周辺構造の断面図である。
このＴＦＴパネル１は、液晶を挾んで対向する２枚のガ
ラス基板２の一方に複数の破線図示によるゲートライン
３と、他方に実線図示によるドレインライン４が互いに
直交させてマトリクスを形成している。その１画素ごと
に透明電極（ＩＴＯ）等による画素電極５が形成され、
ゲートライン３とドレインライン４の各交点近傍に１画
素電極ごとにオン／オフするＴＦＴ素子６が配置されて
なっている。ＴＦＴ素子６は、ゲートライン３に接続す
るゲート電極７を有し、このゲート電極７は上からゲー
ト絶縁膜８で覆われ、ゲート絶縁膜８上の所定位置に能
動的な活性半導体薄膜としてアモルファスシリコン（ａ
−Ｓｉ）層９が形成されている。このａ−Ｓｉ層９上に
はチャネル保護層１０が形成され、これらａ−Ｓｉ層９
とチャネル保護層１０の両層にわたって両側にｎ＋シリ
コンからなるコンタクト層１１、１２が形成されてい
る。ドレイン電極１３およびソース電極１４はコンタク
ト層１１、１２を介して形成され、ソース電極１４を画
素電極５に接続させて構成されている。2. Description of the Related Art For TV images and the like, the resolution is high and high-definition matrix display is required. In such a case, an enormous number of scan electrodes and display electrodes both cause problems such as a slow response speed of a display image and a reduction in image contrast. In order to prevent this, a TFT is provided for each pixel by a scanning line (gate line) and a display line (drain line) arranged in a matrix.
An active matrix type display system in which elements are provided as switching elements or active elements is adopted. Figure 5
An example of a conventional TFT panel used in an active matrix type LCD is shown, and FIG. 6 is a sectional view of a TFT element and a peripheral structure taken along the line III-III in FIG.
In this TFT panel 1, a plurality of glass substrates 2 sandwiching a liquid crystal face each other, and a plurality of gate lines 3 shown by broken lines and a drain line 4 shown by solid lines on the other side are orthogonal to each other to form a matrix. . A pixel electrode 5 made of a transparent electrode (ITO) or the like is formed for each pixel,
A TFT element 6 that is turned on / off for each pixel electrode is arranged in the vicinity of each intersection of the gate line 3 and the drain line 4. The TFT element 6 has a gate electrode 7 connected to the gate line 3, and the gate electrode 7 is covered with a gate insulating film 8 from above, and is amorphous as an active active semiconductor thin film at a predetermined position on the gate insulating film 8. Silicon (a
-Si) layer 9 is formed. A channel protection layer 10 is formed on the a-Si layer 9, and the a-Si layer 9 is formed.
Contact layers 11 and 12 made of n + silicon are formed on both sides of the channel protection layer 10 and the channel protection layer 10. The drain electrode 13 and the source electrode 14 are formed via the contact layers 11 and 12, and the source electrode 14 is connected to the pixel electrode 5.

【０００３】[0003]

【発明が解決しようとする課題】ところで、上記ＴＦＴ
素子６を用いたこれまでのＴＦＴパネルのように、ＴＦ
Ｔ素子６はゲートライン３とドレインライン４の各交差
部近傍で画素電極５の領域に入り込んで配置されるのが
一般的となっている。そのため、１画素ごとの画素電極
５ではＴＦＴ素子６が入り込む占有スペース分だけ表示
面積が削減されることになる。つまり、開口率（有効表
示面積に占める表示画素の面積割合）が低下すること
で、この開口率に依存する液晶パネルの光の透過率を低
下させ、画質を決定づける基本的事項の解像度、輝度、
コントラスト比などを損なう原因の一つになっている。
したがって、この発明では、ＴＦＴ素子の構成および配
置に改良を加えて画素の開口率を向上させ、アクティブ
マトリクス形ＬＣＤなどにおける高画質化に有効なＴＦ
Ｔパネルを提供することを目的としている。By the way, the above-mentioned TFT
Like the conventional TFT panel using the element 6, the TF
The T element 6 is generally arranged in the region of the pixel electrode 5 near each intersection of the gate line 3 and the drain line 4. Therefore, in the pixel electrode 5 for each pixel, the display area is reduced by the occupied space into which the TFT element 6 enters. In other words, the aperture ratio (area ratio of the display pixel occupying the effective display area) is reduced, so that the light transmittance of the liquid crystal panel depending on the aperture ratio is reduced, and the resolution, brightness, and
It is one of the causes of impairing the contrast ratio.
Therefore, in the present invention, the TF which is effective for improving the image quality in the active matrix LCD and the like by improving the structure and arrangement of the TFT element to improve the aperture ratio of the pixel.
The purpose is to provide a T-panel.

【０００４】[0004]

【課題を解決するための手段】上記目的を達成するた
め、この発明によるＴＦＴパネルは、行ラインと列ライ
ンがマトリクス状に交差した各交差部に対応して複数の
画素電極が設けられ、各画素電極ごとに配置されてスイ
ッチするＴＦＴ素子を、行ラインと列ラインの交差領域
内上に設けている。この発明の薄膜トランジスタパネル
では、ＴＦＴ素子を交差領域内に収まる大きさに形成す
ることができる。それによって、画素電極を行ラインお
よび列ラインにそれぞれオーバラップする大きさに拡張
して設けることができる。また、この発明のＴＦＴパネ
ルでは、ＴＦＴ素子がアモルファスシリコン層またはポ
リシリコン層による能動層を有し、この能動層の幅を行
ラインおよび列ラインの各幅にほぼ同等もしくは小さく
形成でき、さらにはこの能動層とチャネル保護層と、コ
ンタクト層の全てを同一幅で、行ラインおよび列ライン
の各幅にほぼ同等もしくは小さく形成することができ
る。In order to achieve the above object, a TFT panel according to the present invention is provided with a plurality of pixel electrodes corresponding to respective intersections where row lines and column lines intersect in a matrix pattern. A TFT element that is arranged for each pixel electrode and switches is provided in an area where the row line and the column line intersect. In the thin film transistor panel of the present invention, the TFT element can be formed in a size that fits within the intersection region. As a result, the pixel electrode can be provided so as to be extended to a size that overlaps the row line and the column line. Further, in the TFT panel of the present invention, the TFT element has an active layer made of an amorphous silicon layer or a polysilicon layer, and the width of this active layer can be formed to be substantially equal to or smaller than each width of the row line and the column line. The active layer, the channel protection layer, and the contact layer can all be formed to have the same width and be substantially equal to or smaller than the widths of the row lines and the column lines.

【０００５】[0005]

【作用】これまでのようにＴＦＴ素子を画素電極の領域
に入り込んで配置することで、画素表示面積を狭めてい
たが、ＴＦＴ素子を行ラインと列ラインの交差領域内に
収まる大きさに形成することで、ＴＦＴ素子の画素電極
に占める面積がほぼ皆無となり、開口率が大きくなる。
ＴＦＴ素子を形成する能動層、チャネル保護層、コンタ
クト層、ゲート電極を全て同一幅にして、行ラインおよ
び列ラインの各幅とほぼ同等もしくはそれよりも小さく
形成すれば、画素電極を行ラインおよび列ラインにオー
バラップする大きさに拡張でき、上記開口率をより一層
大きくできる。The pixel display area is narrowed by arranging the TFT element in the area of the pixel electrode as before, but the TFT element is formed in a size that fits within the intersection area of the row line and the column line. By doing so, the area occupied by the pixel electrode of the TFT element becomes almost zero, and the aperture ratio increases.
If the active layer, the channel protective layer, the contact layer, and the gate electrode forming the TFT element are all made to have the same width and the widths of the row line and the column line are substantially equal to or smaller than each width, the pixel electrode is It can be expanded to a size overlapping the column line, and the aperture ratio can be further increased.

【０００６】[0006]

【実施例】以下、この発明によるＴＦＴパネルの実施例
について図面を参照しつつ説明する。上記図５および図
６で示された従来例のＴＦＴパネルに共通もしくは準ず
る部材には同一符号を付す。図１は、アクティブマトリ
クス形ＬＣＤ等に用いられるＴＦＴパネルの正面図を示
し、図２および図３はI−I矢印線とII−II矢印線による
ＴＦＴ素子およびその周辺のそれぞれ断面図である。Ｔ
ＦＴパネル１は、従来例でも示されたように、液晶を挾
んで対向する２枚のガラス基板２を有し、このガラス基
板２の一方の対向面に設けた複数の破線図示によるこの
発明でいう行ラインの走査ライン（以下、ゲートライン
３という）と、他方の対向面に設けた実線図示によるこ
の発明でいう列ラインの信号ライン（以下、ドレインラ
イン４という）が互いに直交してマトリクスを形成して
いる。ゲートライン３とドレインライン４の各交差領域
内には、１画素の画素電極５に対応してこれをスイッチ
するＴＦＴ素子１０が配置されている。Embodiments of the TFT panel according to the present invention will be described below with reference to the drawings. Members common or similar to those of the conventional TFT panel shown in FIGS. 5 and 6 are designated by the same reference numerals. FIG. 1 shows a front view of a TFT panel used in an active matrix type LCD or the like, and FIGS. 2 and 3 are cross-sectional views of the TFT element and its periphery taken along the lines I-I and II-II. T
As shown in the conventional example, the FT panel 1 has two glass substrates 2 facing each other with a liquid crystal sandwiched between them, and a plurality of broken lines provided on one facing surface of the glass substrate 2 according to the present invention. The so-called row line scanning line (hereinafter referred to as gate line 3) and the column line signal line (hereinafter referred to as drain line 4) according to the present invention shown in solid lines on the other opposing surface are orthogonal to each other to form a matrix Is forming. In each intersection region of the gate line 3 and the drain line 4, a TFT element 10 corresponding to the pixel electrode 5 of one pixel and switching the pixel electrode 5 is arranged.

【０００７】図１で明らかなように、実施例のＴＦＴ素
子１０は、幅ＷGを有するゲートライン３と幅ＷDを有す
るドレインライン４の交差領域内の平面積を越えない大
きさで形成されている。このＴＦＴ素子１０は、図２の
ように、ゲートライン３に接続するゲート電極１１がガ
ラス基板２上に形成され、ゲート電極１１は真空蒸着法
もしくはスパッタ法により堆積させて成膜した金属膜
に、ホトリソエッチングにより所定のパターン加工を施
して形成することができる。このゲート電極１１を覆っ
てゲート絶縁膜１２が成膜され、ゲート絶縁膜１２上の
所定位置には活性化された半導体薄膜による能動層とし
て、アモルファスシリコン（ａ−Ｓｉ）層１３が形成さ
れている。このａ−Ｓｉ層１３上にはチャネル保護膜１
４が形成され、これらａ−Ｓｉ層１３とチャネル保護膜
１４の両層にわたって両側にｎ＋シリコンによるコンタ
クト層１５、１６が形成されている。さらに、図３に示
すように、コンタクト層１５、１６上にはドレイン電極
１７およびソース電極１８がパッシベーション（層間絶
縁膜）１９を介在させて形成され、一方のドレイン電極
１７は上記ドレインライン４に、他方のソース電極１８
は上記画素電極５にそれぞれ接続してなっている。As is apparent from FIG. 1, the TFT element 10 of the embodiment is formed in a size not exceeding the plane area in the intersecting region of the gate line 3 having the width W G and the drain line 4 having the width W D. Has been done. In this TFT element 10, as shown in FIG. 2, a gate electrode 11 connected to a gate line 3 is formed on a glass substrate 2, and the gate electrode 11 is a metal film deposited by a vacuum deposition method or a sputtering method. It can be formed by performing a predetermined pattern processing by photolithography etching. A gate insulating film 12 is formed so as to cover the gate electrode 11, and an amorphous silicon (a-Si) layer 13 is formed at a predetermined position on the gate insulating film 12 as an active layer made of an activated semiconductor thin film. There is. The channel protective film 1 is formed on the a-Si layer 13.
4 are formed, and contact layers 15 and 16 made of n + silicon are formed on both sides of both the a-Si layer 13 and the channel protection film 14. Further, as shown in FIG. 3, a drain electrode 17 and a source electrode 18 are formed on the contact layers 15 and 16 with a passivation (interlayer insulating film) 19 interposed therebetween, and one drain electrode 17 is connected to the drain line 4. , The other source electrode 18
Are connected to the pixel electrodes 5, respectively.

【０００８】この実施例のＴＦＴ素子１０では、画素電
極５に接続されるソース電極１８のみが、ゲートライン
３とドレインライン４の交差領域内から突出した形にな
っているが、素子を形成する大部分は交差領域内に収ま
っている。ＴＦＴ素子１０が画素電極５の表示面積に入
り込んで占める面積は皆無に近く、従来例の図５で示さ
れたＴＦＴ素子６により狭められた画素電極５との比較
で明確なように、１画素単位での表示面積は大きく拡張
でき、開口率を大きくすることができる。In the TFT device 10 of this embodiment, only the source electrode 18 connected to the pixel electrode 5 is projected from the inside of the intersection region of the gate line 3 and the drain line 4, but the device is formed. Most are within the intersection area. The area occupied by the TFT element 10 entering the display area of the pixel electrode 5 is almost zero, and as is clear by comparison with the pixel electrode 5 narrowed by the TFT element 6 shown in FIG. The display area in units can be greatly expanded, and the aperture ratio can be increased.

【０００９】こうした構成によって、マトリクス駆動す
るＴＦＴ素子６がオン（導通）になると、ドレインライ
ン４からの画像情報信号が画素電極５に入力され、相手
基板側の対向する画素電極との間で電位を変化させる
と、その区画に挾まれた液晶の配向が変化する。これに
よって、光を透過、反射させて画像を表示する。すなわ
ち、オンによって画素の静電容量部に電荷の形で書き込
まれた画像情報信号のデータは、オフ（遮断）時にその
書き込まれた電荷を蓄積することで、常に液晶をスイッ
チ駆動させることができる。With this structure, when the matrix-driving TFT element 6 is turned on (conducting), the image information signal from the drain line 4 is input to the pixel electrode 5, and a potential is generated between the pixel electrode 5 and the opposing pixel electrode on the opposite substrate side. Is changed, the orientation of the liquid crystal sandwiched in the section changes. As a result, light is transmitted and reflected to display an image. That is, the data of the image information signal written in the electrostatic capacity portion of the pixel in the form of electric charge when turned on accumulates the written electric charge at the time of turning off (interruption), so that the liquid crystal can be always switch-driven. .

【００１０】また、この発明では、図１のようにソース
電極１８をゲートライン３とドレインライン４の交差領
域内領域から突出させることなく、ＴＦＴ素子１０全体
を完全に交差領域内に収める別の実施例も可能である。
すなわち、図４に概略的に示すように、ＴＦＴ素子２０
全体をゲートライン３とドレインライン４の交差領域内
の面積にほぼ同等もしくはそれよりも小さく形成すれ
ば、画素電極５の縦横による表示面積は、図１の上記実
施例のときのＨ1×Ｌ1よりも大きく、ゲートライン３と
ドレインライン４にオーバラップさせてＨ2×Ｌ2とする
ことができる。その分、開口率は図１の実施例に増して
さらに大きくできる。Further, according to the present invention, as shown in FIG. 1, the source electrode 18 is not projected from the region inside the intersection region of the gate line 3 and the drain line 4, and the whole TFT element 10 is completely contained in the intersection region. Examples are also possible.
That is, as schematically shown in FIG.
If the entire area is formed to be approximately equal to or smaller than the area in the intersection region of the gate line 3 and the drain line 4, the vertical and horizontal display area of the pixel electrode 5 is H 1 × L in the above embodiment of FIG. It is larger than 1 and can be made H 2 × L 2 by overlapping the gate line 3 and the drain line 4. Therefore, the aperture ratio can be further increased as compared with the embodiment of FIG.

【００１１】なお、この発明では、能動層としてａ−Ｓ
ｉ層１３が示されたが、目的によっては、このａ−Ｓｉ
層１３にレーザアニール法などによる焼成手段を施して
変換した多結晶シリコン（poly-Ｓｉ）層としてあって
もよい。例えば、ａ−ＳｉＴＦＴの場合、プロセス温度
が低く大面積のガラス基板上に形成し易いといった利点
がある。しかし、さらに高解像度や高画質化とともに、
大画面化などを実現するには高移動度のｐ−ＳｉＴＦＴ
が好ましいとされている。In the present invention, a-S is used as the active layer.
The i-layer 13 is shown, but depending on the purpose, this a-Si
The layer 13 may be a polycrystalline silicon (poly-Si) layer converted by performing a firing means such as a laser annealing method. For example, in the case of a-Si TFT, there is an advantage that the process temperature is low and it can be easily formed on a large area glass substrate. However, with higher resolution and higher image quality,
High mobility p-SiTFT to realize large screen
Is said to be preferable.

【００１２】[0012]

【発明の効果】以上説明したように、この発明によるＴ
ＦＴパネルによれば、ＴＦＴ素子を走査ラインと信号ラ
インの交差領域内に収まる面積で形成したので、画素電
極による表示領域の一部を占有することなく、そのスペ
ース分だけ表示面積が大きくとれる。そのため、開口率
を大きくでき、この開口率に依存する液晶パネルの光の
透過率を低下させ、解像度、輝度そしてコントラスト比
などにおいて高画質画面が得られる。As described above, the T according to the present invention is
According to the FT panel, since the TFT element is formed in an area that fits within the intersection area of the scanning line and the signal line, the display area can be increased by the space without occupying a part of the display area by the pixel electrode. Therefore, the aperture ratio can be increased, the light transmittance of the liquid crystal panel depending on the aperture ratio can be reduced, and a high-quality screen can be obtained in terms of resolution, brightness, contrast ratio, and the like.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明によるＴＦＴパネルの一部を示す正面
図。FIG. 1 is a front view showing a part of a TFT panel according to the present invention.

【図２】図１のI−I線による実施例のＴＦＴパネルの一
部側面断面図。FIG. 2 is a partial side cross-sectional view of the TFT panel of the example taken along the line II of FIG.

【図３】図１のII−II線による実施例のＴＦＴパネルの
一部側面断面図。FIG. 3 is a partial side sectional view of the TFT panel of the example taken along the line II-II in FIG.

【図４】ＴＦＴパネルの他の実施例を示す正面図。FIG. 4 is a front view showing another embodiment of the TFT panel.

【図５】従来例のＴＦＴパネルの一部を示す正面図。FIG. 5 is a front view showing a part of a conventional TFT panel.

【図６】従来例の図５のIII−III線によるＴＦＴパネル
の一部側面断面図。6 is a partial side sectional view of a TFT panel taken along line III-III in FIG. 5 of a conventional example.

【符号の説明】[Explanation of symbols]

１ ＴＦＴパネル ２ ガラス基板 ３ ゲートライン（行ライン） ４ ドレインライン（列ライン） ５ 画素電極 １０ ＴＦＴ素子 １１ ゲート電極 １３ ａ−Ｓｉ層（能動層） １７ ドレイン電極 １８ ソース電極 1 TFT panel 2 glass substrate 3 gate line (row line) 4 drain line (column line) 5 pixel electrode 10 TFT element 11 gate electrode 13 a-Si layer (active layer) 17 drain electrode 18 source electrode

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 行ラインと列ラインがマトリクス状に交
差した各交差部に対応して複数の画素電極が設けられ、
各画素電極ごとに配置されてスイッチする薄膜トランジ
スタ素子を、行ラインと列ラインの交差領域内に設けた
ことを特徴とする薄膜トランジスタパネル。1. A plurality of pixel electrodes are provided corresponding to each intersection where row lines and column lines intersect in a matrix.
A thin film transistor panel, wherein thin film transistor elements arranged and switched for each pixel electrode are provided in an intersection region of a row line and a column line. 【請求項２】 前記薄膜トランジスタ素子を前記交差領
域内に収まる大きさに形成したことを特徴とする請求項
１記載の薄膜トランジスタパネル。2. The thin film transistor panel according to claim 1, wherein the thin film transistor element is formed in such a size that it can be accommodated in the intersection region. 【請求項３】 前記画素電極を前記行ラインおよび前記
列ラインとオーバラップする大きさに拡張して設けて開
口率を高めたことを特徴とする請求項１または２記載の
薄膜トランジスタパネル。3. The thin film transistor panel according to claim 1, wherein the pixel electrode is expanded to a size overlapping the row line and the column line to increase the aperture ratio. 【請求項４】 前記薄膜トランジスタ素子が能動層を有
し、この能動層の幅を前記行ラインおよび前記列ライン
の各幅にほぼ同等もしくは小さく形成したことを特徴と
する請求項１〜３のいずれか１つ記載の薄膜トランジス
タパネル。4. The thin film transistor element has an active layer, and the width of the active layer is formed to be substantially equal to or smaller than the width of each of the row line and the column line. 1. A thin film transistor panel as described above. 【請求項５】 前記薄膜トランジスタ素子が能動層、チ
ャネル保護層およびコンタクト層を有し、これら各層を
全て同一幅で前記行ラインおよび前記列ラインの各幅に
ほぼ同等もしくは小さく形成したことを特徴とする請求
項１〜３のいずれか１つ記載の薄膜トランジスタパネ
ル。5. The thin film transistor element has an active layer, a channel protection layer and a contact layer, and these layers are all formed to have the same width and to be substantially equal to or smaller than the widths of the row lines and the column lines. The thin film transistor panel according to claim 1. 【請求項６】 前記能動層が、アモルファスシリコン層
またはポリシリコン層であることを特徴とする請求項４
または５記載の薄膜トランジスタパネル。6. The active layer is an amorphous silicon layer or a polysilicon layer.
Alternatively, the thin film transistor panel described in 5 above.
JP8774995A 1995-03-22 1995-03-22 Thin-film transistor panel Pending JPH08262495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8774995A JPH08262495A (en) 1995-03-22 1995-03-22 Thin-film transistor panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8774995A JPH08262495A (en) 1995-03-22 1995-03-22 Thin-film transistor panel

Publications (1)

Publication Number Publication Date
JPH08262495A true JPH08262495A (en) 1996-10-11

Family

ID=13923591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8774995A Pending JPH08262495A (en) 1995-03-22 1995-03-22 Thin-film transistor panel

Country Status (1)

Country Link
JP (1) JPH08262495A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039622A (en) * 1996-11-28 1998-08-17 김영환 Liquid crystal display
US6762805B2 (en) 2001-06-08 2004-07-13 Nec Lcd Technologies, Ltd. Active matrix type liquid crystal display device and method of fabricating the same
KR100542303B1 (en) * 1998-08-24 2006-04-06 비오이 하이디스 테크놀로지 주식회사 Liquid crystal display
KR100870522B1 (en) * 2002-09-17 2008-11-26 엘지디스플레이 주식회사 Liquid Crystal Display Device and Method of Fabricating The same
EP2166407A1 (en) * 2007-06-27 2010-03-24 Sharp Kabushiki Kaisha Liquid crystal display device
JP2012212147A (en) * 2000-08-23 2012-11-01 Semiconductor Energy Lab Co Ltd Portable information device
TWI470327B (en) * 2008-01-08 2015-01-21 Au Optronics Corp Pixel structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980039622A (en) * 1996-11-28 1998-08-17 김영환 Liquid crystal display
KR100542303B1 (en) * 1998-08-24 2006-04-06 비오이 하이디스 테크놀로지 주식회사 Liquid crystal display
JP2012212147A (en) * 2000-08-23 2012-11-01 Semiconductor Energy Lab Co Ltd Portable information device
US6762805B2 (en) 2001-06-08 2004-07-13 Nec Lcd Technologies, Ltd. Active matrix type liquid crystal display device and method of fabricating the same
KR100870522B1 (en) * 2002-09-17 2008-11-26 엘지디스플레이 주식회사 Liquid Crystal Display Device and Method of Fabricating The same
EP2166407A1 (en) * 2007-06-27 2010-03-24 Sharp Kabushiki Kaisha Liquid crystal display device
EP2166407A4 (en) * 2007-06-27 2011-01-05 Sharp Kk Liquid crystal display device
TWI470327B (en) * 2008-01-08 2015-01-21 Au Optronics Corp Pixel structure

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