JPH08262475A - Production of display device - Google Patents

Production of display device

Info

Publication number
JPH08262475A
JPH08262475A JP8878995A JP8878995A JPH08262475A JP H08262475 A JPH08262475 A JP H08262475A JP 8878995 A JP8878995 A JP 8878995A JP 8878995 A JP8878995 A JP 8878995A JP H08262475 A JPH08262475 A JP H08262475A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor integrated
integrated circuit
wiring
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8878995A
Other languages
Japanese (ja)
Other versions
JP3578828B2 (en
Inventor
Setsuo Nakajima
節男 中嶋
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP8878995A priority Critical patent/JP3578828B2/en
Priority to US08/618,267 priority patent/US5834327A/en
Publication of JPH08262475A publication Critical patent/JPH08262475A/en
Priority to US09/126,826 priority patent/US7483091B1/en
Priority to US10/896,015 priority patent/US7271858B2/en
Priority to US10/902,787 priority patent/US7214555B2/en
Application granted granted Critical
Publication of JP3578828B2 publication Critical patent/JP3578828B2/en
Priority to US12/057,994 priority patent/US7776663B2/en
Priority to US12/844,858 priority patent/US8012782B2/en
Priority to US13/224,374 priority patent/US8563979B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE: To reduce the thickness of driver circuit parts by mechanically adhering only the semiconductor integrated circuits equal to stick crystals onto a substrate and electrically connecting these circuits as well. CONSTITUTION: Metallic wirings 4 and the semiconductor integrated circuits 6 are mechanically fixed onto the substrate 3. Further, these circuits are electrically connected by heating the electric wirings 12 formed of materials, such as transparent conductive films, and metallic wirings 4 arranged on the substrate 3 to melt by irradiating the parts where both overlap on each other with a laser. At this time, the metallic wirings 4 are desired to melt easily. Then, low melting metals, such as aluminum, indium, tin and gold, are preferable. In such a case, the semiconductor integrated circuits 6 are formed to the structure in which N channel type TFTs 7 and P channel type TFTs 8 are held by ground surface insulating films 9, interlayer insulators 10 or passivation films 11 of silicon oxide, etc. The connection of the metallic wirings 4 and the wiring electrodes 12 may be electrically executed by fixing both with anisotropic conductive adhesives and press bonding both under heating.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、液晶表示装置等のパッ
シブマトリクス型もしくはアクティブマトリクス型の表
示装置に関し、特に、駆動用の半導体集積回路を効果的
に実装したことにより、表示装置の基板に占める面積を
大きくした、ファッショナブルな表示装置を得ることを
目的とする。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a passive matrix type or active matrix type display device such as a liquid crystal display device, and more particularly to a substrate of a display device by effectively mounting a semiconductor integrated circuit for driving. The purpose is to obtain a fashionable display device that occupies a large area.

【０００２】[0002]

【従来の技術】マトリクス型の表示装置としては、パッ
シブマトリクス型とアクティブマトリクス型の構造が知
られている。パッシブマトリクス型では、第１の基板上
に透明導電膜等でできた多数の短冊型の電気配線（ロー
配線）をある方向に形成し、第２の基板上には、前記第
１の基板上の電気配線とは概略垂直な方向に同様な短冊
型の電気配線（カラム配線）を形成する。そして、両基
板上の電気配線が対向するように基板を配置する。2. Description of the Related Art Passive matrix type and active matrix type structures are known as matrix type display devices. In the passive matrix type, a large number of strip-shaped electric wirings (low wirings) made of a transparent conductive film or the like are formed in a certain direction on the first substrate, and on the second substrate, the above-mentioned first substrate is formed. Similar strip-shaped electrical wiring (column wiring) is formed in a direction substantially perpendicular to the electrical wiring. Then, the substrates are arranged so that the electric wirings on both substrates face each other.

【０００３】基板間に液晶材料のように電圧・電流等に
よって、透光性、光反射・散乱性の変化する電気光学材
料を設けておけば、第１の基板の任意のロー配線と第２
の基板の任意のカラム配線との間に電圧・電流等を印加
すれば、その交差する部分の透光性、光反射・散乱性等
を選択できる。このようにして、マトリクス表示が可能
となる。If an electro-optical material, such as a liquid crystal material, whose translucency, light reflection / scattering property is changed by voltage / current, etc. is provided between the substrates, an arbitrary low wiring of the first substrate and the second wiring are provided.
By applying a voltage / current or the like between the substrate and any column wiring, it is possible to select the translucency, the light reflection / scattering property or the like of the intersecting portion. In this way, matrix display is possible.

【０００４】アクティブマトリクス型では、第１の基板
上に多層配線技術を用いて、ロー配線とカラム配線とを
形成し、この配線の交差する部分に画素電極を設け、画
素電極には薄膜トランジスタ（ＴＦＴ）等のアクティブ
素子を設けて、画素電極の電位や電流を制御する構造と
する。また、第２の基板上にも透明導電膜を設け、第１
の基板の画素電極と、第２の基板の透明導電膜とが対向
するように基板を配置する。In the active matrix type, a row wiring and a column wiring are formed on the first substrate by using a multi-layer wiring technique, a pixel electrode is provided at an intersection of these wirings, and a thin film transistor (TFT) is provided on the pixel electrode. ) Is provided to control the potential and current of the pixel electrode. In addition, a transparent conductive film is provided on the second substrate,
The substrate is arranged so that the pixel electrode on the substrate and the transparent conductive film on the second substrate face each other.

【０００５】いずれにせよ、使用される基板の材料は、
作製プロセスによって選択された。例えば、透明導電膜
を形成して、これをエッチングして、ロー・カラム配線
パターンを形成する以外には特に複雑なプロセスのない
パッシブマトリクス型では、基板はガラス以外に、プラ
スチックでもよかった。一方、比較的、高温の成膜工程
を有し、また、ナトリウム等の可動イオンを避ける必要
のあるアクティブマトリクス型では、基板としてアルカ
リ濃度の極めて低いガラス基板を用いる必要があった。In any case, the substrate material used is
Selected by fabrication process. For example, in the passive matrix type, which has no particularly complicated process other than forming a row / column wiring pattern by forming a transparent conductive film and etching the transparent conductive film, the substrate may be plastic instead of glass. On the other hand, in the active matrix type, which has a relatively high temperature film forming process and needs to avoid mobile ions such as sodium, it is necessary to use a glass substrate having an extremely low alkali concentration as a substrate.

【０００６】[0006]

【発明の解決しようとする課題】いずれにせよ、従来の
マトリクス型表示装置においては、特殊なもの以外は、
マトリクスを駆動するための半導体集積回路（周辺駆動
回路、もしくは、バー回路という）を取り付ける必要が
あった。従来は、これは、テープ自動ボンディング（Ｔ
ＡＢ）法やチップ・オン・グラス（ＣＯＧ）法によって
なされてきた。しかしながら、マトリクスの規模は数１
００行にも及ぶ大規模なものであるので、集積回路の端
子も非常に多く、一方、するドライバー回路は、長方形
状のＩＣパッケージや半導体チップであるため、これら
の端子を基板上の電気配線と接続するために配線を引き
回す必要から、表示画面に比して、周辺部分の面積が無
視できないほど大きくなった。In any case, in the conventional matrix type display device, except the special one,
It was necessary to attach a semiconductor integrated circuit (referred to as a peripheral drive circuit or a bar circuit) for driving the matrix. Traditionally, this has been the tape automatic bonding (T
The AB) method and the chip-on-glass (COG) method have been used. However, the scale of the matrix is 1
Since it is as large as 00 lines, the number of terminals of the integrated circuit is very large. On the other hand, since the driver circuit to be used is a rectangular IC package or a semiconductor chip, these terminals are electrically connected on the substrate. Since the wiring needs to be laid around to connect with, the area of the peripheral portion is so large that it cannot be ignored compared to the display screen.

【０００７】この問題を解決する方法として、特開平７
−１４８８０には、ドライバー回路を、マトリクスの１
辺とほぼ同じ程度の細長い基板（スティック、もしく
は、スティック・クリスタルという）上に形成し、これ
をマトリクスの端子部に接続するという方法が開示され
ている。ドライバー回路としては、幅２ｍｍほど程度で
十分であることにより、このような配置が可能となる。
このため、基板のほとんどを表示画面とすることができ
た。As a method for solving this problem, Japanese Unexamined Patent Publication No. Hei 7
-14880 has a driver circuit in the matrix 1
A method is disclosed in which it is formed on an elongated substrate (called a stick or a stick crystal) having approximately the same size as the sides, and this is connected to the terminal portion of the matrix. Such a layout is possible because a driver circuit having a width of about 2 mm is sufficient.
Therefore, most of the substrates can be used as the display screen.

【０００８】もちろん、この場合には、マトリクスの面
積が大きなものでは、回路をシリコンウェハー上に形成
することができないので、ガラス基板等の上に形成する
必要がある。したがって、ガラス基板等の上に形成され
る半導体回路に用いられる能動素子は、結晶性またはア
モルファスの半導体を用いたＴＦＴである。Of course, in this case, if the matrix has a large area, the circuit cannot be formed on the silicon wafer, so it is necessary to form it on the glass substrate or the like. Therefore, an active element used in a semiconductor circuit formed on a glass substrate or the like is a TFT using a crystalline or amorphous semiconductor.

【０００９】しかしながら、スティック・クリスタルに
関しては、ドライバー回路の基板の厚さが、表示装置全
体の小型化に支障をきたした。例えば、表示装置をより
薄くする必要から基板の厚さを０．３ｍｍとすること
は、基板の種類や工程を最適化することにより可能であ
る。しかし、スティック・クリスタルの厚さは、製造工
程で必要とされる強度から０．５ｍｍ以下とすることは
困難であり、結果として、基板を張り合わせたときに、
０．２ｍｍ以上もスティック・クリスタルが出ることと
なる。However, regarding the stick crystal, the thickness of the substrate of the driver circuit hinders the miniaturization of the entire display device. For example, it is possible to reduce the thickness of the substrate to 0.3 mm because it is necessary to make the display device thinner by optimizing the type and process of the substrate. However, it is difficult to set the thickness of the stick crystal to 0.5 mm or less because of the strength required in the manufacturing process. As a result, when the substrates are laminated,
Stick crystals will be produced for 0.2 mm or more.

【００１０】また、スティック・クリスタルと表示装置
の基板の種類が異なると、熱膨張の違い等の理由によ
り、回路に欠陥が生じることがあった。特に、表示装置
の基板として、プラスチック基板を用いると、この問題
が顕著であった。なぜならば、スティック・クリスタル
の基板としては、プラスチックを用いることは、耐熱性
の観点から、実質的に不可能なためである。本発明はこ
のようなスティック・クリスタルの抱えていた問題を解
決し、表示装置のより一層の小型・軽量化を目的とする
ものである。If the stick crystal and the substrate of the display device are different in type, a defect may occur in the circuit due to a difference in thermal expansion or the like. This problem was particularly noticeable when a plastic substrate was used as the substrate of the display device. This is because it is practically impossible to use plastic as the stick crystal substrate from the viewpoint of heat resistance. The present invention is intended to solve the problems of the stick crystal and further reduce the size and weight of the display device.

【００１１】[0011]

【課題を解決するための手段】本発明は、表示装置の基
板上に、スティック・クリスタルと同等な半導体集積回
路のみを機械的に接着し、かつ、電気的な接続を行うこ
とにより、ドライバー回路部分の薄型化を実施する。ま
た、電気的な接続を、加熱処理により一括に行うこと
で、高スループットを実現する。According to the present invention, a driver circuit is provided by mechanically adhering only a semiconductor integrated circuit equivalent to a stick crystal on a substrate of a display device and electrically connecting the same. Make the part thinner. In addition, high throughput is realized by collectively performing electrical connection by heat treatment.

【００１２】本発明の基本的な構成は、電気配線と、こ
れに電気的に接続され、ＴＦＴを有する細長い半導体集
積回路を有する第１の基板の、電気配線の形成された面
に対して、表面に透明導電膜を有する第２の基板の透明
導電膜を対向させた構造の表示装置であり、特開平７−
１４８８０のスティック・クリスタルと同様、前記半導
体集積回路は、概略、表示装置の表示面（すなわち、マ
トリクス）の１辺の長さに等しく、かつ、他の基板上に
作製されたものを剥離して、前記第１の基板に装着した
ものであるThe basic configuration of the present invention is that the electric wiring and the surface of the first substrate, which is electrically connected to the electric wiring and has the elongated semiconductor integrated circuit having the TFT, on which the electric wiring is formed are A display device having a structure in which a transparent conductive film of a second substrate having a transparent conductive film on its surface is opposed to the second conductive film.
Similar to the stick crystal of 14880, the semiconductor integrated circuit is approximately equal to the length of one side of the display surface (that is, matrix) of the display device, and the one formed on another substrate is peeled off. , Mounted on the first substrate

【００１３】特に、パッシブマトリクス型の場合には、
第１の方向に延びる複数の透明導電膜の第１の電気配線
と、これに接続され、ＴＦＴを有し、第１の方向に概略
垂直な第２の方向に延びる細長い第１の半導体集積回路
とを有する第１の基板と、第２の方向に延びる複数の透
明導電膜の第２の電気配線と、これに接続され、ＴＦＴ
を有し、前記第１の方向に延びる第２の半導体集積回路
とを有する第２の基板とを、第１の電気配線と第２の電
気配線が対向するように配置した表示装置で、第１およ
び第２の半導体集積回路は他の基板上に作製されたもの
を剥離して、それぞれの基板に装着したものである。Particularly, in the case of the passive matrix type,
A first electric wiring of a plurality of transparent conductive films extending in the first direction, and a long and narrow first semiconductor integrated circuit connected to the first electric wiring and having a TFT and extending in a second direction substantially perpendicular to the first direction. And a second electric wiring of a plurality of transparent conductive films extending in the second direction and connected to the first electric wiring.
A second substrate having a second semiconductor integrated circuit extending in the first direction, the first electric wiring and the second electric wiring being arranged to face each other. The first and second semiconductor integrated circuits are manufactured by peeling off those manufactured on other substrates and mounting them on the respective substrates.

【００１４】また、アクティブマトリクス型の場合に
は、第１の方向に延びる複数の第１の電気配線と、これ
に接続され、ＴＦＴを有し、第１の方向に概略垂直な第
２の方向に延びる第１の半導体集積回路と、第２の方向
に延びる複数の第２の電気配線と、これに接続され、Ｔ
ＦＴを有し、第１の方向に延びる第２の半導体集積回路
とを有する第１の基板と、表面に透明導電膜を有する第
２の基板とにおいて、第１の基板の第１および第２の電
気配線と、第２の基板の透明導電膜とが、対向するよう
に、配置させた表示装置で、第１および第２の半導体集
積回路は他の基板上に作製されたものを剥離して、第１
の基板に装着したものである。In the case of the active matrix type, a plurality of first electric wirings extending in the first direction and TFTs connected to the first electric wirings are provided, and the second electric wirings are substantially perpendicular to the first direction. A first semiconductor integrated circuit extending in the second direction, a plurality of second electric wirings extending in the second direction, connected to the second electric wiring, and
A first substrate having an FT and a second semiconductor integrated circuit extending in the first direction, and a second substrate having a transparent conductive film on the surface thereof are the first and second substrates of the first substrate. Of the display device in which the electric wiring of and the transparent conductive film of the second substrate are arranged so as to face each other, and the first and second semiconductor integrated circuits are separated from those manufactured on another substrate. First
It is mounted on the board.

【００１５】ＴＦＴを有する半導体集積回路を他の基板
上に形成し、これを剥離して、他の基板に接着する（も
しくは、他の基板に接着したのち、元の基板を除去す
る）方法は、一般的にはＳＯＩ（シリコン・オン・イン
シュレータ）技術の１つとして知られており、特表平６
−５０４１３９やその他の公知の技術、あるいは、以下
の実施例で用いるような技術を使用すればよい。A method of forming a semiconductor integrated circuit having a TFT on another substrate, peeling it off and adhering it to another substrate (or adhering to another substrate and then removing the original substrate) is , Which is generally known as one of the SOI (silicon on insulator) technologies,
-504139, other known techniques, or the technique used in the following embodiments may be used.

【００１６】図１に、本発明の表示装置の断面構造の例
を示す。図１（Ａ）は、比較的、小さな倍率で見たもの
である。図の左側は、半導体集積回路の設けられたドラ
イバー回路部１を、また、右側は、マトリクス部２を示
す。基板３上に金属配線４及び半導体集積回路６を樹脂
５で機械的に固定する。さらに、基板３上に配置された
透明導電膜等の材料でできた電気配線１２と金属配線４
とを、両者が重なる部分にレーザー照射で加熱すること
により溶融し電気的な接続を行う。この際、金属配線４
は容易に溶融することが望まれる。従ってアルミニウム
・インジウム・スズ・金等の低融点金属が望ましい。FIG. 1 shows an example of a sectional structure of the display device of the present invention. FIG. 1A is viewed at a relatively small magnification. The left side of the figure shows a driver circuit section 1 provided with a semiconductor integrated circuit, and the right side shows a matrix section 2. The metal wiring 4 and the semiconductor integrated circuit 6 are mechanically fixed on the substrate 3 with the resin 5. Further, the electric wiring 12 and the metal wiring 4 made of a material such as a transparent conductive film disposed on the substrate 3
And are melted by heating with laser irradiation in the overlapping portion to establish electrical connection. At this time, the metal wiring 4
Is desired to melt easily. Therefore, low melting point metals such as aluminum, indium, tin, and gold are desirable.

【００１７】図１（Ａ）のうち、点線で囲まれた領域を
拡大したのが、図１（Ｂ）である。符号は、図１（Ａ）
と同じ物を示す。半導体集積回路は、Ｎチャネル型ＴＦ
Ｔ７とＰチャネル型ＴＦＴ８が、下地絶縁膜９、層間絶
縁物１０、あるいは、酸化珪素等のパッシベーション膜
１１で挟まれた構造となる。（図１（Ｂ））FIG. 1B is an enlarged view of a region surrounded by a dotted line in FIG. 1A. The reference numeral is shown in FIG.
Shows the same thing as. The semiconductor integrated circuit is an N-channel TF
The T7 and the P-channel TFT 8 are sandwiched between the base insulating film 9, the interlayer insulator 10 or the passivation film 11 such as silicon oxide. (Fig. 1 (B))

【００１８】金属配線４と配線電極１２との接触部分に
関しては、レーザー溶接する方法の他に、図３（Ａ）に
示すように、透明導電膜等の電気配線３１を備えた基板
４０に、金属配線３３を伴った半導体集積回路３４を異
方性導電接着剤で固定し、加熱・圧着する事で電気的な
接続をしても良い。図３（Ｂ・Ｃ）は接続部の拡大図で
ある。異方性導電接着剤３５による接続（図３（Ｂ））
では、異方性導電接着剤の中の導電性粒子３６により、
金属配線３３と電気配線３１が電気的に接続される。さ
らには、図３（Ｃ）に示すように前もって配線電極３１
上に低融点金属からなるバンプ３７を配置しておき、そ
の後加熱によりバンプ３７を溶融し電気的な接続をとる
方法も可能である。Regarding the contact portion between the metal wiring 4 and the wiring electrode 12, in addition to the laser welding method, as shown in FIG. 3A, a substrate 40 provided with an electric wiring 31 such as a transparent conductive film is provided. The semiconductor integrated circuit 34 with the metal wiring 33 may be fixed with an anisotropic conductive adhesive and heated and pressure-bonded to make electrical connection. 3B and 3C are enlarged views of the connecting portion. Connection with anisotropic conductive adhesive 35 (Fig. 3 (B))
Then, by the conductive particles 36 in the anisotropic conductive adhesive,
The metal wiring 33 and the electric wiring 31 are electrically connected. Furthermore, as shown in FIG.
It is also possible to dispose the bumps 37 made of a low melting point metal on top and then fuse the bumps 37 by heating to establish electrical connection.

【００１９】このような表示装置の作製順序の概略は、
図２に示される。図２はパッシブマトリクス型の表示装
置の作製手順を示す。まず、多数の半導体集積回路２２
を適当な基板２１の上に形成する。（図２（Ａ））The outline of the manufacturing sequence of such a display device is as follows.
As shown in FIG. FIG. 2 shows a procedure for manufacturing a passive matrix display device. First, a large number of semiconductor integrated circuits 22
Are formed on a suitable substrate 21. (Fig. 2 (A))

【００２０】そして、これを分断して、スティック・ク
リスタル２３、２４を得る。得られたスティック・クリ
スタルは、次の工程に移る前に電気特性をテストして、
良品・不良品に選別するとよい。（図２（Ｂ））Then, this is divided to obtain stick crystals 23 and 24. The stick crystal obtained is tested for electrical properties before moving on to the next step,
It is good to select good products and defective products. (FIG. 2 (B))

【００２１】次に、スティック・クリスタル２３、２４
の半導体集積回路２９、３０をＳＯＩ技術によって、別
の基板２５、２７の透明導電膜による配線のパターンの
形成された面２６、２８上に接着し、電気的な接続を取
る。（図２（Ｃ）、図２（Ｄ））Next, the stick crystals 23, 24
The semiconductor integrated circuits 29 and 30 are adhered to the surfaces 26 and 28 on which the wiring patterns are formed by the transparent conductive films of the other substrates 25 and 27 by the SOI technique to establish electrical connection. (Fig. 2 (C), Fig. 2 (D))

【００２２】最後に、このようにして得られた基板を向
かい合わせることにより、パッシブマトリクス型表示装
置が得られる。なお、面２６は、面２６の逆の面、すな
わち、配線パターンの形成されていない方の面を意味す
る（図２（Ｇ））Finally, the substrates thus obtained are opposed to each other to obtain a passive matrix type display device. The surface 26 means the surface opposite to the surface 26, that is, the surface on which the wiring pattern is not formed (FIG. 2 (G)).

【００２３】上記の場合には、ロー・スティック・クリ
スタル（ロー配線を駆動するドライバー回路用のスティ
ック・クリスタル）とカラム・スティック・クリスタル
（カラム配線を駆動するドライバー回路用のスティック
・クリスタル）を同じ基板２１から切りだしたが、別の
基板から切りだしてもよいことは言うまでもない。ま
た、図２ではパッシブマトリクス型表示装置の例を示し
たが、アクティブマトリクス型表示装置でも、同様にお
こなえることは言うまでもない。さらに、フィルムのよ
うな材料を基板として形成される場合は実施例に示し
た。In the above case, the row stick crystal (the stick crystal for the driver circuit that drives the row wiring) and the column stick crystal (the stick crystal for the driver circuit that drives the column wiring) are the same. It is cut out from the substrate 21, but needless to say, it may be cut out from another substrate. Although FIG. 2 shows an example of the passive matrix type display device, it goes without saying that the same can be applied to the active matrix type display device. Further, the case where a material such as a film is formed as the substrate is shown in the embodiment.

【００２４】[0024]

【実施例】【Example】

〔実施例１〕本実施例は、パッシブマトリクス型液晶表
示装置の一方の基板の作製工程の概略を示すものであ
る。本実施例を図４、図５を用いて説明する。図４に
は、スティック・クリスタル上にドライバー回路を形成
する工程の概略を、図５にはドライバー回路を液晶表示
装置の基板に実装する工程の概略を示す。[Embodiment 1] This embodiment outlines a manufacturing process of one substrate of a passive matrix liquid crystal display device. This embodiment will be described with reference to FIGS. FIG. 4 shows an outline of the step of forming the driver circuit on the stick crystal, and FIG. 5 shows an outline of the step of mounting the driver circuit on the substrate of the liquid crystal display device.

【００２５】まず、ガラス基板５０上に剥離層として、
厚さ３０００Åのシリコン膜５１を堆積した。シリコン
膜５１は、その上に形成される回路と基板とを分離する
際にエッチングされるので、膜質についてはほとんど問
題とされないので、量産可能な方法によって堆積すれば
よい。さらに、シリコン膜はアモルファスでも結晶性で
もよく、他の元素を含んでもよい。First, as a release layer on the glass substrate 50,
A 3000 Å thick silicon film 51 was deposited. Since the silicon film 51 is etched when the circuit formed on it and the substrate are separated from each other, there is almost no problem with the film quality, and therefore the silicon film 51 may be deposited by a mass-production method. Furthermore, the silicon film may be amorphous or crystalline, and may contain other elements.

【００２６】また、ガラス基板は、コーニング７０５
９、同１７３７、ＮＨテクノグラスＮＡ４５、同３５、
日本電気硝子ＯＡ２等の無アルカリもしくは低アルカリ
ガラスや石英ガラスを用いればよい。石英ガラスを用い
る場合には、そのコストが問題となるが、本発明では１
つの液晶表示装置に用いられる面積は極めて小さいの
で、単位当たりのコストは十分に小さい。The glass substrate is Corning 705.
9, 1737, NH Techno Glass NA45, 35,
Non-alkali or low-alkali glass such as Nippon Electric Glass OA2 or quartz glass may be used. When quartz glass is used, its cost becomes a problem, but in the present invention, 1
Since the area used for one liquid crystal display device is extremely small, the cost per unit is sufficiently small.

【００２７】シリコン膜５１上には、厚さ２００ｎｍの
酸化珪素膜５３を堆積した。この酸化珪素膜は下地膜と
なるので、作製には十分な注意が必要である。そして、
公知の方法により、結晶性の島状シリコン領域（シリコ
ン・アイランド）５４、５５を形成した。このシリコン
膜の厚さは、必要とする半導体回路の特性を大きく左右
するが、一般には、薄いほうが好ましかった。本実施例
では４０〜６０ｎｍとした。A 200 nm-thickness silicon oxide film 53 was deposited on the silicon film 51. Since this silicon oxide film serves as a base film, sufficient care must be taken in its fabrication. And
The crystalline island-shaped silicon regions (silicon islands) 54 and 55 were formed by a known method. Although the thickness of the silicon film largely influences the required characteristics of the semiconductor circuit, it is generally preferable that the thickness is thin. In this embodiment, the thickness is 40 to 60 nm.

【００２８】また、結晶性シリコンを得るには、アモル
ファスシリコンにレーザー等の強光を照射する方法（レ
ーザーアニール法）や、熱アニールによって固相成長さ
せる方法（固相成長法）が用いられる。固相成長法を用
いる際には、特開平６−２４４１０４に開示されるよう
に、ニッケル等の触媒元素をシリコンに添加すると、結
晶化温度を下げ、アニール時間を短縮できる。さらに
は、特開平６−３１８７０１のように、一度、固相成長
法によって結晶化せしめたシリコンを、レーザーアニー
ルしてもよい。いずれの方法を採用するかは、必要とさ
れる半導体回路の特性や基板の耐熱温度等によって決定
すればよい。In order to obtain crystalline silicon, a method of irradiating amorphous silicon with strong light such as laser (laser annealing method) or a method of solid phase growth by thermal annealing (solid phase growth method) is used. When the solid phase growth method is used, as disclosed in JP-A-6-244104, if a catalytic element such as nickel is added to silicon, the crystallization temperature can be lowered and the annealing time can be shortened. Further, as in Japanese Patent Laid-Open No. 6-318701, silicon once crystallized by the solid phase growth method may be laser annealed. Which method should be adopted may be determined depending on the required characteristics of the semiconductor circuit, the heat resistant temperature of the substrate, and the like.

【００２９】その後、プラズマＣＶＤ法もしくは熱ＣＶ
Ｄ法によって、厚さ１２０ｎｍの酸化珪素のゲイト絶縁
膜５６を堆積し、さらに、厚さ５００ｎｍの結晶性シリ
コンによって、ゲイト電極・配線５７、５８を形成し
た。ゲイト配線は、アルミニウムやタングステン、チタ
ン等の金属や、あるいはそれらの珪化物でもよい。さら
に、金属のゲイト電極を形成する場合には、特開平５−
２６７６６７もしくは同６−３３８６１２に開示される
ように、その上面もしくは側面を陽極酸化物で被覆して
もよい。ゲイト電極をどのような材料で構成するかは、
必要とされる半導体回路の特性や基板の耐熱温度等によ
って決定すればよい。（図４（Ａ））After that, plasma CVD or thermal CV is performed.
A gate insulating film 56 of silicon oxide having a thickness of 120 nm was deposited by the D method, and further gate electrodes / wirings 57 and 58 were formed of crystalline silicon having a thickness of 500 nm. The gate wiring may be a metal such as aluminum, tungsten or titanium, or a silicide thereof. Furthermore, in the case of forming a metal gate electrode, the method disclosed in Japanese Patent Laid-Open No.
As disclosed in 267667 or 6-338612, its top or side may be coated with an anodic oxide. The material used to construct the gate electrode depends on
It may be determined according to the required characteristics of the semiconductor circuit, the heat resistant temperature of the substrate, and the like. (Fig. 4 (A))

【００３０】その後、セルフアライン的に、イオンドー
ピング法等の手段によりＮ型およびＰ型の不純物をシリ
コン・アイランドに導入し、Ｎ型領域５９、Ｐ型領域６
０を形成した。そして、公知の手段で、層間絶縁物（厚
さ５００ｎｍの酸化珪素膜）６１を堆積した。そして、
これにコンタクトホールを開孔し、アルミニウム合金配
線６２〜６４を形成した。（図４（Ｂ））After that, in self-alignment, N-type and P-type impurities are introduced into the silicon island by means such as an ion doping method, and the N-type region 59 and the P-type region 6 are formed.
Formed 0. Then, an interlayer insulator (a silicon oxide film having a thickness of 500 nm) 61 was deposited by a known means. And
Contact holes were opened in this, and aluminum alloy wirings 62 to 64 were formed. (Fig. 4 (B))

【００３１】さらに、これらの上に、パッシベーション
膜として、ポリイミド膜７０を形成した。ポリイミド膜
はワニスを塗布・硬化する事で形成される。本実施例で
は東レ（株）のフォトニースUR-3800 を用いた。まずス
ピンナで塗布する。塗布条件は所望の膜厚に応じて決め
ればよい。ここでは３０００ｒｐｍ・３０秒の条件で約
４ｕｍのポリイミド膜を形成した。これを、乾燥を行っ
た後に、露光・現像を行う。適当に条件を選ぶことで、
所望のパターンを得ることができる。その後、窒素雰囲
気中３００℃で処理することで膜の硬化を行った。さら
にその上にアルミニウムの金属配線９０をスパッタ法に
より形成した。（図４（Ｃ））Further, a polyimide film 70 was formed on these as a passivation film. The polyimide film is formed by applying and curing varnish. In this example, Photo Nice UR-3800 manufactured by Toray Industries, Inc. was used. First, apply with a spinner. The coating conditions may be determined according to the desired film thickness. Here, a polyimide film of about 4 um was formed under the conditions of 3000 rpm and 30 seconds. This is dried and then exposed and developed. By selecting the conditions appropriately,
A desired pattern can be obtained. Then, the film was cured by processing at 300 ° C. in a nitrogen atmosphere. Further, a metal wiring 90 of aluminum was formed thereon by a sputtering method. (Fig. 4 (C))

【００３２】続いて、転写用基板７２を樹脂７１で前記
半導体集積回路に接着する。転写用基板は一時的に集積
回路を保持するための強度・平坦性があればよくガラス
・プラスチック等が使用できる。この転写用基板は後で
再剥離するため、樹脂７１は除去が容易な材質が好まし
い。また粘着剤等剥離が容易なものを使用しても良い。
（図５（Ａ））Subsequently, the transfer substrate 72 is bonded to the semiconductor integrated circuit with a resin 71. The transfer substrate may be made of glass, plastic or the like as long as it has strength and flatness for temporarily holding the integrated circuit. Since this transfer substrate will be peeled again later, the resin 71 is preferably made of a material that can be easily removed. Also, an easily peelable adhesive such as an adhesive may be used.
(Figure 5 (A))

【００３３】このように処理した基板を、三塩化フッ素
（ＣｌＦ3 ）と窒素の混合ガスの気流中に放置した。三
塩化フッ素と窒素の流量は、共に５００ｓｃｃｍとし
た。反応圧力は１〜１０Ｔｏｒｒとした。温度は室温と
した。三塩化フッ素等のハロゲン化フッ素は、珪素を選
択的にエッチングする特性が知られている。一方、酸化
珪素はほとんどエッチングされない。その為、時間の経
過ととも剥離層５１はエッチングされてゆくが、下地層
５３はほとんどエッチングされずＴＦＴ素子へのダメー
ジは無い。さらに時間が経過すると、剥離層５１は完全
にエッチングされ、半導体集積回路が完全に剥離され
る。（図５（Ｂ））The substrate thus treated was left in a stream of mixed gas of fluorine trichloride (ClF 3 ) and nitrogen. The flow rates of fluorine trichloride and nitrogen were both 500 sccm. The reaction pressure was 1 to 10 Torr. The temperature was room temperature. Fluorine halide such as fluorine trichloride is known to have a property of selectively etching silicon. On the other hand, silicon oxide is hardly etched. Therefore, the peeling layer 51 is etched with the elapse of time, but the underlayer 53 is hardly etched and the TFT element is not damaged. When the time further passes, the peeling layer 51 is completely etched, and the semiconductor integrated circuit is completely peeled. (Fig. 5 (B))

【００３４】次に、剥離した半導体集積回路を、液晶表
示装置の基板７５に樹脂７６で接着し、転写用基板７２
を除去する。（図５（Ｃ）） このようにして表示装置の基板への半導体集積回路の転
写が終了した。液晶表示装置の基板としては、厚さ０．
３ｍｍのＰＥＳ（ポリエーテルサルフォン）を用いた。Next, the peeled semiconductor integrated circuit is adhered to the substrate 75 of the liquid crystal display device with the resin 76, and the transfer substrate 72 is attached.
Is removed. (FIG. 5C) In this way, the transfer of the semiconductor integrated circuit to the substrate of the display device is completed. As a substrate of a liquid crystal display device, a thickness of 0.
3 mm PES (polyether sulfone) was used.

【００３５】最後に、液晶表示装置の基板上に配置され
た配線電極８０と金属配線９０の重なる部分をＹＡＧレ
ーザー８５で照射・加熱する事で電気的な接続をする。
（図５（Ｄ））Finally, the YAG laser 85 irradiates and heats an overlapping portion of the wiring electrode 80 and the metal wiring 90 arranged on the substrate of the liquid crystal display device to electrically connect them.
(FIG. 5 (D))

【００３６】このようにして、液晶表示装置の一方の基
板への半導体集積回路の形成を終了した。このようにし
て得られる基板を用いて、液晶表示装置が完成される。Thus, the formation of the semiconductor integrated circuit on one substrate of the liquid crystal display device is completed. A liquid crystal display device is completed using the substrate thus obtained.

【００３７】〔実施例２〕本実施例は液晶表示装置の基
板上の配線と半導体集積回路の金属配線とを電気的に接
続する工程の概略を示すものである。本実施例を図６を
用いて説明する。図６は液晶表示装置の基板上の配線電
極と、半導体集積回路の金属配線との接続箇所の拡大図
を示す。[Embodiment 2] This embodiment outlines a process of electrically connecting wirings on a substrate of a liquid crystal display device and metal wirings of a semiconductor integrated circuit. This embodiment will be described with reference to FIG. FIG. 6 is an enlarged view of a connection portion between a wiring electrode on a substrate of a liquid crystal display device and a metal wiring of a semiconductor integrated circuit.

【００３８】液晶表示装置の基板１００上に透明導電膜
からなる配線電極１０１をスパッタ法により形成する。
さらに、半導体集積回路と電気的に接続される箇所に低
融点金属からなるパッド１０２をスパッタ法で形成す
る。A wiring electrode 101 made of a transparent conductive film is formed on the substrate 100 of the liquid crystal display device by a sputtering method.
Further, a pad 102 made of a low melting point metal is formed by a sputtering method at a place electrically connected to the semiconductor integrated circuit.

【００３９】次に、別の基板上で作製された半導体集積
回路及び金属配線１０３を実施例１で述べた方法により
接着剤１０４を介して機械的に固定する（図６（Ａ））Next, the semiconductor integrated circuit and the metal wiring 103 formed on another substrate are mechanically fixed via the adhesive 104 by the method described in Embodiment 1 (FIG. 6 (A)).

【００４０】最後に、ＹＡＧレーザー１０６を用い金属
配線１０３とパッド１０２の重なる箇所を溶融し電気的
接続１０８を完了する。（図６（Ｂ））Finally, the YAG laser 106 is used to melt the overlapping portion of the metal wiring 103 and the pad 102 to complete the electrical connection 108. (Fig. 6 (B))

【００４１】ここでは、レーザー照射を金属配線１０３
の上から行ったが、基板１００の下側からの照射でも同
様の効果が得られる。Here, the laser irradiation is applied to the metal wiring 103.
However, the same effect can be obtained by irradiation from the lower side of the substrate 100.

【００４２】[0042]

【発明の効果】本発明では、表示装置の基板の種類や厚
さ、大きさに関して、さまざななバリエーションが可能
である。例えば、実施例１に示したように、極めて薄い
フィルム状の液晶表示装置を得ることもできる。この場
合には、表示装置を曲面に合わせて張りつけてもよい。
さらに、基板の種類の制約が緩和された結果、プラスチ
ック基板のように、軽く、耐衝撃性の強い材料を用いる
こともでき、携行性も向上する。According to the present invention, various variations can be made regarding the type, thickness, and size of the substrate of the display device. For example, as shown in Example 1, an extremely thin film type liquid crystal display device can be obtained. In this case, the display device may be attached to the curved surface.
Further, as a result of relaxing the restrictions on the type of substrate, a light material having high impact resistance such as a plastic substrate can be used, and portability is also improved.

【００４３】また、ドライバー回路の専有する面積が小
さいので、表示装置と他の装置の配置の自由度が高ま
る。典型的には、ドライバー回路を表示面の周囲の幅数
ｍｍの領域に押し込めることが可能であるので、表示装
置自体は極めてシンプルであり、ファッション性に富ん
だ製品である。その応用範囲もさまざまに広がり、よっ
て、本発明の工業的価値は極めて高い。Further, since the area occupied by the driver circuit is small, the degree of freedom in disposing the display device and other devices is increased. Typically, since the driver circuit can be pushed into a region having a width of several mm around the display surface, the display device itself is a very simple and fashionable product. The range of its applications is widespread, and the industrial value of the present invention is extremely high.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の断面構造の例を示す。FIG. 1 shows an example of a sectional structure of the present invention.

【図２】 本発明の表示装置の作製方法の概略を示す。FIG. 2 shows an outline of a method for manufacturing a display device of the present invention.

【図３】 本発明の１例の表示装置の断面構造を示す。FIG. 3 shows a cross-sectional structure of a display device according to an example of the present invention.

【図４】 本発明に用いる半導体集積回路の作製工程の
一例を示す。FIG. 4 shows an example of a manufacturing process of a semiconductor integrated circuit used in the present invention.

【図５】 半導体集積回路を表示装置の基板に接着する
工程を示す。FIG. 5 shows a step of adhering a semiconductor integrated circuit to a substrate of a display device.

【図６】 本発明に用いる配線の電気的接続の工程の一
例を示す。FIG. 6 shows an example of a process of electrically connecting wirings used in the present invention.

【符号の説明】[Explanation of symbols]

１ ・・・ 液晶表示装置のドライバー回路部 ２ ・・・ 液晶表示装置のマトリックス部 ３ ・・・ 液晶表示装置の基板 ４ ・・・ 金属電極 ５ ・・・ 樹脂 ６ ・・・ 半導体集積回路 ７ ・・・ Ｎチャネル型ＴＦＴ ８ ・・・ Ｐチャネル型ＴＦＴ ９ ・・・ 下地膜 １０・・・ 層間絶縁膜 １１・・・ パッシベーション膜 １２・・・ 液晶表示装置の配線電極 ２１・・・ スティック・クリスタルを形成する基板 ２２・・・ 半導体集積回路 ２３、２４ スティック・クリスタル ２５、２７ 液晶表示装置の基板 ２６、２８ 配線パターンの形成されている面 ２９、３０ 液晶表示装置の基板上に移されたドライバ
ー回路２６ ・・・ 配線パターンの形成されている面と逆の面 ３１・・・ 液晶表示装置の電極 ３２・・・ 樹脂 ３３・・・ 金属電極 ３４・・・ 半導体集積回路 ３５・・・ 異方性導電接着剤 ３６・・・ 導電性の粒子 ３７・・・ バンプ ４０・・・ 液晶表示装置の基板 ５０・・・ 半導体集積回路を製造する基板 ５１・・・ 剥離層 ５３・・・ 下地膜 ５４・５５ シリコン・アイランド ５６・・・ 層間絶縁膜 ５７・５８ ゲイト電極 ５９・・・ Ｎ型領域 ６０・・・ Ｐ型領域 ６１・・・ ゲイト絶縁膜 ６２〜６４ アルミニウム合金電極 ７０・・・ パッシベーション膜 ７１・・・ 接着剤 ７２・・・ 転写用基板 ７５・・・ 液晶表示装置の基板 ７６・・・ 樹脂 ８０・・・ 液晶表示装置の配線電極 ８５・・・ レーザー光 ９０・・・ 金属電極 １００・・・ 液晶表示装置の基板 １０１・・・ 透明導電膜 １０２・・・ パッド １０３・・・ 金属配線 １０４・・・ 接着剤 １０６・・・ レーザー光 １０８・・・ 電気的接続箇所1 ... Driver circuit part of liquid crystal display device 2 ... Matrix part of liquid crystal display device 3 ... Substrate of liquid crystal display device 4 ... Metal electrode 5 ... Resin 6 ... Semiconductor integrated circuit 7 ... ··· N-channel TFT 8 ・ ・ ・ P-channel TFT 9 ・ ・ ・ Underlayer film 10 ・ ・ ・ Interlayer insulation film 11 ・ ・ ・ Passivation film 12 ・ ・ ・ Liquid crystal display wiring electrode 21 ・ ・ ・ Stick crystal Substrate 22 for forming a semiconductor integrated circuit 23, 24 Stick crystal 25, 27 Liquid crystal display substrate 26, 28 Wiring pattern formed surface 29, 30 Driver transferred onto the liquid crystal display substrate Circuit 26 ... Surface opposite to surface on which wiring pattern is formed 31 ... Electrode of liquid crystal display device 32 ... Resin 33 ... Metal electrode 34 ... Semiconductor integrated circuit 35 ... Anisotropic conductive adhesive 36 ... Conductive particles 37 ... Bumps 40 ... Liquid crystal display substrate 50 ... Substrate for manufacturing semiconductor integrated circuit 51・ ・ ・ Peeling layer 53 ・ ・ ・ Underlayer film 54 ・ 55 Silicon island 56 ・ ・ ・ Interlayer insulating film 57 ・ 58 Gate electrode 59 ・ ・ ・ N type region 60 ・ ・ ・ P type region 61 ・ ・ ・ Gate insulating film 62 to 64 Aluminum alloy electrode 70 ... Passivation film 71 ... Adhesive 72 ... Transfer substrate 75 ... Liquid crystal display substrate 76 ... Resin 80 ... Liquid crystal display wiring electrode 85・ ・ ・ Laser light 90 ・ ・ ・ Metal electrode 100 ・ ・ ・ Substrate of liquid crystal display device 101 ・ ・ ・ Transparent conductive film 102 ・ ・ ・ Pad 103 ・ ・ ・ Metal wiring 104 ・ ・ ・ Adhesive 10 ... laser light 108 ... electric connection points

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】第一の基板上に電気配線を形成する工程
と、 他の基板上に薄膜トランジスタを有する半導体集積回路
を形成する工程と、 第二の基板上に、前記第１の基板上の電気配線に対向し
て、透明導電膜を設ける工程と、 前記半導体集積回路を他の基板上から剥離し、第一の基
板上に装着する工程と、 前記半導体集積回路と前記第一の電気配線を加熱により
電気的に接続する工程とを含む表示装置の作製方法。1. A step of forming electric wiring on a first substrate, a step of forming a semiconductor integrated circuit having a thin film transistor on another substrate, and a second substrate on the first substrate. A step of providing a transparent conductive film facing the electric wiring; a step of peeling the semiconductor integrated circuit from another substrate and mounting it on a first substrate; the semiconductor integrated circuit and the first electric wiring; And a step of electrically connecting the two by heating. 【請求項２】第１の基板上に第一の方向にのびる複数の
透明導電膜の電気配線を形成する工程と、 他の基板上に薄膜トランジスタを有する半導体集積回路
を形成する工程と、 前記半導体集積回路を他の基板上から剥離し、第一の基
板上に、前記第一の方向と概略垂直な第二の方向にのび
る方向に装着する工程と、 第二の基板状に、第二の方向に延びる複数の透明導電膜
の第二の電気配線を設ける工程と、 前記半導体集積回路を他の基板上から剥離し、第二の基
板上に、第一の方向に延びる方向に装着する工程と、 前記第１の電気配線と第２の電気配線が対向するよう
に、基板を配置する工程と、 前記半導体集積回路と前記第一の電気配線を加熱により
電気的に接続する工程とを含む表示装置の作製方法。2. A step of forming electric wirings of a plurality of transparent conductive films extending in a first direction on a first substrate; a step of forming a semiconductor integrated circuit having a thin film transistor on another substrate; A step of peeling the integrated circuit from another substrate, and mounting the integrated circuit on the first substrate in a direction extending in a second direction substantially perpendicular to the first direction; A step of providing a second electric wiring of a plurality of transparent conductive films extending in a direction, and a step of peeling the semiconductor integrated circuit from another substrate and mounting the semiconductor integrated circuit on a second substrate in a direction extending in the first direction. And a step of disposing the substrate so that the first electric wiring and the second electric wiring face each other, and a step of electrically connecting the semiconductor integrated circuit and the first electric wiring by heating. A method for manufacturing a display device. 【請求項３】第一の基板上に、第一の方向にのびる複数
の第一の電気配線を形成する工程と、 第一の基板上に、第二の方向に延びる複数の第二の電気
配線を形成する工程と、 他の基板上に薄膜トランジスタを有する半導体集積回路
を形成する工程と、 前記細長い島状領域を他の基板上から剥離し、第一の基
板上に、前記第一の方向にのびる方向に装着し、前記第
二の電気配線と加熱により接続する工程と、 前記細長い島状領域を他の基板上から剥離し、第一の基
板上に、前記第二の方向にのびる方向に装着し、前記第
一の電気配線と加熱により接続する工程と、 第二の基板上に透明導電膜を形成する工程と、 前記第１の基板の第１および第２の電気配線と、前記第
２の基板の透明導電膜とが、対向するように、基板を配
置する工程と、を含む表示装置の作製方法。3. A step of forming a plurality of first electric wirings extending in a first direction on a first substrate, and a plurality of second electric wires extending in a second direction on the first substrate. A step of forming wiring, a step of forming a semiconductor integrated circuit having a thin film transistor on another substrate, peeling the elongated island region from the other substrate, and forming a first direction on the first substrate. Mounted in a direction extending to the second electrical wiring, and a step of connecting by heating, peeling the elongated island-shaped region from another substrate, on the first substrate, a direction extending in the second direction And connecting to the first electrical wiring by heating, forming a transparent conductive film on the second substrate, first and second electrical wiring of the first substrate, and And a step of disposing the substrate so that the transparent conductive film of the second substrate faces each other. A method for manufacturing a non-display device. 【請求項４】請求項１乃至３において、加熱による電気
的接続が、レーザー光によることを特徴とする表示装置
の作製方法。4. The method for manufacturing a display device according to claim 1, wherein the electrical connection by heating is by laser light. 【請求項５】請求項１乃至３において、電気的な接続
が、少なくとも金・アルミニウム・インジウム・スズの
うち一種以上を含む金属の配線で行われることを特徴と
する表示装置の作製方法。5. The method for manufacturing a display device according to claim 1, wherein the electrical connection is performed by a metal wiring containing at least one of gold, aluminum, indium, and tin.
JP8878995A 1995-03-18 1995-03-21 Method for manufacturing display device Expired - Lifetime JP3578828B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP8878995A JP3578828B2 (en) 1995-03-21 1995-03-21 Method for manufacturing display device
US08/618,267 US5834327A (en) 1995-03-18 1996-03-18 Method for producing display device
US09/126,826 US7483091B1 (en) 1995-03-18 1998-07-31 Semiconductor display devices
US10/896,015 US7271858B2 (en) 1995-03-18 2004-07-22 Method for producing display-device
US10/902,787 US7214555B2 (en) 1995-03-18 2004-08-02 Method for producing display device
US12/057,994 US7776663B2 (en) 1995-03-18 2008-03-28 Semiconductor display devices
US12/844,858 US8012782B2 (en) 1995-03-18 2010-07-28 Method for producing display device
US13/224,374 US8563979B2 (en) 1995-03-18 2011-09-02 Method for producing display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8878995A JP3578828B2 (en) 1995-03-21 1995-03-21 Method for manufacturing display device

Related Child Applications (4)

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JP2003429967A Division JP2004171005A (en) 2003-12-25 2003-12-25 Semiconductor integrated circuit
JP2003429955A Division JP3657596B2 (en) 2003-12-25 2003-12-25 Method for manufacturing semiconductor integrated circuit
JP2004003519A Division JP3579044B2 (en) 2004-01-08 2004-01-08 Manufacturing method of semiconductor integrated circuit
JP2004003520A Division JP3579045B2 (en) 2004-01-08 2004-01-08 Manufacturing method of semiconductor integrated circuit

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