JPH08250943A - Balanced amplifier circuit - Google Patents
Balanced amplifier circuitInfo
- Publication number
- JPH08250943A JPH08250943A JP7077359A JP7735995A JPH08250943A JP H08250943 A JPH08250943 A JP H08250943A JP 7077359 A JP7077359 A JP 7077359A JP 7735995 A JP7735995 A JP 7735995A JP H08250943 A JPH08250943 A JP H08250943A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- differential amplifier
- input
- output
- balanced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Amplifiers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、音声信号等の平衡信号
を電圧増幅し、平衡出力する平衡入力平衡出力増幅回路
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a balanced input balanced output amplifier circuit for voltage-amplifying a balanced signal such as a voice signal and outputting the balanced signal.
【０００２】[0002]
【従来の技術】従来、平衡信号を電圧増幅し平衡出力す
る回路としては、例えば、ラジオ技術１９９２年８月号
の１４４頁から１５０頁に掲載されているような、図２
に示す回路構成があった。この構成の回路においては、
入力信号ｅi がＲ2／Ｒ1倍された出力信号Ｖ0 が出力さ
れる。2. Description of the Related Art Conventionally, as a circuit for voltage-amplifying a balanced signal for balanced output, for example, as shown in pages 144 to 150 of the August 1992 issue of Radio Technology, FIG.
There was a circuit configuration shown in. In the circuit of this configuration,
An output signal V0 obtained by multiplying the input signal ei by R2 / R1 is output.
【０００３】[0003]
【発明が解決しようとする課題】前述の図２に示す回路
の構成では、図３の模式図に示すように、出力の同相成
分(Ｖ1＋Ｖ2)／２は、入力信号の基準電位とは一致せ
ず、一般にはオフセットにより、正負いずれかの電位を
有する。また、正相の出力信号Ｖ1と逆相の出力信号Ｖ2
は、負荷の差により出力信号の基準電位に対して対称な
信号波形とならない。本来、平衡増幅回路において、出
力信号の基準電位が入力信号の基準電位と必ずしも一致
する必要がなく、出力の正相と逆相が同じ基準電位によ
り作られていれば構わない。In the circuit configuration shown in FIG. 2 described above, as shown in the schematic diagram of FIG. 3, the in-phase component (V1 + V2) / 2 of the output does not match the reference potential of the input signal. However, it generally has either positive or negative potential due to offset. In addition, a positive phase output signal V1 and a negative phase output signal V2
Does not have a symmetrical signal waveform with respect to the reference potential of the output signal due to the difference in load. Originally, in the balanced amplifier circuit, the reference potential of the output signal does not necessarily have to match the reference potential of the input signal, and it suffices that the positive and negative phases of the output are made of the same reference potential.
【０００４】しかしながら、入力信号の基準電位と出力
信号の基準電位が一致していないときは、電源の中点電
位を基準電位とすることが困難で、最大出力を大きくす
ることができないという問題があった。また、出力に接
続される負荷は、必ずしも正相の出力と逆相の出力との
間に接続されるとは限らず、正相の出力と基準電位間、
逆相の出力と基準電位間に接続されることもある。その
場合、出力信号の基準電位に対して正相の出力信号と逆
相の出力信号が対称な信号波形でないと、出力信号電流
が基準電位に流れてしまい、電源ライン等からの雑音の
影響を受けやすくなる問題があった。本発明の目的は、
同相入力雑音成分の現れない平衡入力平衡出力増幅回路
でありながら、正相の出力信号と逆相の出力信号が基準
電位に対して対称となる平衡入力平衡出力増幅回路を提
供するものである。また、入力の基準電位と出力信号の
基準電位が一致した平衡入力平衡出力増幅回路を提供す
るものである。However, when the reference potential of the input signal and the reference potential of the output signal do not match, it is difficult to set the midpoint potential of the power source as the reference potential, and the maximum output cannot be increased. there were. Further, the load connected to the output is not always connected between the positive-phase output and the negative-phase output, and between the positive-phase output and the reference potential,
It may be connected between the output of the opposite phase and the reference potential. In that case, if the positive-phase output signal and the negative-phase output signal are not symmetrical signal waveforms with respect to the reference potential of the output signal, the output signal current will flow to the reference potential, and the influence of noise from the power supply line, etc. There was a problem of becoming vulnerable. The purpose of the present invention is to
The present invention provides a balanced input balanced output amplifier circuit in which a positive phase output signal and a negative phase output signal are symmetrical with respect to a reference potential, even though the in-phase input noise component does not appear. The present invention also provides a balanced input balanced output amplifier circuit in which the reference potential of the input and the reference potential of the output signal match.
【０００５】[0005]
【課題を解決するための手段】本発明によれば、反転入
力と非反転入力の入力間の信号を増幅する第１及び第２
の増幅回路と、第３の増幅回路の反転入力に第１及び第
２の増幅回路の出力信号を加え、第３の増幅回路の非反
転入力に基準電位を与え、第３の増幅回路の出力を第１
及び第２の増幅回路の非反転入力に加算する回路を具備
することを特徴としたものである。SUMMARY OF THE INVENTION In accordance with the present invention, first and second amplifying signals between inverting and non-inverting inputs.
And the output signals of the first and second amplifier circuits are added to the inverting input of the third amplifier circuit, the reference potential is applied to the non-inverting input of the third amplifier circuit, and the output of the third amplifier circuit is output. The first
And a circuit for adding to the non-inverting input of the second amplifier circuit.
【０００６】また、入力信号をそれぞれの非反転入力に
加える第１及び第２の差動増幅回路と、第１及び第２の
差動増幅回路の出力をそれぞれの反転入力に帰還する抵
抗と、第１及び第２の差動増幅回路の出力をそれぞれ抵
抗を介して反転入力に入力する第３の差動増幅回路と、
第３の差動増幅回路の非反転入力に入力する基準電位
と、第３の差動増幅回路の出力を第１及び第２の差動増
幅回路のそれぞれの非反転入力に入力する抵抗を具備す
ることを特徴としたものである。Further, first and second differential amplifier circuits for applying an input signal to their respective non-inverting inputs, and resistors for returning the outputs of the first and second differential amplifier circuits to their respective inverting inputs, A third differential amplifier circuit for inputting outputs of the first and second differential amplifier circuits to inverting inputs via resistors,
A reference potential input to the non-inverting input of the third differential amplifier circuit and a resistor for inputting the output of the third differential amplifier circuit to the respective non-inverting inputs of the first and second differential amplifier circuits. It is characterized by doing.
【０００７】[0007]
【作用】平衡入力信号の差成分のみが増幅された平衡信
号出力が得られ、かつ正相の出力信号と逆相の出力信号
が基準電位に対して対称となる。また、入力信号の基準
電位と出力信号の基準電位を同一にできる。The balanced signal output in which only the difference component of the balanced input signal is amplified is obtained, and the positive-phase output signal and the negative-phase output signal are symmetrical with respect to the reference potential. Further, the reference potential of the input signal and the reference potential of the output signal can be made the same.
【０００８】[0008]
【実施例】本発明による一実施例を図面により説明す
る。図１は本発明の一実施例を示す回路図である。以下
図に示した回路に従って説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Description will be given below according to the circuit shown in the figure.
【０００９】入力端１及び入力端２から入力信号ｅi
と、入力同相雑音成分ｅnが入力される。これを接地電
位からみて入力端１に入力信号ｅi1、入力端２に入力信
号ｅi2が入力されたこととする。入力端１から差動増幅
回路３の非反転入力に抵抗Ｒ1aを介して入力され、一方
の入力端２から差動増幅回路４の非反転入力に抵抗Ｒ1b
を介して入力される。差動増幅回路３及び４の出力ｅ01
及び出力ｅ02は、それぞれの差動増幅回路３及び４の反
転入力に抵抗Ｒ2c及びＲ2dを介し負帰還される。Input signals ei from the input terminals 1 and 2
Then, the input common-mode noise component en is input. It is assumed that the input signal ei1 is input to the input terminal 1 and the input signal ei2 is input to the input terminal 2 when viewed from the ground potential. Input from the input terminal 1 to the non-inverting input of the differential amplifier circuit 3 via the resistor R1a, and from one input terminal 2 to the non-inverting input of the differential amplifier circuit 4 the resistor R1b.
Be entered via. Output e01 of the differential amplifier circuits 3 and 4
And the output e02 are negatively fed back to the inverting inputs of the differential amplifier circuits 3 and 4 via resistors R2c and R2d.
【００１０】差動増幅回路３及び４の出力信号はそれぞ
れ出力端５及び出力端６へ出力信号ｅ01及び出力信号ｅ
02として出力される。出力端５及び出力端６は、それぞ
れ抵抗Ｒ3a及びＲ3bを介し差動増幅回路７の反転入力に
共に接続され、非反転入力は、基準電位として接地され
る。差動増幅回路７の出力は抵抗Ｒ2a及びＲ2bを介して
差動増幅回路３及び４の非反転入力にそれぞれ接続され
る。The output signals of the differential amplifier circuits 3 and 4 are output to the output terminal 5 and the output terminal 6, respectively, as an output signal e01 and an output signal e.
It is output as 02. The output terminal 5 and the output terminal 6 are connected together to the inverting input of the differential amplifier circuit 7 via resistors R3a and R3b, respectively, and the non-inverting input is grounded as a reference potential. The output of the differential amplifier circuit 7 is connected to the non-inverting inputs of the differential amplifier circuits 3 and 4 via resistors R2a and R2b, respectively.
【００１１】以下に本発明による増幅回路の動作を説明
する。まず、出力信号ｅ01とｅ02は、差動増幅回路７の
裸利得をＧとすれば、 ｅ01＝(Ｒ2／Ｒ1)(ｅi＋ｅn)ーＧ(ｅ01＋ｅ02) ……(１) ｅ02＝(Ｒ2／Ｒ1）ｅnーＧ(ｅ01＋ｅ02) ……(２)The operation of the amplifier circuit according to the present invention will be described below. First, assuming that the naked gain of the differential amplifier circuit 7 is G, the output signals e01 and e02 are: e01 = (R2 / R1) (ei + en) -G (e01 + e02) (1) e02 = (R2 / R1) en-G (e01 + e02) (2)
【００１２】そして、これをｅ01，ｅ02について解く
と、(２)式より、 ｅ02(１＋Ｇ)＝(Ｒ2／Ｒ1)ｅnーＧ・ｅ01 ｅ02＝Ｒ2・ｅn／{Ｒ1(１＋Ｇ)}ーＧ・ｅ01／(１＋Ｇ) ……(３) となる。(３)式を(１)式に代入すると、Then, solving this for e01 and e02, from the equation (2), e02 (1 + G) = (R2 / R1) en-G.e01 e02 = R2.en / {R1 (1 + G)}-G. e01 / (1 + G) ... (3) Substituting equation (3) into equation (1),
【００１３】 ｅ01＝(Ｒ2／Ｒ1)(ｅi＋ｅn) −Ｇ[ｅ01＋Ｒ2・ｅn／{Ｒ1(１＋Ｇ)}ーＧ・ｅ01／(１＋Ｇ)] ……(４) となる。E01 = (R2 / R1) (ei + en) -G [e01 + R2en / {R1 (1 + G)}-Ge01 / (1 + G)] (4)
【００１４】(４)式をｅ01について解けば、 ｅ01{１＋ＧーＧ2／(１＋Ｇ)} ＝(Ｒ2／Ｒ1)(ｅi＋ｅn)ーＧ・Ｒ2・ｅn／{Ｒ1(１＋Ｇ)} したがって ｅ01＝(Ｒ2／Ｒ1){１／(１＋２・Ｇ)}(ｅi＋ｅn＋Ｇ・ｅi) ＝(Ｒ2／Ｒ1){１／(１＋２・Ｇ)}(１＋Ｇ)ｅi＋(Ｒ2／Ｒ1) ・{１／(１＋２・Ｇ)}ｅn ……(５) となる。[0014] Solving for the equation (4) e01, e01 {1 + G over G 2 / (1 + G) } = (R2 / R1) (ei + en) over G · R2 · en / {R1 (1 + G)} Therefore e01 = ( R2 / R1) {1 / (1 + 2.G)} (ei + en + G.ei) = (R2 / R1) {1 / (1 + 2.G)} (1 + G) ei + (R2 / R1). {1 / (1 + 2.G) )} en …… (5)
【００１５】また、(１)式−(２)式より、 ｅ01−ｅ02＝(Ｒ2／Ｒ1)ｅi ｅ02＝ｅ01−(Ｒ2／Ｒ1)ｅi ……(６) (６)式に(５)式を代入すると、 ｅ02＝−(Ｒ2／Ｒ1){１／(１＋２・Ｇ)Ｇ・ｅi＋(Ｒ2／Ｒ1) ・{１／(１＋２・Ｇ)ｅn ……(７) となる。From equation (1)-(2), e01-e02 = (R2 / R1) ei e02 = e01- (R2 / R1) ei ... (6) Equation (5) Substituting, e02 =-(R2 / R1) {1 / (1 + 2 * G) G * ei + (R2 / R1) * {1 / (1 + 2 * G) en ... (7).
【００１６】ここで演算増幅回路である差動増幅回路７
の裸利得が十分大きいとすると、(５)式及び(７)式よ
り、 ｅ01＝{Ｒ2／(２・Ｒ1)}ｅi ……(８) ｅ02＝−{Ｒ2／(２・Ｒ1)ｅi ……(９) が得られる。Here, a differential amplifier circuit 7 which is an operational amplifier circuit.
(5) and (7), e01 = {R2 / (2.R1)} ei ... (8) e02 =-{R2 / (2.R1) ei ... (9) is obtained.
【００１７】したがって、図１に示す回路構成では、Ｒ
1及びＲ2の抵抗値の比によって決まる増幅度を有する平
衡入力平衡出力増幅回路となる。そして、差動増幅回路
７により、平衡入力信号の差成分のみが増幅されなが
ら、正相の出力信号と逆相の出力信号は、基準電位に対
して対称となる平衡出力が得られるとともに、入力信号
の基準電位と出力信号の基準電位を同一にできる。Therefore, in the circuit configuration shown in FIG.
The balanced input balanced output amplifier circuit has an amplification degree determined by the ratio of the resistance values of 1 and R2. Then, while the differential amplifier circuit 7 amplifies only the difference component of the balanced input signal, the positive-phase output signal and the negative-phase output signal obtain a balanced output that is symmetrical with respect to the reference potential, and The reference potential of the signal and the reference potential of the output signal can be the same.
【００１８】[0018]
【発明の効果】本発明によれば、入力信号の基準電位と
出力信号の基準電位が一致しているので、電源の中点電
位を基準電位とすることができ、最大出力を大きくする
ことができる。また、出力信号の基準電位に対して正相
の出力信号と逆相の出力信号が対称な信号波形となるの
で、出力信号電流が基準電位に流れることが無く、電源
ライン等からの雑音の影響を受け難くすることができ
る。According to the present invention, since the reference potential of the input signal and the reference potential of the output signal match, the midpoint potential of the power supply can be used as the reference potential and the maximum output can be increased. it can. Further, since the positive-phase output signal and the negative-phase output signal have symmetrical signal waveforms with respect to the reference potential of the output signal, the output signal current does not flow to the reference potential, and the influence of noise from the power supply line, etc. Can be made hard to receive.
【図１】本発明の一実施例を示す回路図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
【図２】従来例を示す回路図。FIG. 2 is a circuit diagram showing a conventional example.
【図３】従来例を説明するための模式図。FIG. 3 is a schematic diagram for explaining a conventional example.
１，２ 入力端 ３，４，７ 差動増幅回路 ５，６ 出力端 1, 2 Input terminal 3, 4, 7 Differential amplifier circuit 5, 6 Output terminal
Claims (2)
増幅する第１及び第２の増幅回路と、前記第１及び第２
の増幅回路の出力信号を反転入力に加える第３の増幅回
路と、前記第３の増幅回路の非反転入力に基準電位を与
え、前記第３の増幅回路の出力を前記第１及び第２の増
幅回路の非反転入力に加算する加算回路を具備すること
を特徴とする平衡増幅回路。1. A first and a second amplifier circuit for amplifying a signal between an inverting input and a non-inverting input, and the first and second amplifier circuits.
A reference potential is applied to a third amplifier circuit that applies the output signal of the amplifier circuit to the inverting input and a non-inverting input of the third amplifier circuit, and the output of the third amplifier circuit is applied to the first and second amplifier circuits. A balanced amplifier circuit comprising an adder circuit for adding to a non-inverting input of the amplifier circuit.
る第１及び第２の差動増幅回路と、該第１及び第２の差
動増幅回路の出力をそれぞれの反転入力に帰還する抵抗
と、前記第１及び第２の差動増幅回路の出力をそれぞれ
抵抗を介して反転入力に入力する第３の差動増幅回路
と、該第３の差動増幅回路の非反転入力に入力する基準
電位と、該第３の差動増幅回路の出力を前記第１及び第
２の差動増幅回路のそれぞれの非反転入力に入力する抵
抗を具備することを特徴とする平衡増幅回路。2. A first and second differential amplifier circuit for applying an input signal to each non-inverting input, and a resistor for feeding back the outputs of the first and second differential amplifier circuits to their respective inverting inputs. A third differential amplifier circuit for inputting the outputs of the first and second differential amplifier circuits to inverting inputs via resistors, and a reference for inputting to the non-inverting input of the third differential amplifier circuit. A balanced amplifier circuit comprising a potential and a resistor for inputting the output of the third differential amplifier circuit to the respective non-inverting inputs of the first and second differential amplifier circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7077359A JPH08250943A (en) | 1995-03-08 | 1995-03-08 | Balanced amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7077359A JPH08250943A (en) | 1995-03-08 | 1995-03-08 | Balanced amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08250943A true JPH08250943A (en) | 1996-09-27 |
Family
ID=13631721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7077359A Withdrawn JPH08250943A (en) | 1995-03-08 | 1995-03-08 | Balanced amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08250943A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030037012A (en) * | 2001-11-01 | 2003-05-12 | 주식회사 미토스엠텍 | Balance amplifier circuit |
| FR2936117A1 (en) * | 2008-09-18 | 2010-03-19 | Peugeot Citroen Automobiles Sa | Parasite rejection enhancing circuit for semi-differential connection to transport stereo signal towards input stage of audio processing equipment in automobile field, has resistor with terminal set to reference potential |
-
1995
- 1995-03-08 JP JP7077359A patent/JPH08250943A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030037012A (en) * | 2001-11-01 | 2003-05-12 | 주식회사 미토스엠텍 | Balance amplifier circuit |
| FR2936117A1 (en) * | 2008-09-18 | 2010-03-19 | Peugeot Citroen Automobiles Sa | Parasite rejection enhancing circuit for semi-differential connection to transport stereo signal towards input stage of audio processing equipment in automobile field, has resistor with terminal set to reference potential |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7498879B2 (en) | Summing comparator for higher order class D amplifiers | |
| US7671674B2 (en) | Amplifier circuit with automatic gain correction | |
| US6816003B2 (en) | Circuits with dynamic biasing | |
| JP2001223546A (en) | Multistage signal amplifier circuit | |
| EP0415080B1 (en) | Device for converting unbalanced analog electric signals into fully-differential signals | |
| JPS6041882B2 (en) | An amplifier comprising first and second amplification elements | |
| JP3068642B2 (en) | Circuit for detecting output distortion | |
| WO2000070755A1 (en) | Signal amplifier and balanced input/output differential amplifier | |
| US10797665B2 (en) | Programmable gain amplifier systems and methods | |
| US6838935B2 (en) | Signal amplifier | |
| US5903189A (en) | High gain low distortion bridge amplifier with feedback | |
| JPH08250943A (en) | Balanced amplifier circuit | |
| JPH1117478A (en) | Power amplifier | |
| JPH08148950A (en) | Balanced amplifier circuit | |
| JPH0575362A (en) | Balanced amplifier | |
| JP3179838B2 (en) | Noise detection circuit | |
| JP2000031758A (en) | Balanced amplifier circuit | |
| US6822509B2 (en) | Differential circuit with a linearity correction loop | |
| JP2993532B2 (en) | Excitation circuit of Wheatstone bridge type load cell | |
| JPH062335Y2 (en) | Balanced amplifier | |
| JPH0635540Y2 (en) | Differential amplifier | |
| US6046634A (en) | Amplifier circuit employing floating error cancellation | |
| JPS6340904Y2 (en) | ||
| JPH0661874A (en) | Linear transmission circuit | |
| JP2000155139A (en) | Current detecting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020604 |