JPH08248386A - Active matrix substrate - Google Patents
Active matrix substrateInfo
- Publication number
- JPH08248386A JPH08248386A JP7048893A JP4889395A JPH08248386A JP H08248386 A JPH08248386 A JP H08248386A JP 7048893 A JP7048893 A JP 7048893A JP 4889395 A JP4889395 A JP 4889395A JP H08248386 A JPH08248386 A JP H08248386A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- film
- carbide
- active matrix
- matrix substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 85
- 239000011159 matrix material Substances 0.000 title claims abstract description 73
- 239000004020 conductor Substances 0.000 claims abstract description 114
- 229910021385 hard carbon Inorganic materials 0.000 claims abstract description 68
- 239000012212 insulator Substances 0.000 claims abstract description 49
- 239000010409 thin film Substances 0.000 claims abstract description 35
- 239000010408 film Substances 0.000 claims description 136
- 239000000470 constituent Substances 0.000 claims description 5
- 230000007774 longterm Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 20
- 239000004973 liquid crystal related substance Substances 0.000 description 16
- 238000004544 sputter deposition Methods 0.000 description 12
- 230000007547 defect Effects 0.000 description 10
- 125000004429 atom Chemical group 0.000 description 9
- 239000007789 gas Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 238000007740 vapor deposition Methods 0.000 description 7
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229930195733 hydrocarbon Natural products 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000000704 physical effect Effects 0.000 description 6
- 239000005297 pyrex Substances 0.000 description 6
- -1 CH 4 Chemical class 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 150000002430 hydrocarbons Chemical class 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 238000000862 absorption spectrum Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 238000002329 infrared spectrum Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000001308 synthesis method Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 150000004945 aromatic hydrocarbons Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 229910052798 chalcogen Inorganic materials 0.000 description 1
- 150000001787 chalcogens Chemical class 0.000 description 1
- 238000012629 conventional elemental analysis Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002050 diffraction method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000005426 magnetic field effect Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- JRZJOMJEPLMPRA-UHFFFAOYSA-N olefin Natural products CCCCCCCC=C JRZJOMJEPLMPRA-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 239000012188 paraffin wax Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はアクティブマトリクス基
板に関し、詳しくは、ワードプロセッサやパーソナルコ
ンピュータ、電子ブック等のフラットパネルディスプレ
イ等に好適に使用しうるアクティブマトリクス基板、特
に大容量液晶表示装置のスイッチング素子として有用な
アクティブマトリクス基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate, and more particularly, to an active matrix substrate which can be suitably used for a flat panel display such as a word processor, a personal computer, an electronic book, etc., especially a switching element of a large capacity liquid crystal display device. The present invention relates to an active matrix substrate useful as
【０００２】[0002]
【従来の技術】近年、液晶表示装置（ＬＣＤ）は薄型軽
量で、消費電力が小さいという特色を持っていることか
ら、ディスプレイとしての市場が急速に大きくなってい
る。特にＯＡ機器やＴＶには大面積液晶ディスプレイ使
用の要望が強く、そのため、アクティブマトリクス方式
では各画素ごとにスイッチング素子を設け電圧を印加す
るよう工夫されている。前記スイッチング素子の一つと
して薄膜二端子素子が多く使われている。これは薄膜二
端子素子がスイッチングに好適な非線形の電流−電圧特
性（Ｉ−Ｖ特性）を示すためである。従来からの二端子
素子としては、ガラスなどの絶縁性基板上に下部電極と
してＡｌ，Ｔａ，Ｔｉ，Ｃｒ等の金属電極を設け、その
上に前記金属の酸化物、窒化物あるいは他の絶縁膜を設
け、さらにその上に上部電極としてＡｌ，Ｎｉ，Ｃｒ等
の金属電極を設けたＭＩＭ（Metal-Insurator-Metal)素
子などが知られている。このＭＩＭ素子を用いて、液晶
表示装置の中間調表示を行なう場合には液晶への印加電
圧はあるフレームの走査期間内で時定数ＣLC・ＲON（液
晶容量・ＭＩＭ素子のオン抵抗）により充電され、これ
によって液晶が駆動される。2. Description of the Related Art In recent years, a liquid crystal display device (LCD) has a feature that it is thin and lightweight and consumes less power, so that the market as a display is rapidly expanding. In particular, there is a strong demand to use a large-area liquid crystal display for OA devices and TVs. Therefore, in the active matrix system, a switching element is provided for each pixel to apply a voltage. A thin film two-terminal device is often used as one of the switching devices. This is because the thin film two-terminal element exhibits a non-linear current-voltage characteristic (IV characteristic) suitable for switching. As a conventional two-terminal element, a metal electrode of Al, Ta, Ti, Cr or the like is provided as a lower electrode on an insulating substrate such as glass, and an oxide, nitride or other insulating film of the metal is provided thereon. There is known a MIM (Metal-Insurator-Metal) element in which a metal electrode of Al, Ni, Cr or the like is further provided as an upper electrode on the above. When a halftone display of a liquid crystal display device is performed using this MIM element, the voltage applied to the liquid crystal depends on the time constant C LC · R ON (liquid crystal capacitance · ON resistance of the MIM element) within a scanning period of a frame. It is charged and the liquid crystal is driven by this.
【０００３】また特に、絶縁膜に金属酸化物を用いたＭ
ＩＭ素子（特開昭５７−１９６５８９号、特開昭６２−
６２３３３号等の公報参照）の場合、絶縁膜は下部電極
の陽極酸化または熱酸化により形成されるため、工程が
複雑であり、しかも高温熱処理を必要とし、また膜の制
御性（膜質及び膜厚の均一性及び再現性）に劣る上、基
板が耐熱材料に限られること、及び、絶縁膜は物性が一
定な金属酸化物からなることなどから、素子の材料や特
性を自由に変えることが出来ず、設計上の自由度が狭い
という欠点が有る。これはアクティブマトリクス基板を
用いた液晶表示装置からの仕様を充分に満たすデバイス
を設計、作成することが困難で有ることを意味する。ま
たこのように膜制御性が悪いと、素子特性としてのＩ−
Ｖ特性やＩ−Ｖ特性の対称性（プラスバイアス時とマイ
ナスバイアス時の電流比）のバラツキが大きくなるとい
う問題も生じる。その他、ＭＩＭ素子を液晶表示装置に
使用する場合、液晶部容量／ＭＩＭ素子容量比は一般に
１０以上が望ましいが、金属酸化物の場合、誘電率が大
きいことから素子容量も大きくなり、従って素子容量を
減少させること、即ち素子面積を小さくするための微細
加工を必要とする。またこの場合、液晶材料封入前のラ
ビング工程等で絶縁膜が機械的損傷を受けることによ
り、微細加工とも相まって歩留まり低下を来すという問
題も有る。尚、多層の絶縁層を用いて薄膜二端子素子の
特性制御範囲を広げ、また絶縁層のショートや、膜の剥
離を防止する（特開平３−６７２２６号公報参照）こと
等も行なわれている。Further, in particular, M in which a metal oxide is used for the insulating film
IM element (JP-A-57-196589, JP-A-62-162)
In the case of Japanese Patent Laid-Open No. 62333), the insulating film is formed by anodic oxidation or thermal oxidation of the lower electrode, so that the process is complicated, high temperature heat treatment is required, and the controllability of the film (film quality and film thickness) Since the substrate is limited to heat-resistant materials and the insulating film is made of metal oxide with constant physical properties, it is possible to freely change the material and characteristics of the element. However, there is a drawback that the degree of freedom in design is narrow. This means that it is difficult to design and manufacture a device that sufficiently satisfies the specifications from the liquid crystal display device using the active matrix substrate. If the film controllability is poor, I-
There is also a problem that the symmetry of the V characteristic and the IV characteristic (the current ratio between the positive bias and the negative bias) becomes large. In addition, when the MIM element is used in a liquid crystal display device, the liquid crystal part capacitance / MIM element capacitance ratio is generally desired to be 10 or more. However, in the case of a metal oxide, the element capacitance is large because the dielectric constant is large, and therefore the element capacitance is large. Is required, that is, fine processing for reducing the element area is required. Further, in this case, there is also a problem that the insulating film is mechanically damaged in a rubbing process before encapsulating the liquid crystal material and the yield is reduced in combination with the fine processing. Incidentally, it is also attempted to widen the characteristic control range of the thin film two-terminal element by using a multi-layered insulating layer and prevent short circuit of the insulating layer and peeling of the film (see Japanese Patent Laid-Open No. 3-67226). .
【０００４】[0004]
【発明が解決しようとする課題】従来技術ではアクティ
ブマトリクス基板作製時に第一導体と絶縁体層の組み合
わせによっては、所定の形状にパターンを形成した第一
導体上に、蒸着法、スパッタリング法、ＣＶＤ（Chemic
al Vapor Deposition，化学気相成長)法などを用いて絶
縁体層を作製する際に、絶縁体層の付着力が不足して、
基板及び下部電極と絶縁体層の界面から膜剥がれが起き
ることがある。あるいは液晶表示装置完成後に、徐々に
微視的な剥離が生じて特性が変化し、経時的信頼性が劣
る場合がある。In the prior art, depending on the combination of the first conductor and the insulator layer during the production of the active matrix substrate, the vapor deposition method, the sputtering method, the CVD method are formed on the first conductor having a pattern formed in a predetermined shape. (Chemic
Al Vapor Deposition, chemical vapor deposition) method, etc., is used to form the insulator layer, the adhesion of the insulator layer is insufficient,
Film peeling may occur from the interface between the substrate and the lower electrode and the insulating layer. Alternatively, after completion of the liquid crystal display device, microscopic peeling may occur gradually to change the characteristics and deteriorate the reliability over time.
【０００５】本発明は上記事情に鑑みなされたものであ
って、薄膜二端子素子の電極を構成する導体と絶縁体層
の剥離を防止し、素子部の段差による電極の断線と電極
間の短絡を防いだ薄膜二端子素子を提供することを目的
とし、さらに、アクティブマトリクス基板のスイッチン
グ素子として、該薄膜二端子素子を使用することによ
り、特性変化がなく、長期安定性や信頼性の向上したア
クティブマトリクス基板を提供することを目的とする。The present invention has been made in view of the above circumstances, and prevents peeling of a conductor and an insulating layer constituting an electrode of a thin film two-terminal element, disconnection of the electrode due to a step of the element portion and short circuit between the electrodes. In order to provide a thin-film two-terminal element that prevents the above-mentioned problems, and by using the thin-film two-terminal element as a switching element of an active matrix substrate, there is no characteristic change and long-term stability and reliability are improved. It is an object to provide an active matrix substrate.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するた
め、請求項１記載の発明は、第一導体（下部電極）と第
二導体（上部電極）の間に硬質炭素からなる絶縁体層を
有し、前記第一導体または第二導体を表示用電極に接続
してなるアクティブマトリクス基板において、第一導体
と硬質炭素、及び／または第二導体と硬質炭素の間に導
体の構成元素の炭化物を含む層を有する構成とした。To achieve the above object, the invention according to claim 1 provides an insulating layer made of hard carbon between a first conductor (lower electrode) and a second conductor (upper electrode). In an active matrix substrate having the first conductor or the second conductor connected to a display electrode, a carbide of a constituent element of the conductor between the first conductor and the hard carbon and / or the second conductor and the hard carbon. It is configured to have a layer including.
【０００７】請求項２記載の発明は、請求項１記載のア
クティブマトリクス基板において、第一導体と絶縁体層
の間に該導体の炭化物を含む層を形成してあり、該炭化
物層と第一導体が同じ形状に加工してあるとき、硬質炭
素の膜厚が炭化物の膜厚と第一導体の膜厚の和よりも大
きい構成とした。According to a second aspect of the present invention, in the active matrix substrate according to the first aspect, a layer containing carbide of the conductor is formed between the first conductor and the insulating layer, and the carbide layer and the first layer are provided. When the conductors were processed into the same shape, the film thickness of the hard carbon was larger than the sum of the film thickness of the carbide and the film thickness of the first conductor.
【０００８】請求項３記載の発明は、請求項１記載のア
クティブマトリクス基板において、第一導体と絶縁体層
の間に該導体の炭化物を含む層を形成してあり、該炭化
物層と絶縁体層が同じ形状に加工してあるとき、硬質炭
素の膜厚と炭化物の膜厚の和が第一導体の膜厚よりも大
きい構成とした。According to a third aspect of the present invention, in the active matrix substrate according to the first aspect, a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer and the insulator are formed. When the layers were processed into the same shape, the sum of the thickness of the hard carbon and the thickness of the carbide was set to be larger than the thickness of the first conductor.
【０００９】請求項４記載の発明は、請求項１記載のア
クティブマトリクス基板において、第二導体と絶縁体層
の間に該導体の炭化物を含む層を形成してあり、該炭化
物層と第二導体が同じ形状に加工してあるとき、硬質炭
素の膜厚が炭化物の膜厚と第二導体の膜厚の和よりも小
さい構成とした。According to a fourth aspect of the present invention, in the active matrix substrate according to the first aspect, a layer containing carbide of the conductor is formed between the second conductor and the insulator layer, and the carbide layer and the second layer are formed. When the conductors were processed into the same shape, the hard carbon film thickness was smaller than the sum of the carbide film thickness and the second conductor film thickness.
【００１０】請求項５記載の発明は、請求項１記載のア
クティブマトリクス基板において、第二導体と絶縁体層
の間に該導体の炭化物を含む層を形成してあり、該炭化
物層と絶縁体層が同じ形状に加工してあるとき、硬質炭
素の膜厚と炭化物の膜厚の和が第二導体の膜厚よりも小
さい構成とした。According to a fifth aspect of the present invention, in the active matrix substrate according to the first aspect, a layer containing a carbide of the conductor is formed between the second conductor and the insulator layer, and the carbide layer and the insulator are formed. When the layers were processed into the same shape, the sum of the thickness of the hard carbon and the thickness of the carbide was smaller than that of the second conductor.
【００１１】請求項６記載の発明は、請求項１記載のア
クティブマトリクス基板において、第一導体と絶縁体層
の間に該導体の炭化物を含む層を形成してあり、薄膜二
端子素子部で炭化物層と第一導体、表示用電極が同じ形
状に加工してあるとき、硬質炭素の膜厚が炭化物の膜厚
と第一導体の膜厚と表示用電極の膜厚の和よりも大きい
構成とした。According to a sixth aspect of the present invention, in the active matrix substrate according to the first aspect, a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the thin film two-terminal element portion is formed. When the carbide layer, the first conductor, and the display electrode are processed into the same shape, the hard carbon film thickness is larger than the sum of the carbide film thickness, the first conductor film thickness, and the display electrode film thickness. And
【００１２】請求項７記載の発明は、請求項１記載のア
クティブマトリクス基板において、第一導体と絶縁体層
の間に該導体の炭化物を含む層を形成してあり、薄膜二
端子素子部で炭化物層と絶縁体層が同じ形状に加工して
あるとき、硬質炭素の膜厚と炭化物の膜厚の和が第一導
体の膜厚と表示用電極の膜厚の和よりも大きい構成とし
た。According to a seventh aspect of the present invention, in the active matrix substrate according to the first aspect, a layer containing carbide of the conductor is formed between the first conductor and the insulating layer, and the thin film two-terminal element portion is formed. When the carbide layer and the insulator layer are processed into the same shape, the sum of the thickness of the hard carbon and the thickness of the carbide is larger than the sum of the thickness of the first conductor and the thickness of the display electrode. .
【００１３】[0013]
【作用】本発明では、第一導体（下部電極）と第二導体
（上部電極）の間に硬質炭素からなる絶縁体層を有し、
前記第一導体または第二導体を表示用電極に接続してな
るアクティブマトリクス基板において、第一導体と硬質
炭素、及び／または第二導体と硬質炭素の間に導体の構
成元素の炭化物を含む層を有する構成とした（請求項
１）ことにより、該導体と絶縁体層が剥離することが防
止される。In the present invention, an insulating layer made of hard carbon is provided between the first conductor (lower electrode) and the second conductor (upper electrode),
In the active matrix substrate formed by connecting the first conductor or the second conductor to a display electrode, a layer containing a carbide of a constituent element of the conductor between the first conductor and the hard carbon and / or the second conductor and the hard carbon. By adopting a configuration having (1), the conductor and the insulating layer are prevented from peeling off.
【００１４】また、上記アクティブマトリクス基板にお
いて、第一導体と絶縁体層の間に該導体の炭化物を含む
層を形成してあり、該炭化物層と第一導体が同じ形状に
加工してあるとき、硬質炭素の膜厚が炭化物の膜厚と第
一導体の膜厚の和よりも大きい構成とする（請求項
２）、第一導体と絶縁体層の間に該導体の炭化物を含む
層を形成してあり、該炭化物層と絶縁体層が同じ形状に
加工してあるとき、硬質炭素の膜厚と炭化物の膜厚の和
が第一導体の膜厚よりも大きい構成とする（請求項
３）、第二導体と絶縁体層の間に該導体の炭化物を含む
層を形成してあり、該炭化物層と第二導体が同じ形状に
加工してあるとき、硬質炭素の膜厚が炭化物の膜厚と第
二導体の膜厚の和よりも小さい構成とする（請求項
４）、第二導体と絶縁体層の間に該導体の炭化物を含む
層を形成してあり、該炭化物層と絶縁体層が同じ形状に
加工してあるとき、硬質炭素の膜厚と炭化物の膜厚の和
が第二導体の膜厚よりも小さい構成とする（請求項
５）、第一導体と絶縁体層の間に該導体の炭化物を含む
層を形成してあり、薄膜二端子素子部で炭化物層と第一
導体、表示用電極が同じ形状に加工してあるとき、硬質
炭素の膜厚が炭化物の膜厚と第一導体の膜厚と表示用電
極の膜厚の和よりも大きい構成とする（請求項６）、第
一導体と絶縁体層の間に該導体の炭化物を含む層を形成
してあり、薄膜二端子素子部で炭化物層と絶縁体層が同
じ形状に加工してあるとき、硬質炭素の膜厚と炭化物の
膜厚の和が第一導体の膜厚と表示用電極の膜厚の和より
も大きい構成とする（請求項７）、ことにより、硬質炭
素からなる絶縁体層を挾んで上下電極が短絡することが
なく、かつ、上部電極が断線することがない薄膜二端子
素子を作製することができる。したがって、アクティブ
マトリクス基板の作製プロセスにおいて、歩留まりが向
上し、コストを低減させることができる。In the above active matrix substrate, a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer and the first conductor are processed into the same shape. The hard carbon has a thickness larger than the sum of the thickness of the carbide and the thickness of the first conductor (claim 2), and a layer containing the carbide of the conductor is provided between the first conductor and the insulator layer. When the carbide layer and the insulator layer are formed to have the same shape, the sum of the film thickness of hard carbon and the film thickness of carbide is larger than the film thickness of the first conductor. 3), a layer containing carbide of the conductor is formed between the second conductor and the insulator layer, and when the carbide layer and the second conductor are processed into the same shape, the film thickness of hard carbon is carbide. Between the second conductor and the insulator layer, wherein the thickness is smaller than the sum of the film thickness of the second conductor and the film thickness of the second conductor (claim 4). When a layer containing carbide of the conductor is formed and the carbide layer and the insulator layer are processed into the same shape, the sum of the film thickness of hard carbon and the film thickness of carbide is smaller than the film thickness of the second conductor. And a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer, the first conductor, and the display electrode are formed in the thin-film two-terminal element portion. When processed into the same shape, the hard carbon film thickness is larger than the sum of the carbide film thickness, the first conductor film thickness, and the display electrode film thickness (claim 6). When a layer containing a carbide of the conductor is formed between the conductor and the insulator layer and the carbide layer and the insulator layer are processed into the same shape in the thin film two-terminal element portion, the film thickness of the hard carbon and the carbide The sum of the film thicknesses of the two is larger than the sum of the film thickness of the first conductor and the film thickness of the display electrode (Claim 7). Without the upper and lower electrodes shorted by sandwiching an insulator layer made of hydrogen and can be a thin film two-terminal element is not the upper electrode disconnected. Therefore, in the manufacturing process of the active matrix substrate, the yield can be improved and the cost can be reduced.
【００１５】また、本発明のアクティブマトリクス基板
において、絶縁層として用いる硬質炭素膜は、 １）プラズマＣＶＤ法等の気相合成法で作製されるた
め、成膜条件によって物性（比誘電率（ε），比抵抗
（ρ））が広範囲に制御でき、従って、デバイス設計の
自由度が大きい、 ２）硬質でしかも厚膜にできるため、機械的損傷を受け
がたく、また、厚膜化によるピンホールの減少も期待で
きる、 ３）室温付近の低温においても良質な膜を形成できるの
で、基板材質に制約がない、 ４）膜厚、膜質の均一性に優れているため薄膜デバイス
用として適している、 ５）誘電率が低いので、高度の微細加工技術を必要とせ
ず、したがって素子の大面積化に有利である、等の特徴
を有し、このような絶縁膜を用いた薄膜二端子素子は液
晶表示用スイッチング素子として好適である。Further, in the active matrix substrate of the present invention, the hard carbon film used as the insulating layer is formed by 1) a vapor phase synthesis method such as a plasma CVD method, so that the physical properties (relative permittivity (ε ), The specific resistance (ρ)) can be controlled in a wide range, and therefore the degree of freedom in device design is large. It can be expected to reduce the number of holes. 3) There is no restriction on the substrate material because a good film can be formed even at low temperatures near room temperature. 4) It is suitable for thin film devices because it has excellent uniformity in film thickness and film quality. 5) The thin-film two-terminal element using such an insulating film has the characteristics that it has a low dielectric constant and does not require high-level fine processing technology, and is therefore advantageous for increasing the area of the element. Is for liquid crystal display It is suitable as switching elements.
【００１６】ここで図１及び図７で表されたアクティブ
マトリクス基板上の薄膜二端子素子の電流−電圧特性
（Ｉ−Ｖ特性）を調べてみると、この特性は近似的に以
下に示すような伝導式で表される。When the current-voltage characteristic (IV characteristic) of the thin film two-terminal element on the active matrix substrate shown in FIGS. 1 and 7 is examined, this characteristic is approximately as shown below. It is expressed by a simple conduction formula.
【００１７】[0017]
【数１】 但し、Ｉ：電流、Ｖ：印加電圧、κ：導電係数、β：プ
ールフレンケル係数、ｎ：キャリア密度、μ：キャリア
モビリティ、ｑ：電子の電荷量、Φ：トラップ深さ、
ρ：比抵抗、ｄ：絶縁膜の膜厚、ｋ：ボルツマン定数、
Ｔ：雰囲気温度、ε：絶縁膜の比誘電率、である。[Equation 1] However, I: current, V: applied voltage, κ: conductivity coefficient, β: pool Frenkel coefficient, n: carrier density, μ: carrier mobility, q: electron charge amount, Φ: trap depth,
ρ: specific resistance, d: thickness of insulating film, k: Boltzmann constant,
T: atmosphere temperature, ε: dielectric constant of insulating film.
【００１８】次に、本発明のアクティブマトリクス基板
において絶縁膜として用いられる硬質炭素膜について詳
しく説明する。この膜は、炭素及び水素原子を主要な組
織形成元素として非晶質及び微結晶の少なくとも一方を
含む硬質炭素膜（ｉ−Ｃ膜、ダイヤモンド状炭素膜、ア
モルファスダイヤモンド膜、ダイヤモンド薄膜とも呼ば
れる）からなっている。硬質炭素膜の一つの特徴は気相
成長膜であるがために、後述するように、その諸物性が
成膜条件によって広範囲に制御できることである。従っ
て、絶縁膜といってもその抵抗値は半導体から絶縁体ま
での領域をカバーしており、この意味では本発明の薄膜
二端子素子はＭＩＭ素子はもちろんのこと、それ以外で
も例えば特開昭６１−２６０２１９号公報で言うところ
のＭＳＩ素子（Metal-Semi-Insurator）やＳＩＳ（半導
体−絶縁体−半導体であって、ここでの「半導体」は不
純物を高濃度にドープさせたものである）としても位置
付けられるものである。Next, the hard carbon film used as an insulating film in the active matrix substrate of the present invention will be described in detail. This film is a hard carbon film (also called i-C film, diamond-like carbon film, amorphous diamond film, diamond thin film) containing at least one of amorphous and microcrystalline with carbon and hydrogen atoms as main texture-forming elements. Has become. One characteristic of the hard carbon film is that it is a vapor phase growth film, and as described later, its physical properties can be controlled in a wide range depending on the film forming conditions. Therefore, even if it is an insulating film, its resistance value covers the region from the semiconductor to the insulator. In this sense, the thin film two-terminal element of the present invention is not limited to the MIM element, but other than that, for example, Japanese Patent Application Laid-Open No. 61-260219 MSI element (Metal-Semi-Insurator) or SIS (semiconductor-insulator-semiconductor, where "semiconductor" here is one doped with a high concentration of impurities) It is also positioned as.
【００１９】尚、この硬質炭素膜中には、さらに物性制
御範囲を広げるために、構成元素の一つとして少なくと
も周規律表第III族元素を全構成元素に対し５原子％以
下、同じく第IＶ族元素を３５原子％以下、同じく第Ｖ
族元素を５原子％以下、アルカリ土類金属元素を５原子
％以下、アルカリ金属元素を５原子％以下、窒素原子を
５原子％以下、酸素原子を５原子％以下、カルコゲン元
素を３５原子％以下、またはハロゲン元素を３５原子％
以下の量で含有させても良い。これら元素または原子の
量は元素分析の常法、例えばオージェ分析によって測定
することができる。または、この量の多少は原料ガスに
含まれる他の化合物の量や成膜条件で調節可能である。In this hard carbon film, in order to further expand the physical property control range, at least 5 Group% of the elements in the Periodic Table of the Periodic Table as one of the constituent elements, relative to all the constituent elements, and also the IV group. 35 atom% or less of group element, also V group
Group elements of 5 atom% or less, alkaline earth metal elements of 5 atom% or less, alkali metal elements of 5 atom% or less, nitrogen atoms of 5 atom% or less, oxygen atoms of 5 atom% or less, chalcogen elements of 35 atom% or less. Or less, or 35 atom% halogen element
You may contain in the following amounts. The amount of these elements or atoms can be measured by a conventional elemental analysis method, for example, Auger analysis. Alternatively, this amount can be adjusted to some extent by the amount of other compound contained in the source gas and the film forming conditions.
【００２０】こうした硬質炭素膜を形成するためには有
機化合物ガス、特に炭化水素ガスが用いられる。これら
原料における相状態は常温常圧において必ずしも気相で
ある必要はなく、加熱あるいは減圧等により溶融、蒸
発、昇華を経て気化しうるものであれば、液相でも固相
でも使用可能である。原料ガスとしての炭化水素ガスに
ついては、例えばＣＨ4、Ｃ3Ｈ8、Ｃ4Ｈ10等のパラフィ
ン系炭化水素、Ｃ2Ｈ4等のオレフィン系炭化水素、ジオ
レフィン系炭化水素、アセチレン系炭化水素、さらには
芳香族炭化水素など全ての炭化水素を少なくとも含むガ
スが使用可能である。To form such a hard carbon film, an organic compound gas, especially a hydrocarbon gas is used. The phase state of these raw materials does not necessarily have to be a gas phase at room temperature and atmospheric pressure, and a liquid phase or a solid phase can be used as long as it can be vaporized by being melted, evaporated, sublimated by heating or decompressing. Examples of the hydrocarbon gas as the raw material gas include paraffin hydrocarbons such as CH 4 , C 3 H 8 and C 4 H 10 , olefin hydrocarbons such as C 2 H 4 , diolefin hydrocarbons and acetylene carbon. A gas containing at least all hydrocarbons such as hydrogen and aromatic hydrocarbons can be used.
【００２１】本発明における原料ガスからの硬質炭素膜
の形成方法としては、成膜活性種が、直流、低周波、高
周波、あるいはマイクロ波等を用いたプラズマ法により
生成されるプラズマ状態を経て形成される方法が好まし
いが、より大面積化、均一性向上及び／または低温成膜
の目的で低圧下で堆積を行なわせしめるのには磁界効果
を利用する方法がさらに好ましい。また、高温における
熱分解によっても活性種を形成できる。その他にも、イ
オン化蒸着法、あるいはイオンビーム蒸着法等により生
成されるイオン状態を経て形成されても良いし、真空蒸
着法、あるいはスパッタリング法等により生成される中
性粒子から形成されても良いし、さらには、これらの組
み合わせにより形成されても良い。As a method of forming a hard carbon film from a source gas in the present invention, a film formation active species is formed through a plasma state generated by a plasma method using direct current, low frequency, high frequency, or microwave. The above method is preferable, but a method utilizing a magnetic field effect is more preferable for causing the deposition under a low pressure for the purpose of increasing the area, improving the uniformity, and / or forming a film at a low temperature. In addition, active species can also be formed by thermal decomposition at high temperature. Besides, it may be formed through an ion state generated by an ionization vapor deposition method, an ion beam vapor deposition method or the like, or may be formed from neutral particles generated by a vacuum vapor deposition method, a sputtering method or the like. However, it may be formed by a combination thereof.
【００２２】こうして作製される硬質炭素膜の堆積条件
の一例はプラズマＣＶＤの場合、概ね次の通りである。 ＲＦ出力：０．０１〜５０Ｗ／ｃｍ、 圧 力：０．１〜１０００Ｐａ、 堆積温度：室温〜９５０℃で行うことができるが好まし
くは室温〜３００℃。 このプラズマ状態により原料ガスがラジカルとイオンに
分解され反応することによって、基板上に炭素原子Ｃと
水素原子Ｈとからなるアモルファス（非晶質）及び微結
晶（結晶の大きさは数ｎｍから数μｍ）の少なくとも一
方を含む硬質炭素膜が堆積する。硬質炭素膜の諸特性を
表１に示す。In the case of plasma CVD, an example of the deposition conditions of the hard carbon film thus produced is as follows. RF output: 0.01 to 50 W / cm, pressure: 0.1 to 1000 Pa, deposition temperature: room temperature to 950 ° C., preferably room temperature to 300 ° C. The raw material gas is decomposed into radicals and ions by this plasma state and reacts with each other, so that amorphous (amorphous) and microcrystalline (crystal size is several nm to several nm) consisting of carbon atoms C and hydrogen atoms H on the substrate. a hard carbon film containing at least one of Table 1 shows various characteristics of the hard carbon film.
【００２３】[0023]
【表１】 [Table 1]
【００２４】注）測定法 比抵抗（ρ）：コプレナー型セルによるＩ−Ｖ特性より
求める。 光学的バンドギャップ（Ｅgopt）：分光特性から吸収係
数（α）を求め、 （αｈν）＝[β（ｈν−Ｅgopt）]2 の関係より決定する。 膜中水素量[Ｃ（Ｈ）]：赤外吸収スペクトルから２９０
０ｃｍ~1付近のピークを積分し吸収断面積Ａをかけて求
める。すなわち、 ［Ｃ（Ｈ）］＝Ａ・∫α（ν）／ν・ｄν の関係より求める。 ＳＰ3／ＳＰ2比：赤外吸収スペクトルをＳＰ3、ＳＰ2に
それぞれ帰属されるガウス関数に分解し、その面積比よ
り求める。 ビッカース硬度（Ｈ）：マイクロビッカース硬度計によ
る。 屈折率（ｎ）：エリプソメーターによる。 欠陥密度：ＥＳＲによる。Note) Measurement method Specific resistance (ρ): Determined from IV characteristics of a coplanar cell. Optical band gap (Eg opt ): The absorption coefficient (α) is obtained from the spectral characteristics, and is determined from the relationship of (αhν) = [β (hν-Eg opt )] 2 . Hydrogen content in film [C (H)]: 290 from infrared absorption spectrum
The peak near 0 cm to 1 is integrated and the absorption cross section A is multiplied to obtain. That is, it is obtained from the relationship of [C (H)] = A · ∫α (ν) / ν · dν. SP 3 / SP 2 ratio: The infrared absorption spectrum is decomposed into Gaussian functions assigned to SP 3 and SP 2 , respectively, and calculated from the area ratio. Vickers hardness (H): By micro Vickers hardness meter. Refractive index (n): By ellipsometer. Defect density: According to ESR.
【００２５】こうして形成される硬質炭素膜はラマン分
光法及びＩＲ吸収法による分析の結果、それぞれ図９及
び図１０に示すように炭素原子がＳＰ3 の混成軌道とＳ
Ｐ2の混成軌道とを形成した原子間結合が混在している
ことが明らかになっている。ＳＰ3 結合とＳＰ2 結合の
比率は、ＩＲスペクトルをピーク分離することで概ね推
定できる。ＩＲスペクトルには、２８８〜３１５０ｃｍ
~1に多くのモードのスペクトルが重なって測定される
が、それぞれの波数に対応するピークの帰属は明らかに
なっており、図１１に示したごときガウス分布によって
ピーク分離を行ない、それぞれのピーク面積を算出し、
その比率を求めればＳＰ3／ＳＰ2を知ることができる。
また、前記の硬質炭素膜は、Ｘ線及び電子線回折分析に
よればアモルファス状態（ａ−Ｃ：Ｈ）、及び／又は数
ｎｍ〜数百ｎｍ程度の微結晶粒を含むアモルファス状態
にあることがわかる。The hard carbon film thus formed was analyzed by Raman spectroscopy and IR absorption, and as a result, as shown in FIGS. 9 and 10, respectively, a hybrid orbital having carbon atoms of SP 3 and S.
It has been clarified that the interatomic bonds forming the P 2 hybrid orbital are mixed. The ratio of SP 3 bond to SP 2 bond can be roughly estimated by separating peaks in the IR spectrum. IR spectrum has 288-3150 cm
Although the spectrum of many modes is overlapped with ~ 1 , the attribution of the peaks corresponding to each wave number is clear, and the peak separation is performed by the Gaussian distribution as shown in Fig. 11. And calculate
SP 3 / SP 2 can be known by obtaining the ratio.
Further, the hard carbon film is in an amorphous state (a-C: H) according to X-ray and electron beam diffraction analysis, and / or in an amorphous state containing fine crystal grains of about several nm to several hundred nm. I understand.
【００２６】一般に量産に適しているプラズマＣＶＤ法
の場合には、ＲＦ出力が小さいほど膜の比抵抗値及び硬
度が増加し、また低圧力なほど活性種の寿命が増加する
ために、基板温度の低温化、大面積での均一化が図ら
れ、かつ比抵抗、硬度が増加する傾向に有る。更に、低
圧力ではプラズマ密度が減少するため、磁場閉じ込め効
果を利用する方法は、比抵抗の増加には特に効果的であ
る。更にまた、この方法（プラズマＣＶＤ法）は常温〜
１５０℃程度の比較的低い温度条件でも同様に良質の硬
質炭素膜を形成できるという特徴を有しているため、薄
膜二端子素子製造プロセスの低温化には最適である。従
って、使用する基板材料の選択自由度が広がり、基板温
度をコントロールしやすいために均一な膜が得られると
いう特徴を持っている。In the case of the plasma CVD method, which is generally suitable for mass production, the smaller the RF output, the more the specific resistance value and hardness of the film increase, and the lower the pressure, the longer the life of active species. It is possible to achieve low temperature, uniformization over a large area, and increase the specific resistance and hardness. Furthermore, since the plasma density decreases at low pressure, the method of utilizing the magnetic field confinement effect is particularly effective for increasing the specific resistance. Furthermore, this method (plasma CVD method)
Since it has the characteristic that a good quality hard carbon film can be formed even under a relatively low temperature condition of about 150 ° C., it is optimal for lowering the temperature of the thin film two-terminal element manufacturing process. Therefore, the degree of freedom in selecting the substrate material to be used is widened, and the substrate temperature can be easily controlled, so that a uniform film can be obtained.
【００２７】硬質炭素膜の構造、物性は表１に示したよ
うに広範囲に制御可能であるため、デバイス特性を自由
に設計できる利点も有る。さらには膜の誘電率も３〜５
と従来のＭＩＭに使用されていたＴａ2Ｏ5，Ａｌ2Ｏ3，
ＳｉＮX などと比較して小さいため、同じ電気容量を持
った素子を作る場合、素子サイズが大きくて済むので、
それほど微細加工を必要とせず、歩留まりが向上する
（駆動条件の関係からＬＣＤとＭＩＭの容量比はＣLCD
／ＣMIM＝１０：１程度必要である）。さらに膜の硬度
が高いため、液晶材料封入時のラビング工程による素子
の損傷が少なく、この点からも歩留まりが向上する。Since the structure and physical properties of the hard carbon film can be controlled over a wide range as shown in Table 1, there is also an advantage that the device characteristics can be freely designed. Furthermore, the dielectric constant of the film is 3-5.
And Ta 2 O 5 , Al 2 O 3 used in conventional MIM,
Since it is smaller than SiN x, etc., when making elements with the same electric capacity, the element size can be large.
Yield is improved without much need for microfabrication. (Due to driving conditions, the capacitance ratio of LCD and MIM is C LCD.
/ C MIM = about 10: 1 is necessary). Furthermore, since the hardness of the film is high, the element is less damaged by the rubbing process when the liquid crystal material is filled, and the yield is improved also from this point.
【００２８】液晶駆動用薄膜二端子素子として好適な硬
質炭素膜は、駆動条件から膜厚が１０〜８００ｎｍ、比
抵抗が１０6〜１０12Ωｃｍの範囲であることが有利で
ある。尚、駆動電圧と耐圧（絶縁破壊電圧）とのマージ
ンを考慮すると膜厚は２０ｎｍ以上であることが望まし
く、また、画素部と薄膜二端子素子の段差（セルギャッ
プ差）に起因する色ムラが実用上問題とならないように
するには膜厚は６００ｎｍ以下であることが望ましいこ
とから、硬質炭素膜の膜厚は２０〜６００ｎｍ、比抵抗
は５×１０6〜１０12Ωｃｍであることがより好まし
い。The hard carbon film suitable as a thin film two-terminal element for driving a liquid crystal has a film thickness of 10 to 800 nm and a specific resistance of 10 6 to 10 12 Ωcm, which is advantageous in view of driving conditions. In consideration of the margin between the driving voltage and the breakdown voltage (dielectric breakdown voltage), the film thickness is preferably 20 nm or more, and color unevenness caused by a step (cell gap difference) between the pixel portion and the thin film two-terminal element is generated. Since it is desirable that the film thickness is 600 nm or less so as not to cause a problem in practical use, it is more preferable that the hard carbon film has a film thickness of 20 to 600 nm and a specific resistance of 5 × 10 6 to 10 12 Ωcm. preferable.
【００２９】硬質炭素膜のピンホールによる素子の欠陥
数は膜厚の減少にともなって増加し、３０ｎｍ以下では
特に顕著になること（欠陥数は１％を越える）、及び、
膜厚の面内均一性（ひいては素子特性の均一性）が確保
できなくなる（膜厚制御の精度は３ｎｍ程度が限度で、
膜厚のバラツキが１０％を越える）ことから、膜厚は３
０ｎｍ以上であることがより望ましい。また、ストレス
による硬質炭素膜の剥離が起こりにくくするため、及
び、より低デューティ比（望ましくは１／１０００以
下）で駆動するために、膜厚は４００ｎｍ以下であるこ
とがより好ましい。これらを総合して考慮すると、硬質
炭素膜の膜厚は３０〜４００ｎｍ、比抵抗は１０7〜１
０11Ωｃｍであることが一層好ましい。The number of defects of the element due to pinholes in the hard carbon film increases with the decrease of the film thickness, and becomes particularly remarkable when the thickness is 30 nm or less (the number of defects exceeds 1%).
In-plane uniformity of film thickness (and thus uniformity of device characteristics) cannot be ensured (accuracy of film thickness control is limited to about 3 nm,
Since the variation in film thickness exceeds 10%), the film thickness is 3
More preferably, it is 0 nm or more. Further, the film thickness is more preferably 400 nm or less in order to prevent the hard carbon film from peeling off due to stress and to drive at a lower duty ratio (desirably 1/1000 or less). Taking these factors into consideration, the hard carbon film has a thickness of 30 to 400 nm and a specific resistance of 10 7 to 1
More preferably, it is 0 11 Ωcm.
【００３０】次に、本発明の前記アクティブマトリクス
基板の製造法及び構成を図１の例に基づいて説明する。
ガラス、プラスチック板、プラスチックフィルム等の基
板６上にＡｌ，Ｔａ，Ｔｉ，Ｃｒ，Ｎｉ，Ａｕ，Ｃｕ，
Ａｇ，Ｗ，Ｍｏ，Ｐｔ等の導電性薄膜を数十ｎｍから数
百ｎｍの厚さに成膜し、所定のパターンにエッチングし
て下部電極１とする。その上に下部電極の炭化物２を数
ｎｍから数十ｎｍの厚さに形成し、下部電極１と同じパ
ターンにエッチングし、さらに絶縁膜として硬質炭素３
を下部電極とその炭化物膜厚の和より数ｎｍから数百ｎ
ｍ厚く、上下電極の短絡及び上部電極の断線を防止する
ために、より好ましくは１０ｎｍから１００ｎｍ厚く成
膜し所定のパターンにエッチングする。最後に上部電極
４としてＡｌ，Ｔａ，Ｔｉ，Ｃｒ，Ｎｉ，Ｃｏ，Ｆｅ，
Ａｕ，Ｃｕ，Ａｇ，Ｗ，Ｍｏ，Ｐｔ等の導電性薄膜を数
十ｎｍから数百ｎｍの厚さに成膜し、所定のパターンに
エッチングし上部電極を形成する。引き続き表示用電極
５としてＩＴＯ（Indium Tin Oxide），ＺｎＯ：Ａｌ，
Ｉｎ2Ｏ3，ＳｎＯ2 等の透明導電性薄膜を数十から数百
ｎｍの厚さに成膜し所定のパターンにエッチングする。
各薄膜の形成方法としては、スパッタリング、蒸着法、
ＣＶＤ等の慣用の薄膜の形成方法が採用できる。Next, the manufacturing method and structure of the active matrix substrate of the present invention will be described based on the example of FIG.
Al, Ta, Ti, Cr, Ni, Au, Cu, on the substrate 6 such as glass, plastic plate, plastic film, etc.
A conductive thin film of Ag, W, Mo, Pt, or the like is formed to a thickness of several tens nm to several hundreds nm, and is etched into a predetermined pattern to form the lower electrode 1. Carbide 2 of the lower electrode is formed thereon to a thickness of several nm to several tens of nm, the same pattern as the lower electrode 1 is etched, and hard carbon 3 is used as an insulating film.
From the sum of the thickness of the lower electrode and the thickness of the carbide to several nm to several hundreds n
In order to prevent short circuit between the upper and lower electrodes and disconnection of the upper electrode, the thickness is more preferably 10 nm to 100 nm, and the film is etched into a predetermined pattern. Finally, as the upper electrode 4, Al, Ta, Ti, Cr, Ni, Co, Fe,
A conductive thin film of Au, Cu, Ag, W, Mo, Pt, or the like is formed to a thickness of several tens nm to several hundreds nm and is etched into a predetermined pattern to form an upper electrode. Subsequently, as the display electrode 5, ITO (Indium Tin Oxide), ZnO: Al,
A transparent conductive thin film of In 2 O 3 , SnO 2 or the like is formed to a thickness of several tens to several hundreds of nm and etched into a predetermined pattern.
As a method for forming each thin film, sputtering, vapor deposition,
A conventional thin film forming method such as CVD can be adopted.
【００３１】このようにして得られたアクティブマトリ
クス基板は、図１の例に示すように第一導体（下部電
極）１と第二導体（上部電極）４の間に絶縁体層３を有
し、第二導体４を表示用電極に接続してなるアクティブ
マトリクス基板において、第一導体１と硬質炭素３の間
に第一導体の炭化物２を有する構成としたものである。The active matrix substrate thus obtained has an insulator layer 3 between a first conductor (lower electrode) 1 and a second conductor (upper electrode) 4 as shown in the example of FIG. In the active matrix substrate in which the second conductor 4 is connected to the display electrode, the first conductor carbide 2 is provided between the first conductor 1 and the hard carbon 3.
【００３２】[0032]
【実施例】次に、図示の実施例により本発明を具体的に
説明するが、本発明はこれらに限定されるものではな
い。EXAMPLES The present invention will now be specifically described with reference to the illustrated examples, but the present invention is not limited thereto.
【００３３】［実施例１］図１は請求項１，２記載の発
明の一実施例を示すアクティブマトリクス基板の要部断
面図である。本実施例では、図１に示すようにパイレッ
クスガラス基板６上にアクティブマトリクスを以下の様
にして設けた。まずＴｉをスパッタリング法により約５
０ｎｍ厚に堆積し、続いてＴｉＣX を約２０ｎｍ堆積す
る。この積層膜を同じパターンで連続してエッチングし
下部電極１と炭化物膜２を形成した。その後、絶縁体層
３としてプラズマＣＶＤ法を用いて、硬質炭素膜を１０
０ｎｍ堆積した。このときの成膜条件は以下の通りであ
る。 圧力：７Ｐａ ＣＨ4流量：２０SCCM ＲＦパワー：０．５Ｗ／ｃｍ2 [Embodiment 1] FIG. 1 is a sectional view of an essential part of an active matrix substrate showing an embodiment of the present invention. In this embodiment, as shown in FIG. 1, an active matrix is provided on the Pyrex glass substrate 6 as follows. First, Ti is sputtered to about 5
0nm was deposited to a thickness, followed by about 20nm deposited TiC X. This laminated film was continuously etched in the same pattern to form the lower electrode 1 and the carbide film 2. Then, a hard carbon film is formed as the insulator layer 3 by plasma CVD.
0 nm was deposited. The film forming conditions at this time are as follows. Pressure: 7 Pa CH 4 Flow rate: 20 SCCM RF power: 0.5 W / cm 2
【００３４】このようにして成膜した硬質炭素膜をドラ
イエッチングによりパターン化した。続いてこの上にＮ
ｉをスパッタリング法により約１２０ｎｍ堆積し、下部
電極１と交差するパターンでエッチングし上部電極４を
形成し、続いてＩＴＯをスパッタリング法で約５０ｎｍ
の厚さに堆積し、ウェットエッチングして、表示用電極
５を形成した。こうして作製したアクティブマトリクス
基板は、素子部の短絡がなく、欠陥率が非常に低いもの
であった。また炭化物層２に下部電極１と絶縁体層３の
化合物を用いているために下部電極と絶縁体層界面の付
着力が強く、絶縁体層３の剥離が全く無く、信頼性の高
いアクティブマトリクス基板を作製することができた。The hard carbon film thus formed was patterned by dry etching. Then on this N
i is deposited to a thickness of about 120 nm by a sputtering method and is etched in a pattern intersecting with the lower electrode 1 to form an upper electrode 4, and then ITO is deposited to a thickness of about 50 nm by the sputtering method.
And was wet-etched to form a display electrode 5. The active matrix substrate thus manufactured had no element short circuit and had a very low defect rate. Further, since the compound of the lower electrode 1 and the insulator layer 3 is used for the carbide layer 2, the adhesive force at the interface between the lower electrode and the insulator layer is strong, the insulator layer 3 is not peeled off at all, and a highly reliable active matrix is provided. The substrate could be made.
【００３５】［実施例２］図２は請求項１，３記載の発
明の一実施例を示すアクティブマトリクス基板の要部断
面図である。本実施例では、図２に示すようにパイレッ
クスガラス基板６上にアクティブマトリクスを以下の様
にして設けた。まずＴｉをスパッタリング法により約５
０ｎｍ厚に堆積し、所定の形状にエッチングして下部電
極１を形成した。次に炭化物膜２としてＴｉＣX を約２
０ｎｍ堆積し、連続して絶縁体層３としてプラズマＣＶ
Ｄ法を用いて、硬質炭素膜を９０ｎｍ堆積した。これを
ドライエッチングにより一括してパターン化した。続い
てこの上にＮｉをスパッタリング法により約１２０ｎｍ
堆積し、下部電極１と交差するパターンでエッチングし
上部電極４を形成し、続いてＩＴＯをスパッタリング法
で約５０ｎｍの厚さに堆積し、ウェットエッチングし
て、表示用電極５を形成した。こうして作製したアクテ
ィブマトリクス基板は、素子部の短絡がなく、欠陥率が
非常に低いものであった。[Embodiment 2] FIG. 2 is a sectional view of an essential part of an active matrix substrate showing an embodiment of the present invention. In this embodiment, as shown in FIG. 2, an active matrix is provided on the Pyrex glass substrate 6 as follows. First, Ti is sputtered to about 5
The lower electrode 1 was formed by depositing it to a thickness of 0 nm and etching it into a predetermined shape. Next, about 2% of TiC X is used as the carbide film 2.
Plasma CV is deposited as an insulator layer 3 with a thickness of 0 nm.
A hard carbon film was deposited to 90 nm using the D method. This was collectively patterned by dry etching. Then, Ni is sputtered on the surface of this to a thickness of about 120 nm.
The deposited electrode was etched in a pattern intersecting with the lower electrode 1 to form an upper electrode 4, and then ITO was deposited to a thickness of about 50 nm by a sputtering method and wet-etched to form a display electrode 5. The active matrix substrate thus manufactured had no element short circuit and had a very low defect rate.
【００３６】［実施例３］図３は請求項１，４記載の発
明の一実施例を示すアクティブマトリクス基板の要部断
面図である。本実施例では、図３に示すようにパイレッ
クスガラス基板６上にアクティブマトリクスを以下の様
にして設けた。最初にＩＴＯをスパッタリング法で約６
０ｎｍの厚さに堆積し、ウェットエッチングして、表示
用電極５を形成した。次にＡｌを蒸着法により約５０ｎ
ｍ厚に堆積後、パターン化して下部電極１を形成した。
その上に絶縁体層３としてプラズマＣＶＤ法を用いて、
硬質炭素膜を１００ｎｍ堆積し、エッチングして絶縁体
層を形成した。続いてこの上にＮｉＣX １５ｎｍとＮｉ
１２０ｎｍを連続してスパッタリング法により堆積し、
下部電極と交差するパターンで連続してエッチングし炭
化物層２及び上部電極４を形成した。本実施例では硬質
炭素３の膜厚が炭化物２と第二導体（上部電極）４の膜
厚の和より小さくしてあるために、第二導体４の断線が
少なく、欠陥率が低いアクティブマトリクス基板を作製
することができた。[Embodiment 3] FIG. 3 is a sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 4. In this example, an active matrix was provided on the Pyrex glass substrate 6 as follows, as shown in FIG. First, about 6 ITO was sputtered
The display electrode 5 was formed by depositing it to a thickness of 0 nm and performing wet etching. Next, about 50n of Al is vapor-deposited.
After depositing to a thickness of m, the lower electrode 1 was formed by patterning.
By using the plasma CVD method as the insulator layer 3 thereon,
A hard carbon film was deposited to a thickness of 100 nm and etched to form an insulator layer. Then NiC X 15nm and Ni
120 nm continuously deposited by sputtering method,
The carbide layer 2 and the upper electrode 4 were formed by continuous etching in a pattern intersecting with the lower electrode. In the present embodiment, the thickness of the hard carbon 3 is smaller than the sum of the thickness of the carbide 2 and the thickness of the second conductor (upper electrode) 4, so that the second conductor 4 is less broken and the defect rate is low. The substrate could be made.
【００３７】［実施例４］図４は請求項１，５記載の発
明の一実施例を示すアクティブマトリクス基板の要部断
面図である。本実施例では、図４に示すようにパイレッ
クスガラス基板６上にアクティブマトリクスを以下の様
にして設けた。最初にＩＴＯをスパッタリング法で約６
０ｎｍの厚さに堆積し、ウェットエッチングして表示用
電極５を形成した。次にＡｌを蒸着法により約５０ｎｍ
厚に堆積後、パターン化して下部電極１を形成した。そ
の上に絶縁体層３としてプラズマＣＶＤ法を用いて硬質
炭素膜を８０ｎｍ堆積した。さらにＴｉＣX を２０ｎｍ
積層し、硬質炭素とＴｉＣXを同じパターンに連続して
エッチングし炭化物層２と絶縁体層３を形成した。続い
てこの上にＴｉをスパッタリング法により約１２０ｎｍ
堆積し、下部電極１と交差するパターンでエッチングし
上部電極４を形成した。本実施例では硬質炭素３と炭化
物２の膜厚の和が第二導体（上部電極）４の膜厚の和よ
り小さくしてあるために、第二導体４の断線が少なく、
欠陥率が低いアクティブマトリクス基板を作製すること
ができた。[Embodiment 4] FIG. 4 is a sectional view of an essential part of an active matrix substrate showing an embodiment of the present invention. In this embodiment, as shown in FIG. 4, an active matrix is provided on the Pyrex glass substrate 6 as follows. First, about 6 ITO was sputtered
It was deposited to a thickness of 0 nm and wet-etched to form a display electrode 5. Next, about 50 nm of Al is deposited by the vapor deposition method.
After thickly depositing, the lower electrode 1 was formed by patterning. A hard carbon film having a thickness of 80 nm was deposited thereon as the insulator layer 3 by using the plasma CVD method. Furthermore, TiC X is 20 nm
The layers were laminated, and hard carbon and TiC X were successively etched in the same pattern to form a carbide layer 2 and an insulator layer 3. Then, Ti is sputtered on the top surface of the substrate by about 120 nm.
An upper electrode 4 was formed by depositing and etching in a pattern intersecting with the lower electrode 1. In this embodiment, since the sum of the film thicknesses of the hard carbon 3 and the carbide 2 is smaller than the sum of the film thicknesses of the second conductor (upper electrode) 4, the number of disconnections of the second conductor 4 is small,
An active matrix substrate with a low defect rate could be manufactured.
【００３８】尚、図７に実施例１〜４に対応するアクテ
ィブマトリクス基板の薄膜二端子素子部分の平面構成例
を示すが、図１〜４は図７のＡ−Ａ’線部分に相当する
断面図である。また、実施例１，２の場合は図７のよう
に下部電極１の上に表示用電極５が形成されるが、実施
例３，４の場合は図示とは逆に表示用電極５の上に下部
電極１が形成される。Incidentally, FIG. 7 shows an example of a planar structure of the thin film two-terminal element portion of the active matrix substrate corresponding to Embodiments 1 to 4, and FIGS. 1 to 4 correspond to the line AA ′ portion of FIG. 7. FIG. Further, in the case of Examples 1 and 2, the display electrode 5 is formed on the lower electrode 1 as shown in FIG. 7, but in the case of Examples 3 and 4, the display electrode 5 is formed on the contrary to the illustration. The lower electrode 1 is formed on.
【００３９】［実施例５］図５は請求項１，６記載の発
明の一実施例を示すアクティブマトリクス基板の要部断
面図である。本実施例では、図５に示すようにパイレッ
クスガラス基板６上にアクティブマトリクスを以下の様
にして設けた。最初に表示用電極５となるＩＴＯをスパ
ッタリング法で約３０ｎｍの厚さに堆積し、下部電極と
なるＴｉを厚さ３０ｎｍ堆積し、さらに炭化物層２とし
てＴｉＣX を１０ｎｍ堆積し、下部電極１と表示用電極
５を含む形に連続してエッチングして、電極を形成し
た。その上に絶縁体層３としてプラズマＣＶＤ法を用い
て、硬質炭素膜を１１０ｎｍ堆積し、エッチングして絶
縁体層を形成した。続いてこの上にＮｉを１２０ｎｍの
厚さにスパッタリング法により堆積し、下部電極１と交
差するパターンで連続してエッチングし上部電極４を形
成した。最後に表示用電極上のＴｉＣX とＴｉを除去
し、ＩＴＯを露出させ、アクティブマトリクス基板を完
成させた。本実施例では硬質炭素層３の膜厚が炭化物２
と第一導体（下部電極）１と表示用電極５の膜厚の和よ
り大きくしてあるために、上下電極の短絡がなく、欠陥
率が非常に低いものであった。[Embodiment 5] FIG. 5 is a sectional view of an essential part of an active matrix substrate showing an embodiment of the present invention. In this example, an active matrix was provided on the Pyrex glass substrate 6 as follows, as shown in FIG. First, ITO serving as the display electrode 5 is deposited by sputtering to a thickness of about 30 nm, Ti serving as the lower electrode is deposited to a thickness of 30 nm, and TiC X is deposited as the carbide layer 2 to 10 nm to form the lower electrode 1. An electrode was formed by continuously etching in a shape including the display electrode 5. A hard carbon film having a thickness of 110 nm was deposited thereon as the insulator layer 3 by using the plasma CVD method, and the insulator layer was formed by etching. Subsequently, Ni was deposited thereon to a thickness of 120 nm by a sputtering method and continuously etched in a pattern intersecting with the lower electrode 1 to form an upper electrode 4. Finally, TiC X and Ti on the display electrode were removed to expose the ITO, thus completing the active matrix substrate. In this embodiment, the hard carbon layer 3 has a thickness of carbide 2
Since the thickness was made larger than the sum of the film thicknesses of the first conductor (lower electrode) 1 and the display electrode 5, the upper and lower electrodes were not short-circuited and the defect rate was very low.
【００４０】［実施例６］図６は請求項１，７記載の発
明の一実施例を示すアクティブマトリクス基板の要部断
面図である。本実施例では、図６に示すようにパイレッ
クスガラス基板６上にアクティブマトリクスを以下の様
にして設けた。最初に表示用電極５となるＩＴＯをスパ
ッタリング法で約４０ｎｍの厚さに堆積し、ウェットエ
ッチングして、表示用電極５を形成した。次にＡｌをス
パッタリング法により約４０ｎｍ厚に堆積後、素子部で
同じ形状にパターン化して下部電極１を形成した。その
上に炭化物層２となる厚さ２０ｎｍのＡｌＣX と、絶縁
体層３となる１００ｎｍの硬質炭素膜を連続して堆積さ
せた。これを同じパターンにエッチングし、続いてこの
上にＰｔをスパッタリング法により約１４０ｎｍ堆積
し、下部電極１と交差するパターンでエッチングして上
部電極４を形成した。本実施例では硬質炭素３と炭化物
２の膜厚の和が第一導体（下部電極）１と表示用電極５
の膜厚の和より大きくしてあるために、上下電極の短絡
がなく、欠陥率が低いアクティブマトリクス基板を作製
することができた。[Embodiment 6] FIG. 6 is a cross-sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 7. In this embodiment, as shown in FIG. 6, an active matrix is provided on the Pyrex glass substrate 6 as follows. First, ITO to be the display electrode 5 was deposited to a thickness of about 40 nm by a sputtering method and wet-etched to form the display electrode 5. Next, Al was deposited to a thickness of about 40 nm by a sputtering method, and then patterned into the same shape in the element portion to form the lower electrode 1. And AlC X thickness 20nm as a carbide layer 2 thereon, deposited in succession a hard carbon film of 100nm as the insulator layer 3. This was etched in the same pattern, and then Pt was deposited thereon by a sputtering method to have a thickness of about 140 nm, and the upper electrode 4 was formed by etching in a pattern intersecting with the lower electrode 1. In this embodiment, the sum of the film thicknesses of the hard carbon 3 and the carbide 2 is the first conductor (lower electrode) 1 and the display electrode 5.
Since it is made larger than the sum of the film thicknesses of the above, the active matrix substrate having a low defect rate can be produced without short-circuiting the upper and lower electrodes.
【００４１】尚、図８に実施例５，６に対応するアクテ
ィブマトリクス基板の薄膜二端子素子部分の平面構成例
を示すが、図５，６は図８のＢ−Ｂ’線部分に相当する
断面図である。Incidentally, FIG. 8 shows an example of the planar structure of the thin film two-terminal element portion of the active matrix substrate corresponding to the fifth and sixth embodiments. FIGS. 5 and 6 correspond to the BB ′ line portion of FIG. FIG.
【００４２】[0042]
【発明の効果】以上説明したように、本発明によれば、
アクティブマトリクス基板の電極を構成する導体と絶縁
体層の剥離を防止し、素子部の段差による電極の断線と
電極間の短絡を防いだ薄膜二端子素子を作製することが
できる。また使用可能な絶縁体層の成膜条件範囲を広く
し、アクティブマトリクス基板の製造工程のマージンを
増やすことができる。また素子の欠陥を少なくし、歩留
まりを向上させることができる。特性変化がなく、長期
安定性や信頼性の向上したアクティブマトリクス基板を
作製することができる。As described above, according to the present invention,
It is possible to manufacture a thin film two-terminal element in which the conductor constituting the electrode of the active matrix substrate and the insulating layer are prevented from peeling off, and the disconnection of the electrode due to the step of the element portion and the short circuit between the electrodes are prevented. Further, it is possible to widen the film forming condition range of the usable insulator layer and increase the margin of the manufacturing process of the active matrix substrate. In addition, it is possible to reduce defects of the device and improve the yield. It is possible to manufacture an active matrix substrate which has no characteristic change and has improved long-term stability and reliability.
【００４３】ここで絶縁体層に用いる硬質炭素膜は、 １）プラズマＣＶＤ法等の気相合成法で作製されるた
め、成膜条件によって物性が広範囲に制御でき、従って
デバイス設計の自由度が大きい、 ２）硬質でしかも厚膜にできるため、機械的損傷を受け
がたく、また厚膜化によるピンホールの減少も期待でき
る、 ３）室温付近の低温においても良質な膜を形成できるの
で、基板材質に制約がない、 ４）膜厚、膜質の均一性に優れているため、薄膜デバイ
ス用として適している、 ５）誘電率が低いので、高度の微細加工技術を必要とせ
ず、従って素子の大面積化に有利である、等の特徴を有
し、このような絶縁膜を用いたアクティブマトリクス基
板は液晶表示用スイッチング素子として好適である。Since the hard carbon film used for the insulating layer is prepared by 1) a vapor phase synthesis method such as a plasma CVD method, the physical properties can be controlled in a wide range depending on the film forming conditions, and therefore the degree of freedom in device design is high. Large, 2) hard and thick film is less likely to suffer mechanical damage, and pinholes can be expected to be reduced due to thicker film. 3) Good quality film can be formed even at low temperatures near room temperature. There are no restrictions on the substrate material. 4) It is suitable for thin film devices because it has excellent uniformity in film thickness and film quality. 5) It has a low dielectric constant, so it does not require high-level microfabrication technology. The active matrix substrate using such an insulating film is suitable as a switching element for liquid crystal display.
【図１】請求項１，２記載の発明の一実施例を示すアク
ティブマトリクス基板の要部断面図である。FIG. 1 is a cross-sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 2.
【図２】請求項１，３記載の発明の一実施例を示すアク
ティブマトリクス基板の要部断面図である。FIG. 2 is a cross-sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 3.
【図３】請求項１，４記載の発明の一実施例を示すアク
ティブマトリクス基板の要部断面図である。FIG. 3 is a cross-sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 4.
【図４】請求項１，５記載の発明の一実施例を示すアク
ティブマトリクス基板の要部断面図である。FIG. 4 is a cross-sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 5.
【図５】請求項１，６記載の発明の一実施例を示すアク
ティブマトリクス基板の要部断面図である。FIG. 5 is a cross-sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 6.
【図６】請求項１，７記載の発明の一実施例を示すアク
ティブマトリクス基板の要部断面図である。FIG. 6 is a sectional view of an essential part of an active matrix substrate showing an embodiment of the invention described in claims 1 and 7.
【図７】実施例１〜４に対応するアクティブマトリクス
基板の薄膜二端子素子部分の構成例を示す要部平面図で
ある。FIG. 7 is a plan view of essential parts showing a configuration example of a thin film two-terminal element portion of an active matrix substrate corresponding to Examples 1 to 4;
【図８】実施例５，６に対応するアクティブマトリクス
基板の薄膜二端子素子部分の構成例を示す要部平面図で
ある。FIG. 8 is a plan view of essential parts showing a configuration example of a thin film two-terminal element portion of an active matrix substrate corresponding to Examples 5 and 6;
【図９】本発明の絶縁体層に使用した硬質炭素膜をラマ
ン分光法で分析した結果を示すスペクトル図である。FIG. 9 is a spectrum diagram showing the results of Raman spectroscopy analysis of the hard carbon film used for the insulating layer of the present invention.
【図１０】本発明の絶縁体層に使用した硬質炭素膜をＩ
Ｒ吸収法で分析した結果を示すスペクトル図である。FIG. 10 shows the hard carbon film used for the insulating layer of the present invention
It is a spectrum figure which shows the result analyzed by R absorption method.
【図１１】本発明の絶縁体層に使用した硬質炭素膜のＩ
Ｒスペクトルをガウス関数で分解した結果を示す図であ
る。FIG. 11: I of the hard carbon film used for the insulating layer of the present invention
It is a figure which shows the result of having decomposed | disassembled the R spectrum by the Gaussian function.
１：第一導体（下部電極） ２：炭化物層 ３：絶縁体層（硬質炭素膜） ４：第二導体（上部電極） ５：表示用電極 ６：基板 1: First conductor (lower electrode) 2: Carbide layer 3: Insulator layer (hard carbon film) 4: Second conductor (upper electrode) 5: Display electrode 6: Substrate
Claims (7)
極）の間に硬質炭素からなる絶縁体層を有し、前記第一
導体または第二導体を表示用電極に接続してなるアクテ
ィブマトリクス基板において、第一導体と硬質炭素、及
び／または第二導体と硬質炭素の間に導体の構成元素の
炭化物を含む層を有することを特徴とするアクティブマ
トリクス基板。1. An insulating layer made of hard carbon is provided between a first conductor (lower electrode) and a second conductor (upper electrode), and the first conductor or the second conductor is connected to a display electrode. The active matrix substrate according to claim 1, further comprising a layer containing a carbide of a constituent element of the conductor between the first conductor and the hard carbon and / or the second conductor and the hard carbon.
において、第一導体と絶縁体層の間に該導体の炭化物を
含む層を形成してあり、該炭化物層と第一導体が同じ形
状に加工してあるとき、硬質炭素の膜厚が炭化物の膜厚
と第一導体の膜厚の和よりも大きいことを特徴とするア
クティブマトリクス基板。2. The active matrix substrate according to claim 1, wherein a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer and the first conductor are processed into the same shape. The active matrix substrate is characterized in that the thickness of the hard carbon is larger than the sum of the thickness of the carbide and the thickness of the first conductor.
において、第一導体と絶縁体層の間に該導体の炭化物を
含む層を形成してあり、該炭化物層と絶縁体層が同じ形
状に加工してあるとき、硬質炭素の膜厚と炭化物の膜厚
の和が第一導体の膜厚よりも大きいことを特徴とするア
クティブマトリクス基板。3. The active matrix substrate according to claim 1, wherein a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer and the insulator layer are processed into the same shape. The active matrix substrate is characterized in that the sum of the film thickness of hard carbon and the film thickness of carbide is larger than that of the first conductor.
において、第二導体と絶縁体層の間に該導体の炭化物を
含む層を形成してあり、該炭化物層と第二導体が同じ形
状に加工してあるとき、硬質炭素の膜厚が炭化物の膜厚
と第二導体の膜厚の和よりも小さいことを特徴とするア
クティブマトリクス基板。4. The active matrix substrate according to claim 1, wherein a layer containing carbide of the conductor is formed between the second conductor and the insulator layer, and the carbide layer and the second conductor are processed into the same shape. The active matrix substrate is characterized in that the film thickness of the hard carbon is smaller than the sum of the film thickness of the carbide and the film thickness of the second conductor.
において、第二導体と絶縁体層の間に該導体の炭化物を
含む層を形成してあり、該炭化物層と絶縁体層が同じ形
状に加工してあるとき、硬質炭素の膜厚と炭化物の膜厚
の和が第二導体の膜厚よりも小さいことを特徴とするア
クティブマトリクス基板。5. The active matrix substrate according to claim 1, wherein a layer containing a carbide of the conductor is formed between the second conductor and the insulator layer, and the carbide layer and the insulator layer are processed into the same shape. The active matrix substrate is characterized in that the sum of the film thickness of hard carbon and the film thickness of carbide is smaller than the film thickness of the second conductor.
において、第一導体と絶縁体層の間に該導体の炭化物を
含む層を形成してあり、薄膜二端子素子部で炭化物層と
第一導体、表示用電極が同じ形状に加工してあるとき、
硬質炭素の膜厚が炭化物の膜厚と第一導体の膜厚と表示
用電極の膜厚の和よりも大きいことを特徴とするアクテ
ィブマトリクス基板。6. The active matrix substrate according to claim 1, wherein a layer containing a carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer and the first conductor are formed in the thin film two-terminal element portion. , When the display electrodes are processed into the same shape,
An active matrix substrate characterized in that the film thickness of hard carbon is larger than the sum of the film thickness of carbide, the film thickness of a first conductor and the film thickness of a display electrode.
において、第一導体と絶縁体層の間に該導体の炭化物を
含む層を形成してあり、薄膜二端子素子部で炭化物層と
絶縁体層が同じ形状に加工してあるとき、硬質炭素の膜
厚と炭化物の膜厚の和が第一導体の膜厚と表示用電極の
膜厚の和よりも大きいことを特徴とするアクティブマト
リクス基板。7. The active matrix substrate according to claim 1, wherein a layer containing carbide of the conductor is formed between the first conductor and the insulator layer, and the carbide layer and the insulator layer are formed in the thin film two-terminal element portion. When processed into the same shape, the sum of the film thickness of hard carbon and the film thickness of carbide is larger than the sum of the film thickness of the first conductor and the film thickness of the display electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7048893A JPH08248386A (en) | 1995-03-08 | 1995-03-08 | Active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7048893A JPH08248386A (en) | 1995-03-08 | 1995-03-08 | Active matrix substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08248386A true JPH08248386A (en) | 1996-09-27 |
Family
ID=12815958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7048893A Pending JPH08248386A (en) | 1995-03-08 | 1995-03-08 | Active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08248386A (en) |
-
1995
- 1995-03-08 JP JP7048893A patent/JPH08248386A/en active Pending
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