JPH08236478A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH08236478A JPH08236478A JP33931895A JP33931895A JPH08236478A JP H08236478 A JPH08236478 A JP H08236478A JP 33931895 A JP33931895 A JP 33931895A JP 33931895 A JP33931895 A JP 33931895A JP H08236478 A JPH08236478 A JP H08236478A
- Authority
- JP
- Japan
- Prior art keywords
- film
- concentration
- alloy film
- semiconductor device
- atomic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置及びその
製造方法に関し、特に高アスペクト比の微細コンタクト
ホールを有する半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having fine contact holes with a high aspect ratio and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、半導体装置（デバイス）の微細化
に伴い、コンタクトホールのアスペクト比（ホールの深
さｈをホールの幅または径ｄで除した値）が大きくな
り、例えば０．３５μｍの設計ルールによるデバイスの
場合、絶縁膜の厚さが１．５μｍを超すと、アスペクト
比は４対１、すなわち４以上にもなる。このような高ア
スペクト比のコンタクトホールを有する半導体基板上
に、Ｔｉ／ＴｉＮ等からなるバリアメタルを堆積させた
後、更にその上にＡｌ−ＳｉまたはＡｌ−Ｓｉ−Ｃｕ合
金をスパッタリング法により形成しながら、高アスペク
ト比の微細コンタクトホールを埋め込む（充填する）こ
とは不可能になっている。2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, the aspect ratio of a contact hole (the value obtained by dividing the depth h of the hole by the width or diameter d of the hole) has increased. In the case of the device according to the design rule, when the thickness of the insulating film exceeds 1.5 μm, the aspect ratio becomes 4: 1 or 4 or more. After depositing a barrier metal such as Ti / TiN on a semiconductor substrate having such a high aspect ratio contact hole, an Al-Si or Al-Si-Cu alloy is further formed thereon by a sputtering method. However, it is impossible to fill (fill) fine contact holes with a high aspect ratio.
【０００３】そこで、例えば特開平４−１９６４２１号
公報には、Ａｌ−ＳｉまたはＡｌ−Ｓｉ−Ｃｕ合金をス
パッタする前に、下地膜としてＧｅ薄膜をバリアメタル
上に堆積させることにより、高アスペクト比の微細コン
タクトホールを埋め込む方法が提案されている。これ
は、Ｇｅと金属配線中のＡｌとの合金化反応によって形
成されるＡｌ−Ｇｅ合金は、その共晶温度がＡｌ−Ｓｉ
またはＡｌ−Ｓｉ−Ｃｕ合金に比べて低く、溶融し易い
ので、微細なコンタクトホールにも流れ込み易いという
特徴を利用した技術である。Ａｌ−Ｓｉ系合金の場合よ
りも低い温度、すなわち室温より高くＡｌ−Ｇｅ系合金
の共晶温度以下の基板温度でＧｅ薄膜上にＡｌ−Ｓｉ系
合金をスパッタした際の成膜中に、Ａｌ−Ｓｉ系合金は
Ｇｅを取り込みＡｌ−Ｇｅ−Ｓｉ合金をつくる。このＡ
ｌ−Ｇｅ−Ｓｉ系合金は表面マイグレートを起こしてコ
ンタクトホール内に流れ込み易くなる。Therefore, for example, in Japanese Unexamined Patent Publication (Kokai) No. 4-196421, a Ge thin film as a base film is deposited on a barrier metal before sputtering Al-Si or an Al-Si-Cu alloy to obtain a high aspect ratio. The method of burying the fine contact holes has been proposed. This is because the Al-Ge alloy formed by the alloying reaction between Ge and Al in the metal wiring has an eutectic temperature of Al-Si.
Alternatively, it is a technique using a feature that it is lower than an Al-Si-Cu alloy and easily melts, so that it easily flows into a fine contact hole. During the film formation when the Al-Si alloy is sputtered on the Ge thin film at a temperature lower than that of the Al-Si alloy, that is, a substrate temperature higher than room temperature and lower than the eutectic temperature of the Al-Ge alloy, The --Si alloy takes in Ge to form an Al--Ge--Si alloy. This A
The l-Ge-Si-based alloy causes surface migration and easily flows into the contact hole.
【０００４】また、例えば特開平４−１９６４２０号公
報には、コンタクトホール底部と下地バリアメタルとの
間にＧｅ層またはＧｅを高濃度に含有するＳｉ層を挿入
することにより、高アスペクト比のコンタクトホールを
埋め込むことができると同時に、コンタクト抵抗を低減
する方法が提案されている。Further, for example, in Japanese Unexamined Patent Publication No. 4-196420, a Ge layer or a Si layer containing a high concentration of Ge is inserted between the bottom of the contact hole and the underlying barrier metal, whereby a contact with a high aspect ratio is formed. A method has been proposed in which holes can be filled and at the same time, contact resistance is reduced.
【０００５】[0005]
【発明が解決しようとする課題】しかし、これら従来の
デバイスにおいては、配線あるいは電極の抵抗値にバラ
ツキが生じ、デバイス動作の信頼性が著しく低下すると
いう問題がある。However, in these conventional devices, there is a problem that the resistance value of the wiring or the electrode varies, and the reliability of the device operation is significantly lowered.
【０００６】図４には、コンタクトホールをＡｌ−５％
Ｇｅで一度充填した（埋め込んだ）際のコンタクト抵抗
値が示されている。図４から明らかなように、このコン
タクト抵抗値には１０％以上のバラツキが認められる。
なお、バリアメタルにはポリシリコンが用いられてい
る。In FIG. 4, the contact hole is made of Al-5%.
The contact resistance value when once filled (embedded) with Ge is shown. As is clear from FIG. 4, this contact resistance value has a variation of 10% or more.
Polysilicon is used as the barrier metal.
【０００７】この抵抗値のバラツキは、一旦合金化され
て半溶融状態になったＧｅが冷却時にバリアメタル上に
析出してノジュールを形成することが原因とされる。This variation in the resistance value is attributed to the fact that Ge, which has been alloyed and is in a semi-molten state, precipitates on the barrier metal during cooling and forms nodules.
【０００８】合金の融点を低下させるためには、図５に
示されるように、合金のＧｅ含有量を増大させなければ
ならない。その結果、室温ではＧｅの固溶濃度はほとん
ど０であるので、Ｇｅノジュールの大きさは著しく大き
くなる。In order to lower the melting point of the alloy, the Ge content of the alloy must be increased, as shown in FIG. As a result, since the solid solution concentration of Ge is almost 0 at room temperature, the size of Ge nodules becomes significantly large.
【０００９】配線あるいは電極金属中にこのような大き
なＧｅノジュールが存在することは、コンタクトホール
の微細化に伴い、その抵抗値にバラツキを生む主因とな
り、デバイスの電気特性の劣化を招くことになる。The presence of such a large Ge nodule in the wiring or the electrode metal becomes a main cause of variation in the resistance value of the contact hole with the miniaturization of the contact hole, resulting in deterioration of the electrical characteristics of the device. .
【００１０】本発明は従来技術における上記問題点を解
決するために為されたもので、その目的とするところ
は、高アスペクト比の微細ホールを比較的低温状態で埋
め込むことによって、信頼性の高い配線及び電極構造を
形成するようにした半導体装置及びその製造方法を提供
することにある。The present invention has been made in order to solve the above-mentioned problems in the prior art, and its purpose is to fill a fine hole having a high aspect ratio at a relatively low temperature to obtain high reliability. It is an object of the present invention to provide a semiconductor device having a wiring and electrode structure and a manufacturing method thereof.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、本発明の第１基本態様によれば、半導体基板上の絶
縁膜に形成された少なくとも１つのホールと、該ホール
内の少なくとも半導体基板と接する部分に形成されたバ
リアメタルと、該バリアメタル上に成膜された第一のＡ
ｌ含有金属膜及び該第一のＡｌ含有金属膜上に続いて成
膜された前記第一のＡｌ含有金属膜よりも融点の低い第
二のＡｌ含有金属膜の２層からなる金属配線とを具備す
ることを特徴とする半導体装置が提供される。To achieve the above object, according to a first basic aspect of the present invention, at least one hole formed in an insulating film on a semiconductor substrate and at least a semiconductor in the hole. A barrier metal formed in a portion in contact with the substrate, and a first A film formed on the barrier metal.
and a metal wiring comprising two layers of a second Al-containing metal film having a lower melting point than that of the first Al-containing metal film formed on the first Al-containing metal film. There is provided a semiconductor device including the above.
【００１２】上記第１基本態様に記載の半導体装置は以
下の実施態様を有する。すなわち、第一のＡｌ含有金属
膜がＡｌ単独及びＡｌ−Ｓｉ合金膜並びにＡｌ−Ｓｉ−
Ｃｕ合金膜を含むグループから選ばれる１つである。The semiconductor device described in the first basic aspect has the following embodiments. That is, the first Al-containing metal film is Al alone, an Al-Si alloy film, and an Al-Si- film.
It is one selected from the group including a Cu alloy film.
【００１３】前記第二のＡｌ含有金属膜がＡｌ−Ｇｅ−
Ｓｉ合金膜、Ａｌ−Ｇｅ−Ｓｉ−Ｃｕ合金膜、Ａｌ−Ｇ
ｅ合金膜、Ａｌ−Ｇｅ−Ｃｕ合金膜、Ａｌ−Ｓｎ合金
膜、並びにＡｌ−Ｓｎ−Ｃｕ合金膜を含むグループから
選ばれる１つである。The second Al-containing metal film is Al-Ge-
Si alloy film, Al-Ge-Si-Cu alloy film, Al-G
It is one selected from the group including an e-alloy film, an Al-Ge-Cu alloy film, an Al-Sn alloy film, and an Al-Sn-Cu alloy film.
【００１４】前記Ａｌ−Ｓｉ合金膜のＳｉ濃度が０．１
〜２原子％である。The Si concentration of the Al--Si alloy film is 0.1.
~ 2 atomic%.
【００１５】前記Ａｌ−Ｓｉ−Ｃｕ合金膜のＳｉ濃度が
０．１〜２原子％、またＣｕ濃度が０．１〜２原子％で
ある。The Al concentration of the Al-Si-Cu alloy film is 0.1 to 2 atomic%, and the Cu concentration is 0.1 to 2 atomic%.
【００１６】前記Ａｌ−Ｇｅ−Ｓｉ合金膜のＧｅ濃度が
０．５〜３０原子％、またＳｉ濃度が０．１〜２原子％
である。The Al-Ge-Si alloy film has a Ge concentration of 0.5 to 30 atomic% and a Si concentration of 0.1 to 2 atomic%.
Is.
【００１７】前記Ａｌ−Ｇｅ−Ｓｉ−Ｃｕ合金膜のＧｅ
濃度が０．５〜３０原子％、Ｓｉ濃度が０．１〜２原子
％、そしてＣｕ濃度が０．１〜２原子％である。Ge of the Al-Ge-Si-Cu alloy film
The concentration is 0.5 to 30 atom%, the Si concentration is 0.1 to 2 atom%, and the Cu concentration is 0.1 to 2 atom%.
【００１８】前記Ａｌ−Ｇｅ合金膜のＧｅ濃度が０．５
〜３０原子％である。The Ge concentration of the Al-Ge alloy film is 0.5.
Is about 30 atomic%.
【００１９】前記Ａｌ−Ｇｅ−Ｃｕ合金膜のＧｅ濃度が
０．５〜３０原子％、またＣｕ濃度が０．１〜２原子％
である。The Al-Ge-Cu alloy film has a Ge concentration of 0.5 to 30 atomic% and a Cu concentration of 0.1 to 2 atomic%.
Is.
【００２０】前記Ａｌ−Ｓｎ合金膜のＳｎ濃度が０．１
〜９８原子％である。The Sn concentration of the Al--Sn alloy film is 0.1.
Is about 98 atomic%.
【００２１】前記Ａｌ−Ｓｎ−Ｃｕ合金膜のＳｎ濃度及
びＣｕ濃度がそれぞれ０．１〜９８原子％及び０．１〜
２原子％である。The Sn concentration and Cu concentration of the Al-Sn-Cu alloy film are 0.1 to 98 atomic% and 0.1 to 0.1%, respectively.
It is 2 atomic%.
【００２２】また、上記目的を達成するために、本発明
の第２基本態様によれば、半導体基板上の絶縁膜に少な
くとも１つのホールを有する半導体装置の製造方法にお
いて、前記ホール内及び表面に酸化膜を有する半導体基
板上にバリアメタルを形成することと、該バリアメタル
上に第一のＡｌ含有金属膜を形成することと、続いて該
第一のＡｌ含有金属膜上に該第一のＡｌ含有金属膜より
も融点の低い第二のＡｌ含有金属膜を形成することと、
その後前記ホールを充填するために前記第二のＡｌ含有
金属膜の共晶温度以下で該第二のＡｌ含有金属膜を半溶
融状態として前記ホール内にリフローさせることの各ス
テップからなることを特徴とする半導体装置の製造方法
が提供される。In order to achieve the above object, according to a second basic aspect of the present invention, in a method of manufacturing a semiconductor device having at least one hole in an insulating film on a semiconductor substrate, the inside and the surface of the hole are formed. Forming a barrier metal on the semiconductor substrate having an oxide film, forming a first Al-containing metal film on the barrier metal, and subsequently forming the first Al-containing metal film on the first Al-containing metal film; Forming a second Al-containing metal film having a melting point lower than that of the Al-containing metal film;
After that, in order to fill the hole, each step of reflowing the second Al-containing metal film into the hole in a semi-molten state at the eutectic temperature of the second Al-containing metal film or less A method of manufacturing a semiconductor device is provided.
【００２３】上記第２基本態様に記載の半導体装置の製
造方法は以下の実施態様を有する。すなわち、前記第一
のＡｌ含有金属膜がＡｌ単独及びＡｌ−Ｓｉ合金膜並び
にＡｌ−Ｓｉ−Ｃｕ合金膜を含むグループから選ばれる
１つである。The method for manufacturing a semiconductor device described in the second basic aspect has the following embodiments. That is, the first Al-containing metal film is one selected from the group consisting of Al alone, an Al-Si alloy film, and an Al-Si-Cu alloy film.
【００２４】前記第二のＡｌ含有金属膜がＡｌ−Ｇｅ−
Ｓｉ合金膜、Ａｌ−Ｇｅ−Ｓｉ−Ｃｕ合金膜、Ａｌ−Ｇ
ｅ合金膜、Ａｌ−Ｇｅ−Ｃｕ合金膜、Ａｌ−Ｓｎ合金
膜、並びにＡｌ−Ｓｎ−Ｃｕ合金膜を含むグループから
選ばれる１つである。The second Al-containing metal film is Al-Ge-
Si alloy film, Al-Ge-Si-Cu alloy film, Al-G
It is one selected from the group including an e-alloy film, an Al-Ge-Cu alloy film, an Al-Sn alloy film, and an Al-Sn-Cu alloy film.
【００２５】前記Ａｌ−Ｓｉ合金膜のＳｉ濃度が０．１
〜２原子％である。The Si concentration of the Al--Si alloy film is 0.1.
~ 2 atomic%.
【００２６】前記Ａｌ−Ｓｉ−Ｃｕ合金膜のＳｉ濃度が
０．１〜２原子％、またＣｕ濃度が０．１〜２原子％で
ある。The Al concentration of the Al-Si-Cu alloy film is 0.1 to 2 atomic% and the Cu concentration is 0.1 to 2 atomic%.
【００２７】前記Ａｌ−Ｇｅ−Ｓｉ合金膜のＧｅ濃度が
０．５〜３０原子％、またＳｉ濃度が０．１〜２原子％
である。The Al-Ge-Si alloy film has a Ge concentration of 0.5 to 30 atomic% and a Si concentration of 0.1 to 2 atomic%.
Is.
【００２８】前記Ａｌ−Ｇｅ−Ｓｉ−Ｃｕ合金膜のＧｅ
濃度が０．５〜３０原子％、Ｓｉ濃度が０．１〜２原子
％、そしてＣｕ濃度が０．１〜２原子％である。Ge of the Al-Ge-Si-Cu alloy film
The concentration is 0.5 to 30 atom%, the Si concentration is 0.1 to 2 atom%, and the Cu concentration is 0.1 to 2 atom%.
【００２９】前記Ａｌ−Ｇｅ合金膜のＧｅ濃度が０．５
〜３０原子％である。The Ge concentration of the Al-Ge alloy film is 0.5.
Is about 30 atomic%.
【００３０】前記Ａｌ−Ｇｅ−Ｃｕ合金膜のＧｅ濃度が
０．５〜３０原子％、またＣｕ濃度が０．１〜２原子％
である。The Al-Ge-Cu alloy film has a Ge concentration of 0.5 to 30 atomic% and a Cu concentration of 0.1 to 2 atomic%.
Is.
【００３１】前記Ａｌ−Ｓｎ合金膜のＳｎ濃度が０．１
〜９８原子％である。The Sn concentration of the Al--Sn alloy film is 0.1.
Is about 98 atomic%.
【００３２】前記Ａｌ−Ｓｎ−Ｃｕ合金膜のＳｎ濃度及
びＣｕ濃度がそれぞれ０．１〜９８原子％及び０．１〜
２原子％である。The Sn concentration and the Cu concentration of the Al-Sn-Cu alloy film are 0.1 to 98 atomic% and 0.1 to 98 atomic%, respectively.
It is 2 atomic%.
【００３３】[0033]
【作用】上記各態様から明らかなように、本発明者ら
は、スパッタリング中に基板表面で半溶融状態を実現す
ることによってホールを埋め込むという従来法の替わり
に、スパッタリング後に半溶融状態を実現することによ
ってホールを埋め込むというリフロー法（プロシーディ
ングス・オブ・ヴィエルエスアイ・マルチレベル・イン
ターコネクション・コンファレンス (Proceedings of V
LSI Multilevel In-terconnection Conference) 、１９
９１年、第３２６頁等参照）に着目し、これを半導体装
置の製造に採用することに成功したのである。As is apparent from each of the above aspects, the present inventors realize a semi-molten state after sputtering instead of the conventional method of filling holes by realizing the semi-molten state on the substrate surface during sputtering. Reflow method of embedding holes by doing so (Proceedings of VIESA Multi-level Interconnection Conference)
LSI Multilevel In-terconnection Conference), 19
1991, see page 326), and succeeded in adopting this in the manufacture of semiconductor devices.
【００３４】そして、このリフロー法においては、リフ
ロー温度を上げていくと、堆積された金属薄膜の表面か
ら先に溶融し始めることを低速電子線回析を用いた実験
及びシミュレーションを用いた解析から見出した。In this reflow method, it is found that when the reflow temperature is raised, melting starts first from the surface of the deposited metal thin film based on the analysis using the slow electron beam diffraction and the analysis using the simulation. I found it.
【００３５】すなわち、Ｇｅと合金化させることによ
り、金属薄膜の表層の融点だけを下げることができれ
ば、低温状態でホールの埋め込みが可能になると共に、
無視し得る程度にＧｅノジュールを小さくすることがで
きると考えて、本発明が完成された。換言すれば、リフ
ローは堆積された膜の表面だけで生じているため、Ｇｅ
を添加して融点を下げる場所は膜の表面だけで良いこと
になる。その結果、Ｇｅ添加料を低減し、またＧｅをバ
リアメタルに接触させない構成としたことにより、本発
明はリフロー温度を低下させると共に、最終的なＡｌ膜
中のＧｅ濃度の低下をも可能にしている。これにより、
本発明は、例えば０．２５μｍの設計ルールのデバイス
等における電極及び配線工程の信頼性を著しく向上させ
ることができる。That is, if only the melting point of the surface layer of the metal thin film can be lowered by alloying with Ge, holes can be filled in at a low temperature and
The present invention has been completed in the belief that the Ge nodules can be made negligibly small. In other words, the reflow occurs only on the surface of the deposited film, so Ge
The point where the melting point is added to lower the melting point is only on the surface of the film. As a result, since the Ge additive is reduced and the Ge is not brought into contact with the barrier metal, the present invention lowers the reflow temperature and also makes it possible to lower the Ge concentration in the final Al film. There is. This allows
The present invention can remarkably improve the reliability of the electrode and wiring process in a device or the like having a design rule of 0.25 μm, for example.
【００３６】[0036]
【発明の実施の形態】以下、本発明の実施の形態を添付
の図面を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.
【００３７】図１の（ａ）〜（ｂ）及び図２の（ｃ）〜
（ｄ）は、それぞれ本発明の半導体装置に関する製造工
程の一実施の形態を工程順に示す断面図である。1A to 1B and 2C to 2C.
6D is a cross-sectional view showing one embodiment of the manufacturing process of the semiconductor device of the present invention in the order of processes. FIG.
【００３８】トランジスタ等の素子の一部となるｐ+ 拡
散層１を表面に形成したＳｉ基板２上に酸化絶縁膜３を
ＣＶＤ法等で形成し、酸化絶縁膜３をエッチングして直
径０．２５μｍ、アスペクト比４のコンタクトホール４
を形成する。（図１（ａ）参照） 次に、Ｔｉ薄膜５を室温で２０ｎｍの厚さにスパッタ成
膜した後、引き続いてＴｉＮ薄膜６を基板温度２００℃
の状態で１００ｎｍの厚さにスパッタ成膜する。その
後、窒素雰囲気中でランプアニールを６２０℃で３０秒
間行った。（図１（ｂ）参照） なお、Ｔｉ／ＴｉＮ積
層膜５，６はバリアメタルとして作用するものである。An oxide insulating film 3 is formed by a CVD method or the like on a Si substrate 2 having a p + diffusion layer 1 which becomes a part of an element such as a transistor formed on its surface, and the oxide insulating film 3 is etched to have a diameter of 0. Contact hole 4 with 25 μm and aspect ratio 4
To form. (See FIG. 1A) Next, after the Ti thin film 5 is formed by sputtering to a thickness of 20 nm at room temperature, the TiN thin film 6 is subsequently formed at a substrate temperature of 200 ° C.
In this state, a sputter film is formed to a thickness of 100 nm. Then, lamp annealing was performed at 620 ° C. for 30 seconds in a nitrogen atmosphere. (See FIG. 1B) The Ti / TiN laminated films 5 and 6 act as barrier metals.
【００３９】さらに、第一のＡｌ含有金属膜７として、
Ｓｉを１原子％含有するＡＬ−Ｓｉ合金膜、またはＳｉ
を１原子％、Ｃｕを０．５原子％それぞれ含有するＡｌ
−Ｓｉ−Ｃｕ合金膜を、基板１を２０〜１００℃に加熱
した状態でバリアメタル５，６上に０．８μｍの厚さに
スパッタ成膜した。（図２（ｃ）参照） 続いて、第一のＡｌ含有金属膜７の上に該第一のＡｌ含
有金属膜７よりも融点の低い第二のＡｌ含有金属膜８と
して、Ｇｅを２０原子％、Ｓｉを１原子％含有するＡｌ
−Ｇｅ−Ｓｉ合金膜、またはＧｅを２０原子％、Ｓｉを
１原子％、Ｃｕを０．５原子％含有するＡｌ−Ｇｅ−Ｓ
ｉ−Ｃｕ合金膜を、基板１を２０〜１００℃に加熱した
状態で０．０１μｍの厚さにスパッタ成膜し、その後、
３００℃でリフローさせた。（図２（ｄ）参照） その結果、コンタクトホール４は完全に充填され（埋め
込まれ）、その際、配線及び電極の抵抗値のバラツキ
は、図３から明らかなように、１０％以内に納まり、信
頼性に関する問題は解決されていることが判った。Further, as the first Al-containing metal film 7,
AL-Si alloy film containing 1 atomic% of Si, or Si
Al containing 1 atomic% of Cu and 0.5 atomic% of Cu
An —Si—Cu alloy film was sputter-deposited on the barrier metals 5 and 6 to a thickness of 0.8 μm while the substrate 1 was heated to 20 to 100 ° C. (See FIG. 2C) Subsequently, Ge is used as 20 atoms on the first Al-containing metal film 7 as a second Al-containing metal film 8 having a melting point lower than that of the first Al-containing metal film 7. %, Al containing 1 atomic% of Si
-Ge-Si alloy film or Al-Ge-S containing 20 atomic% Ge, 1 atomic% Si, and 0.5 atomic% Cu
The i-Cu alloy film is sputter-deposited to a thickness of 0.01 μm while the substrate 1 is heated to 20 to 100 ° C., and thereafter,
Reflowed at 300 ° C. (See FIG. 2D) As a result, the contact hole 4 is completely filled (embedded), and at that time, the variation in the resistance value of the wiring and the electrode is within 10% as is apparent from FIG. , It turns out that the reliability issue has been resolved.
【００４０】ここで、上記第一のＡｌ含有金属膜７とし
て、Ａｌ単独で成膜したＡｌ膜を用いても、全く変わら
ない効果が得られた。Here, even if an Al film formed of Al alone was used as the first Al-containing metal film 7, the same effect was obtained.
【００４１】また、上記第二のＡｌ含有金属膜８とし
て、Ｓｉを含まないＡｌ−Ｇｅ合金膜、Ａｌ−Ｇｅ−Ｃ
ｕ膜、Ａｌ−Ｓｎ膜、あるいはＡｌ−Ｓｎ−Ｃｕ膜を用
いても同様な効果を得ることが判った。Further, as the second Al-containing metal film 8, an Al-Ge alloy film containing no Si, Al-Ge-C is used.
It was found that the same effect can be obtained by using a u film, an Al-Sn film, or an Al-Sn-Cu film.
【００４２】さらに、第一のＡｌ含有金属膜７における
Ｓｉ濃度及びＣｕ濃度はそれぞれ０．１〜２原子％の範
囲であれば本発明の目的が達成されることが判った。Further, it has been found that the object of the present invention can be achieved if the Si concentration and the Cu concentration in the first Al-containing metal film 7 are in the range of 0.1 to 2 atomic%, respectively.
【００４３】なおまた、第二のＡｌ含有金属膜８におけ
るＧｅ濃度は０．５％〜３０原子％の範囲、Ｓｉ濃度ま
たはＳｎ濃度及びＣｕ濃度は、Ｓｉが０．１〜２原子％
の範囲、Ｓｎが０．１〜９８原子％、そしてＣｕが０．
１〜２原子％であれば、本発明の目的が達成され得るこ
とが判った。The Ge concentration in the second Al-containing metal film 8 is in the range of 0.5% to 30 atomic%, and the Si concentration or the Sn concentration and the Cu concentration are 0.1 to 2 atomic% in Si.
, Sn is 0.1 to 98 atomic%, and Cu is 0.
It has been found that the object of the present invention can be achieved with 1 to 2 atomic%.
【００４４】[0044]
【発明の効果】以上説明したように、本発明によれば、
高アスペクト比の微細コンタクトホールを完全に充填す
ることが可能になり、その際に、電気的特性の劣化を全
く起こすことなく、半導体装置のデバイス特性及び信頼
性の向上を実現させることができる。As described above, according to the present invention,
It becomes possible to completely fill a fine contact hole having a high aspect ratio, and at that time, improvement in device characteristics and reliability of the semiconductor device can be realized without causing deterioration of electrical characteristics.
【００４５】また、本発明によれば、従来のスパッタ法
にて微細コンタクトホールを充填することができるた
め、従来の製造プロセスをそのまま利用することが可能
となり、製造コストを低減させ得るという効果が得られ
る。Further, according to the present invention, since the fine contact holes can be filled by the conventional sputtering method, the conventional manufacturing process can be used as it is, and the manufacturing cost can be reduced. can get.
【００４６】さらに、第二のＡｌ含有金属膜のリフロー
のために、従来、基板としてのウェハを４５０℃以上に
加熱しなければならないところを、本発明ではその温度
よりもはるかに低い温度、例えば、３００℃の基板加熱
温度でリフローを達成することができるので、半導体装
置のデバイス特性及び信頼性が著しく向上するという効
果を併せ持つ。Further, in order to reflow the second Al-containing metal film, conventionally, a wafer as a substrate has to be heated to 450 ° C. or higher, but in the present invention, a temperature much lower than that, for example, Since reflow can be achieved at a substrate heating temperature of 300 ° C., it also has the effect of significantly improving the device characteristics and reliability of the semiconductor device.
【００４７】以上の説明は単に本発明の好適な実施例の
例証であり、本発明の範囲はこれに限定されることはな
い。本発明に関するさらに多くの変形例や改造例が本発
明の範囲を逸脱することなく当該技術の熟達者にとって
みれば容易に思い当たるであろう。The above description is merely illustrative of the preferred embodiments of the present invention and the scope of the present invention is not limited thereto. Many variations and modifications of the present invention will readily suggest themselves to those skilled in the art without departing from the scope of the invention.
【図１】図１の（ａ）〜（ｂ）はそれぞれ本発明の半導
体装置及びその製造方法の１つの実施の形態を製造工程
順に示す断面図である。1A to 1B are cross-sectional views showing, in the order of manufacturing steps, one embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.
【図２】図２の（ｃ）〜（ｄ）はそれぞれ本発明の半導
体装置及びその製造方法の１つの実施の形態を製造工程
順に示す断面図である。2 (c) to 2 (d) are cross-sectional views showing a semiconductor device and a method of manufacturing the same according to one embodiment of the present invention in the order of manufacturing steps.
【図３】図３は本発明の半導体装置のコンタクト抵抗値
に関するバラツキ状態を示すグラフである。FIG. 3 is a graph showing variations in contact resistance value of the semiconductor device of the present invention.
【図４】図４は従来例におけるコンタクト抵抗値のバラ
ツキ状態を示すグラフである。FIG. 4 is a graph showing a variation state of a contact resistance value in a conventional example.
【図５】図５はＡｌ−Ｇｅ系合金における融点のＧｅ濃
度依存度を示すグラフである。FIG. 5 is a graph showing the Ge concentration dependence of the melting point in an Al—Ge based alloy.
１ ｐ+ 拡散層 ２ Ｓｉ基板 ３ 酸化絶縁膜 ４ コンタクトホール ５，６ Ｔｉ／ＴｉＮ積層膜（バリアメタル） ７ 第一のＡｌ含有金属膜 ８ 第二のＡｌ含有金属膜1 p + Diffusion Layer 2 Si Substrate 3 Oxide Insulation Film 4 Contact Holes 5, 6 Ti / TiN Laminated Film (Barrier Metal) 7 First Al-Containing Metal Film 8 Second Al-Containing Metal Film
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/90 Ｃ Ｄ Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display area H01L 21/90 CD
Claims (22)
くとも１つのホールと、該ホール内の少なくとも半導体
基板と接する部分に形成されたバリアメタルと、該バリ
アメタル上に成膜された第一のＡｌ含有金属膜及び該第
一のＡｌ含有金属膜上に続いて成膜された前記第一のＡ
ｌ含有金属膜よりも融点の低い第二のＡｌ含有金属膜の
２層からなる金属配線とを具備することを特徴とする半
導体装置。1. At least one hole formed in an insulating film on a semiconductor substrate, a barrier metal formed in at least a portion of the hole in contact with the semiconductor substrate, and a first film formed on the barrier metal. Al-containing metal film and the first A film successively formed on the first Al-containing metal film
2. A semiconductor device, comprising: a metal wiring comprising two layers of a second Al-containing metal film having a melting point lower than that of the l-containing metal film.
びＡｌ−Ｓｉ合金膜並びにＡｌ−Ｓｉ−Ｃｕ合金膜を含
むグループから選ばれる１つであることを特徴とする請
求項１記載の半導体装置。2. The first Al-containing metal film is one selected from the group consisting of Al alone, an Al-Si alloy film, and an Al-Si-Cu alloy film. Semiconductor device.
−Ｓｉ合金膜、Ａｌ−Ｇｅ−Ｓｉ−Ｃｕ合金膜、Ａｌ−
Ｇｅ合金膜、Ａｌ−Ｇｅ−Ｃｕ合金膜、Ａｌ−Ｓｎ合金
膜、並びにＡｌ−Ｓｎ−Ｃｕ合金膜を含むグループから
選ばれる１つであることを特徴とする請求項１記載の半
導体装置。3. The second Al-containing metal film is Al-Ge
-Si alloy film, Al-Ge-Si-Cu alloy film, Al-
The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group including a Ge alloy film, an Al-Ge-Cu alloy film, an Al-Sn alloy film, and an Al-Sn-Cu alloy film.
１〜２原子％であることを特徴とする請求項２記載の半
導体装置。4. The Si concentration of the Al--Si alloy film is 0.
The semiconductor device according to claim 2, wherein the content is 1 to 2 atomic%.
が０．１〜２原子％、またＣｕ濃度が０．１〜２原子％
であることを特徴とする請求項２記載の半導体装置。5. The Si concentration of the Al—Si—Cu alloy film is 0.1 to 2 atomic%, and the Cu concentration is 0.1 to 2 atomic%.
The semiconductor device according to claim 2, wherein
が０．５〜３０原子％、またＳｉ濃度が０．１〜２原子
％であることを特徴とする請求項３記載の半導体装置。6. The semiconductor device according to claim 3, wherein the Ge concentration of the Al—Ge—Si alloy film is 0.5 to 30 atom%, and the Si concentration is 0.1 to 2 atom%. .
ｅ濃度が０．５〜３０原子％、Ｓｉ濃度が０．１〜２原
子％、そしてＣｕ濃度が０．１〜２原子％であることを
特徴とする請求項３記載の半導体装置。7. The G of the Al-Ge-Si-Cu alloy film
4. The semiconductor device according to claim 3, wherein the e concentration is 0.5 to 30 atom%, the Si concentration is 0.1 to 2 atom%, and the Cu concentration is 0.1 to 2 atom%.
５〜３０原子％であることを特徴とする請求項３記載の
半導体装置。8. The Ge concentration of the Al--Ge alloy film is 0.
The semiconductor device according to claim 3, wherein the content is 5 to 30 atomic%.
が０．５〜３０原子％、またＣｕ濃度が０．１〜２原子
％であることを特徴とする請求項３記載の半導体装置。9. The semiconductor device according to claim 3, wherein the Al—Ge—Cu alloy film has a Ge concentration of 0.5 to 30 atom% and a Cu concentration of 0.1 to 2 atom%. .
０．１〜９８原子％であることを特徴とする請求項３記
載の半導体装置。10. The semiconductor device according to claim 3, wherein the Sn concentration of the Al—Sn alloy film is 0.1 to 98 atomic%.
度及びＣｕ濃度がそれぞれ０．１〜９８原子％及び０．
１〜２原子％であることを特徴とする請求項３記載の半
導体装置。11. The Sn concentration and Cu concentration of the Al—Sn—Cu alloy film are 0.1 to 98 atomic% and 0.
The semiconductor device according to claim 3, wherein the content is 1 to 2 atomic%.
つのホールを有する半導体装置の製造方法において、前
記ホール内及び表面に酸化膜を有する半導体基板上にバ
リアメタルを形成することと、該バリアメタル上に第一
のＡｌ含有金属膜を形成することと、続いて該第一のＡ
ｌ含有金属膜上に該第一のＡｌ含有金属膜よりも融点の
低い第二のＡｌ含有金属膜を形成することと、その後前
記ホールを充填するために前記第二のＡｌ含有金属膜の
共晶温度以下で該第二のＡｌ含有金属膜を半溶融状態と
して前記ホール内にリフローさせることの各ステップか
らなることを特徴とする半導体装置の製造方法。12. At least one insulating film on a semiconductor substrate.
In a method of manufacturing a semiconductor device having two holes, forming a barrier metal on a semiconductor substrate having an oxide film inside and on the surface, and forming a first Al-containing metal film on the barrier metal. , Then the first A
forming a second Al-containing metal film having a melting point lower than that of the first Al-containing metal film on the 1-containing metal film, and then forming the second Al-containing metal film to fill the holes. A method of manufacturing a semiconductor device, comprising the steps of reflowing the second Al-containing metal film in a semi-molten state into the hole at a crystallization temperature or lower.
及びＡｌ−Ｓｉ合金膜並びにＡｌ−Ｓｉ−Ｃｕ合金膜を
含むグループから選ばれる１つであることを特徴とする
請求項１２記載の半導体装置の製造方法。13. The first Al-containing metal film is one selected from the group consisting of Al alone, an Al—Si alloy film, and an Al—Si—Cu alloy film. Manufacturing method of semiconductor device.
ｅ−Ｓｉ合金膜、Ａｌ−Ｇｅ−Ｓｉ−Ｃｕ合金膜、Ａｌ
−Ｇｅ合金膜、Ａｌ−Ｇｅ−Ｃｕ合金膜、Ａｌ−Ｓｎ合
金膜、並びにＡｌ−Ｓｎ−Ｃｕ合金膜を含むグループか
ら選ばれる１つであることを特徴とする請求項１２記載
の半導体装置の製造方法。14. The second Al-containing metal film is Al-G.
e-Si alloy film, Al-Ge-Si-Cu alloy film, Al
13. The semiconductor device according to claim 12, wherein the semiconductor device is one selected from the group including a --Ge alloy film, an Al--Ge--Cu alloy film, an Al--Sn alloy film, and an Al--Sn--Cu alloy film. Production method.
０．１〜２原子％であることを特徴とする請求項１３記
載の半導体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 13, wherein the Si concentration of the Al—Si alloy film is 0.1 to 2 atomic%.
度が０．１〜２原子％、またＣｕ濃度が０．１〜２原子
％であることを特徴とする請求項１３記載の半導体装置
の製造方法。16. The semiconductor device according to claim 13, wherein the Al concentration of the Al—Si—Cu alloy film is 0.1 to 2 atomic%, and the Cu concentration is 0.1 to 2 atomic%. Manufacturing method.
度が０．５〜３０原子％、またＳｉ濃度が０．１〜２原
子％であることを特徴とする請求項１４記載の半導体装
置の製造方法。17. The semiconductor device according to claim 14, wherein a Ge concentration of the Al—Ge—Si alloy film is 0.5 to 30 atom%, and a Si concentration is 0.1 to 2 atom%. Manufacturing method.
Ｇｅ濃度が０．５〜３０原子％、Ｓｉ濃度が０．１〜２
原子％、そしてＣｕ濃度が０．１〜２原子％であること
を特徴とする請求項１４記載の半導体装置の製造方法。18. The Ge concentration of the Al-Ge-Si-Cu alloy film is 0.5 to 30 atomic%, and the Si concentration is 0.1 to 2.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the atomic percent and the Cu concentration are 0.1 to 2 atomic percent.
０．５〜３０原子％であることを特徴とする請求項１４
記載の半導体装置の製造方法。19. The Ge concentration of the Al—Ge alloy film is 0.5 to 30 atomic%.
The manufacturing method of the semiconductor device described in the above.
度が０．５〜３０原子％、またＣｕ濃度が０．１〜２原
子％であることを特徴とする請求項１４記載の半導体装
置の製造方法。20. The semiconductor device according to claim 14, wherein the Al—Ge—Cu alloy film has a Ge concentration of 0.5 to 30 atom% and a Cu concentration of 0.1 to 2 atom%. Manufacturing method.
０．１〜９８原子％であることを特徴とする請求項１４
記載の半導体装置。21. The Sn concentration of the Al—Sn alloy film is 0.1 to 98 atomic%.
13. The semiconductor device according to claim 1.
度及びＣｕ濃度がそれぞれ０．１〜９８原子％及び０．
１〜２原子％であることを特徴とする請求項１４記載の
半導体装置。22. The Sn concentration and Cu concentration of the Al-Sn-Cu alloy film are 0.1 to 98 atomic% and 0.
15. The semiconductor device according to claim 14, wherein the content is 1 to 2 atomic%.
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| JP6-338719 | 1994-12-28 | ||
| JP33871994 | 1994-12-28 | ||
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100265993B1 (en) * | 1997-04-02 | 2000-10-02 | 김영환 | Method of forming metal line of semicondcutor device |
| KR100399066B1 (en) * | 2000-12-28 | 2003-09-26 | 주식회사 하이닉스반도체 | Method for aluminium-alloy in semiconductor device |
| US6673704B2 (en) | 1996-12-24 | 2004-01-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| KR100421281B1 (en) * | 1996-10-02 | 2004-05-10 | 주식회사 하이닉스반도체 | Method for fabricating metal interconnection of semiconductor device |
| KR100480582B1 (en) * | 1998-03-10 | 2005-05-16 | 삼성전자주식회사 | Fabricating method of barrier film of semiconductor device and fabricating method of metal wiring using the same |
-
1995
- 1995-12-26 JP JP33931895A patent/JP2730623B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100421281B1 (en) * | 1996-10-02 | 2004-05-10 | 주식회사 하이닉스반도체 | Method for fabricating metal interconnection of semiconductor device |
| US6673704B2 (en) | 1996-12-24 | 2004-01-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6946387B2 (en) | 1996-12-24 | 2005-09-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| KR100265993B1 (en) * | 1997-04-02 | 2000-10-02 | 김영환 | Method of forming metal line of semicondcutor device |
| KR100480582B1 (en) * | 1998-03-10 | 2005-05-16 | 삼성전자주식회사 | Fabricating method of barrier film of semiconductor device and fabricating method of metal wiring using the same |
| KR100399066B1 (en) * | 2000-12-28 | 2003-09-26 | 주식회사 하이닉스반도체 | Method for aluminium-alloy in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2730623B2 (en) | 1998-03-25 |
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