JPH08204133A - High-frequency integrated circuit - Google Patents
High-frequency integrated circuitInfo
- Publication number
- JPH08204133A JPH08204133A JP1124395A JP1124395A JPH08204133A JP H08204133 A JPH08204133 A JP H08204133A JP 1124395 A JP1124395 A JP 1124395A JP 1124395 A JP1124395 A JP 1124395A JP H08204133 A JPH08204133 A JP H08204133A
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- Prior art keywords
- layer
- semiconductor substrate
- line
- matching circuit
- loss
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高周波領域における半
導体集積回路、特に、トランジスタやダイオード等のよ
うな半導体素子と同一基板上にインピーダンス整合回路
としてマイクロストリップ線路やコプレナ線路の様な分
布定数線路を設けたＭＭＩＣ（モノリシックマイクロ波
ＩＣ）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in a high frequency region, and particularly to a distributed constant line such as a microstrip line or a coplanar line as an impedance matching circuit on the same substrate as a semiconductor element such as a transistor or a diode. The present invention relates to an MMIC (monolithic microwave IC) provided with.
【０００２】[0002]
【従来の技術】高周波領域においてマイクロストリップ
線路やコプレナ線路の様な分布定数線路から成るインピ
ーダンス整合回路をシリコン基板の様な導電性の半導体
基板上に設ける場合、一般的にはまず半導体基板上にＳ
ｉＯ2 等により誘電体層を形成し、その上に金属の導体
層により線路を形成する例が電子通信学会論文誌 '７０
／１０ Ｖol.５３−Ｂ Ｎo.１０ で報告されている。
以下、高周波領域の半導体素子として一般的に使用され
ているＳｉ−MOSFETを例に、従来技術について説明す
る。2. Description of the Related Art When an impedance matching circuit composed of a distributed constant line such as a microstrip line or a coplanar line in a high frequency region is provided on a conductive semiconductor substrate such as a silicon substrate, the semiconductor substrate is generally first placed on the semiconductor substrate. S
An example of forming a dielectric layer with iO 2 or the like and then forming a line with a metal conductor layer on the dielectric layer is published in IEICE Transactions '70.
/ 10 Vol.53-B No.10.
Hereinafter, the conventional technique will be described by taking a Si-MOSFET generally used as a semiconductor element in a high frequency region as an example.
【０００３】図１にＳｉ−MOSFETの構造を、図２にその
ＡーＡ′断面を示す。図において１はゲート電極、２は
ソース電極、３はドレイン電極である。４は層間絶縁膜
であり、一般にはＳｉＯ2 やＰＳＧが良く使われる。５
は素子を形成する為の高抵抗層で一般には１Ω・cm以
上、６はソース抵抗を低減するための低抵抗層で一般に
は０．１Ω・cm以下が使われる。また、７は基板の裏面
に設けられた金属層によるアース導体である。ソース電
極２の下にはソースをアースに落した場合の抵抗を減ら
すため低抵抗層の孔が設けられている。FIG. 1 shows the structure of a Si-MOSFET, and FIG. 2 shows its AA 'cross section. In the figure, 1 is a gate electrode, 2 is a source electrode, and 3 is a drain electrode. Reference numeral 4 is an interlayer insulating film, and generally SiO 2 or PSG is often used. 5
Is a high resistance layer for forming an element, generally 1 Ω · cm or more, and 6 is a low resistance layer for reducing the source resistance, generally 0.1 Ω · cm or less. Further, 7 is an earth conductor formed of a metal layer provided on the back surface of the substrate. Below the source electrode 2, a hole of a low resistance layer is provided in order to reduce the resistance when the source is grounded.
【０００４】図３はＳｉ−MOSFETのゲート電極とドレイ
ン電極にマイクロストリップ線路を接続した場合の断面
を示す。層間絶縁膜を誘電体層とし、ゲート電極とドレ
イン電極の金属層をそのまま線路の導体として使用して
いる。FIG. 3 shows a cross section when a microstrip line is connected to the gate electrode and the drain electrode of the Si-MOSFET. The interlayer insulating film is used as a dielectric layer, and the metal layers of the gate electrode and the drain electrode are used as they are as conductors of the line.
【０００５】[0005]
【発明が解決しようとする課題】図３に示したような従
来構造のＭＭＩＣにおいて、マイクロストリップ線路は
１，３が線路導体として、４の絶縁膜が誘電体層とし
て、５の導電性半導体基板であるシリコン基板が下部導
体（アース導体）として働く。シリコン基板の電気抵抗
は一般に高抵抗層では数Ω・cm程度、低抵抗層でも０.
０２Ω・cm 程度有る。この為、下部導体を形成するシ
リコン基板の電気抵抗が金属層で形成された導体、例え
ば銅の１.７×１０-6Ω・cm 等に比較して非常に大きな
ものとなり、線路の損失が大幅に増加する。この結果、
本構造の線路を用いた増幅器等では利得や出力電力を大
幅に低下させる事になる。In the MMIC having the conventional structure as shown in FIG. 3, microstrip lines 1 and 3 are line conductors, 4 insulating films are dielectric layers, and 5 is a conductive semiconductor substrate. The silicon substrate that works as a lower conductor (earth conductor). The electric resistance of a silicon substrate is generally about several Ω · cm in the high resistance layer, and is even in the low resistance layer.
There is about 02 Ω · cm. For this reason, the electrical resistance of the silicon substrate forming the lower conductor is much higher than that of a conductor formed of a metal layer, such as 1.7 × 10 −6 Ω · cm of copper, and the line loss is low. Increase significantly. As a result,
In an amplifier using the line of this structure, the gain and output power will be significantly reduced.
【０００６】本発明の目的は、シリコン等の導電性の半
導体基板を用いて、半導体素子とその整合回路を同一基
板上に構成するＭＭＩＣにおいてマイクロストリップ線
路等の分布定数線路の損失を低減することにより、増幅
器や発振器等の性能向上を図ることにある。An object of the present invention is to reduce the loss of a distributed constant line such as a microstrip line in an MMIC in which a semiconductor element and its matching circuit are formed on the same substrate by using a conductive semiconductor substrate such as silicon. To improve the performance of amplifiers and oscillators.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目標を達
成するため、マイクロストリップ線路等の分布定数線路
で構成した整合回路部については、半導体基板の上（基
板と誘電体層の間）に金属層を一層設け、この金属層を
下部導体として用いると共に前記金属層下の半導体基板
の高抵抗層を除き低抵抗層と直接接触するような構成と
した。In order to achieve the above-mentioned object, the present invention provides a matching circuit section constituted by a distributed constant line such as a microstrip line on a semiconductor substrate (between the substrate and the dielectric layer). A metal layer is provided on the substrate, and this metal layer is used as a lower conductor and is in direct contact with the low resistance layer except for the high resistance layer of the semiconductor substrate under the metal layer.
【０００８】[0008]
【作用】マイクロストリップ線路の損失は、一般に次式
で表わされる(ＩＥＥＥ Ｖol.ＭＴＴ−１６，Ｎo.６
ＪＵＮＥ １９６８）。The loss of the microstrip line is generally expressed by the following equation (IEEE Vol. MTT-16, No. 6).
JUNE 1968).
【０００９】[0009]
【数１】 [Equation 1]
【００１０】減衰定数αは、線路を構成する誘電体の誘
電体損(tanδ）で発生する損失で決まる減衰定数αｄと
線路導体とアース導体の電気抵抗成分で発生する損失で
決まる減衰定数αｃの和となる。マイクロストリップ線
路を構成するＳｉＯ2 等の誘電体の損失は一般に非常に
小さく、線路導体の導体損によるものが大半を占めてい
る場合が多い。導体損で決まる減衰定数αｃは次式の様
に線路導体とアース導体の電気抵抗に比例する。The damping constant α is a damping constant αd determined by a loss generated by a dielectric loss (tan δ) of a dielectric material forming a line and a damping constant αc determined by a loss generated by an electric resistance component of a line conductor and a ground conductor. It becomes the sum. The loss of the dielectric material such as SiO 2 that constitutes the microstrip line is generally very small, and the loss due to the conductor loss of the line conductor occupies the majority in many cases. The attenuation constant αc determined by the conductor loss is proportional to the electric resistance of the line conductor and the ground conductor as shown in the following equation.
【００１１】[0011]
【数２】 αｃ∝ｋ１・√ρ1／２Ｚｏ＋ｋ２・√ρ2／２Ｚｏ …（数２） ここで ρ1：線路導体の比抵抗 ρ2：アース導体の比抵抗 Ｚｏ：線路の特性インピーダンス ｋ１，ｋ２：周波数等で決まる定数 即ち、シリコン等の導電性の半導体基板がマイクロスト
リップ線路のアース導体となる場合にはρ2が大きくな
り線路損失が増大する。本発明では、このアース導体と
して金属層を一層設けρ2を極めて小さなものとし、線
路損失を大幅に低減する。[Formula 2] αc∝k1√ρ 1 / 2Zo + k2√ρ 2 / 2Zo (Equation 2) where ρ 1 : specific resistance of line conductor ρ 2 : specific resistance of ground conductor Zo: characteristic impedance k1 of line k2: constant determined by frequency or the like, that is, when a conductive semiconductor substrate such as silicon serves as the ground conductor of the microstrip line, ρ 2 increases and line loss increases. In the present invention, a single metal layer is provided as the ground conductor to make ρ 2 extremely small, and line loss is greatly reduced.
【００１２】[0012]
【実施例】以下、本発明の実施例について詳細に説明す
る。図４は、本発明による実施例の一つであり、素子と
してＳｉ−MOSFETを、整合回路としてマイクロストリッ
プ線路を用いた場合の構成を示す。図において１−１は
ゲート電極に接続されている伝送線路で、１−２はその
線路に並列に入るインピーダンス整合用のスタブであ
る。２はソース電極であり、下のアースに接続されてい
る。３−１はドレイン電極に接続されている伝送線路
で、３−２はその線路に並列に入るインピーダンス整合
用のスタブである。８は伝送線路の下に設けた誘電体層
とその下のシリコン基板との間に設けた金属層を示して
いる。図において点線で囲まれたＦＥＴ近傍は金属層８
が取り除かれている。EXAMPLES Examples of the present invention will be described in detail below. FIG. 4 is one of the embodiments according to the present invention, and shows a configuration in the case of using a Si-MOSFET as an element and a microstrip line as a matching circuit. In the figure, 1-1 is a transmission line connected to the gate electrode, and 1-2 is an impedance matching stub that is connected in parallel to the line. Reference numeral 2 is a source electrode, which is connected to the lower ground. 3-1 is a transmission line connected to the drain electrode, and 3-2 is an impedance matching stub that is connected in parallel to the line. Reference numeral 8 denotes a metal layer provided between the dielectric layer provided under the transmission line and the silicon substrate thereunder. In the vicinity of the FET surrounded by the dotted line in the figure, the metal layer 8 is formed.
Have been removed.
【００１３】図５は、本発明による実施例の一つであ
り、整合回路としてグランドコプレナ線路を用いた場合
の構成を示す。図において、２−１はＦＥＴのソース電
極と接続されたアース導体であり下の誘電体層を貫通し
た孔等によりシリコン基板との間に設けた金属層に接続
されている。その他の構成は、図４と同じである。FIG. 5 is one of the embodiments according to the present invention, and shows the configuration when a ground coplanar line is used as a matching circuit. In the figure, reference numeral 2-1 is a ground conductor connected to the source electrode of the FET, and is connected to a metal layer provided between the source electrode and the silicon substrate by a hole penetrating the lower dielectric layer. Other configurations are the same as those in FIG.
【００１４】図６は、図４のＡ−Ａ′断面を示す。図に
おいて４はマイクロストリップ線路を構成するための層
間絶縁膜を兼ねた誘電体層である。５−１はＦＥＴを形
成する部分にのみ設けたシリコン基板の高抵抗層であ
り、６はシリコン基板の低抵抗層である。７は、チップ
をパッケージやヒートシンクに取り付けるために基板の
裏面に設けられた金属層でありアース導体となってい
る。８はシリコン基板と誘電体層との間に設けられた金
属の導体層であり、基板の低抵抗層６を介してアース導
体７に接続されている。FIG. 6 shows a cross section taken along the line AA 'of FIG. In the figure, 4 is a dielectric layer which also serves as an interlayer insulating film for forming a microstrip line. Reference numeral 5-1 is a high resistance layer of the silicon substrate provided only in a portion forming the FET, and 6 is a low resistance layer of the silicon substrate. A metal layer 7 is a metal layer provided on the back surface of the substrate for attaching the chip to a package or a heat sink and serves as a ground conductor. Reference numeral 8 is a metal conductor layer provided between the silicon substrate and the dielectric layer, and is connected to the ground conductor 7 through the low resistance layer 6 of the substrate.
【００１５】図７は、図６と同じく図４のＡ−Ａ′断面
を示すがシリコン基板の高抵抗層をＦＥＴの近傍に限ら
ず全面に設けた場合であり、線路の下部導体となる金属
層の数個所に高抵抗層を貫通する低抵抗層の孔６−１を
設けた構成を示す。Similar to FIG. 6, FIG. 7 shows a cross section taken along the line AA ′ in FIG. 4, but in the case where the high resistance layer of the silicon substrate is provided not only in the vicinity of the FET but on the entire surface, a metal serving as a lower conductor of the line is formed. A structure in which holes 6-1 of a low resistance layer penetrating the high resistance layer are provided in several places of the layer is shown.
【００１６】図８は、半導体素子を用いた高周波増幅回
路の一例を等価回路で示したものであり、１１は高周波
信号の入力端子、１２は高周波信号の出力端子、１３は
ドレインバイアス端子、１４はゲートバイアス端子、１
５はMOSFET、１６−１，２，３は出力側のインピーダン
ス整合回路を構成するマイクロストリップ線路、１７は
入力側インピーダンス整合回路を構成するスパイラルイ
ンダクタ、１８−１，２，３，４，５，６はコンデンサ
類、１９はゲートバイアス印加用の抵抗である。FIG. 8 shows an example of a high-frequency amplifier circuit using a semiconductor element by an equivalent circuit. 11 is a high-frequency signal input terminal, 12 is a high-frequency signal output terminal, 13 is a drain bias terminal, and 14 is a high-frequency signal output terminal. Is the gate bias terminal, 1
5 is a MOSFET, 16-1, 2, 3 are microstrip lines forming an output side impedance matching circuit, 17 is a spiral inductor forming an input side impedance matching circuit, 18-1, 2, 3, 4, 5, Reference numeral 6 is a capacitor, and 19 is a resistor for applying a gate bias.
【００１７】図９は、本発明を適用し、図８の等価回路
の増幅器を実現した場合の構成の一例を示す図であり、
ＦＥＴ１５の下とスパイラルインダクタ１７の下の金属
層による下部導体が除去されている。スパイラルインダ
クタの下の下部導体が取り除かれているのは、スパイラ
ルインダクタの直下に金属層が有る場合、ミラー効果に
より誘電体層が十分厚くないとインダクタンス値が大幅
に低下するためである。FIG. 9 is a diagram showing an example of the configuration when the amplifier of the equivalent circuit of FIG. 8 is realized by applying the present invention,
The lower conductor formed by the metal layer under the FET 15 and under the spiral inductor 17 is removed. The lower conductor under the spiral inductor is removed because if there is a metal layer directly under the spiral inductor, the inductance value is significantly reduced unless the dielectric layer is sufficiently thick due to the mirror effect.
【００１８】図１０はＦＥＴとスパイラルインダクタの
下を除いた回路部の下の部分にのみ金属層による下部導
体８を設けた場合である。この場合マイクロストリップ
線路の部分の下部導体幅は少なくとも上部導体幅の２倍
以上は必要である。FIG. 10 shows the case where the lower conductor 8 made of a metal layer is provided only in the lower portion of the circuit portion except under the FET and the spiral inductor. In this case, the lower conductor width of the microstrip line portion must be at least twice the upper conductor width.
【００１９】図１１は増幅回路の整合回路を入力側は集
中定数型回路で、出力側は分布定数型回路で構成し、出
力側のみ金属層による下部導体８を設けた場合である。FIG. 11 shows a case where the matching circuit of the amplifier circuit is composed of a lumped constant type circuit on the input side and a distributed constant type circuit on the output side, and the lower conductor 8 made of a metal layer is provided only on the output side.
【００２０】[0020]
【発明の効果】本発明によれば、シリコン等の導電性の
半導体基板を用いて、半導体素子とその整合回路を同一
基板上に構成するＭＭＩＣにおいて、整合回路を構成す
るマイクロストリップ線路等の分布定数線路の損失を大
幅に低減することが出来、もって高周波領域での増幅器
や発振器等の性能向上を図ることが出来る。更に言え
ば、高出力の増幅器では入力側より出力側の損失を低減
することが高出力，高効率化の観点から重要である。こ
のため、入力側には多少損失が増えても小型化に有利な
集中定数型の整合回路を用い、出力側には、多少面積が
増えても低損失化に有利な分布定数型の整合回路を用い
ることが良いと考えられる。この場合、実施例でも示し
たように、出力側のみ本発明を適用しても十分性能向上
を図ることが可能となる。According to the present invention, in a MMIC in which a semiconductor element and its matching circuit are formed on the same substrate by using a conductive semiconductor substrate such as silicon, the distribution of microstrip lines etc. forming the matching circuit is distributed. It is possible to significantly reduce the loss of the constant line, and thus improve the performance of the amplifier, oscillator, etc. in the high frequency region. Furthermore, in a high output amplifier, it is important to reduce the loss on the output side rather than the input side from the viewpoint of high output and high efficiency. Therefore, a lumped-constant type matching circuit that is advantageous for downsizing is used on the input side even if the loss increases slightly, and a distributed constant type matching circuit that is advantageous for low loss even if the area increases slightly on the output side. It is considered good to use. In this case, as shown in the embodiment, it is possible to sufficiently improve the performance even if the present invention is applied only to the output side.
【図１】従来の高周波用半導体素子（Ｓｉ−MOSFET）の
構造を示す上面図。FIG. 1 is a top view showing the structure of a conventional high-frequency semiconductor element (Si-MOSFET).
【図２】従来の高周波用半導体素子（Ｓｉ−MOSFET）の
構造を示す断面図。FIG. 2 is a cross-sectional view showing the structure of a conventional high-frequency semiconductor element (Si-MOSFET).
【図３】従来の導電性半導体基板（Ｓｉ）を用いたＭＭ
ＩＣの構造を示す断面図。FIG. 3 MM using a conventional conductive semiconductor substrate (Si)
Sectional drawing which shows the structure of IC.
【図４】本発明によるＭＭＩＣの実施例の構造を示す上
面図。FIG. 4 is a top view showing a structure of an example of an MMIC according to the present invention.
【図５】本発明によるＭＭＩＣの他の実施例の構造を示
す上面図。FIG. 5 is a top view showing the structure of another embodiment of the MMIC according to the present invention.
【図６】本発明によるＭＭＩＣの実施例の構造を示す断
面図。FIG. 6 is a sectional view showing the structure of an MMIC according to an embodiment of the present invention.
【図７】本発明によるＭＭＩＣの他の実施例の構造を示
す断面図。FIG. 7 is a sectional view showing the structure of another embodiment of the MMIC according to the present invention.
【図８】半導体素子を用いた高周波増幅回路の一例を等
価回路図。FIG. 8 is an equivalent circuit diagram showing an example of a high frequency amplifier circuit using a semiconductor element.
【図９】本発明によるＭＭＩＣ増幅器の実施例の構造を
示す上面図。FIG. 9 is a top view showing the structure of an embodiment of an MMIC amplifier according to the present invention.
【図１０】本発明によるＭＭＩＣ増幅器の他の実施例の
構造を示す上面図。FIG. 10 is a top view showing the structure of another embodiment of the MMIC amplifier according to the present invention.
【図１１】本発明によるＭＭＩＣ増幅器の他の実施例の
構造を示す上面図。FIG. 11 is a top view showing the structure of another embodiment of the MMIC amplifier according to the present invention.
１−１…ゲート側ストリップ線路、１−２…ゲート側ス
タブ、２…ソース電極、３−１…ドレイン側ストリップ
線路、３−２…ドレイン側スタブ、８…下部導体となる
金属層。1-1 ... Gate-side strip line, 1-2 ... Gate-side stub, 2 ... Source electrode, 3-1 ... Drain-side strip line, 3-2 ... Drain-side stub, 8 ... Metal layer serving as lower conductor.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉田 功 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isao Yoshida 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.
Claims (5)
導体素子を形成するため半導体基板の表面に高抵抗層を
設け、その他は接地導体との電気抵抗を減らすための低
抵抗層からなる半導体基板と、前記半導体基板と同一の
基板上に絶縁層を設けその上に金属層の線路により前記
半導体素子のインピーダンス整合回路を形成した集積回
路において、前記半導体素子を形成するため前記半導体
基板の表面に設ける高抵抗層を半導体素子の近傍のみと
し、半導体素子以外の整合回路を構成する部分は前記半
導体基板上に設けた前記絶縁層と前記半導体基板の間に
金属層を設けたことを特徴とする高周波集積回路。1. A semiconductor substrate comprising a high resistance layer on the surface of a semiconductor substrate for forming a semiconductor element such as an FET or a bipolar transistor, and a low resistance layer for reducing the electric resistance with a ground conductor. In an integrated circuit in which an insulating layer is provided on the same substrate as the semiconductor substrate and an impedance matching circuit for the semiconductor element is formed by a line of a metal layer on the insulating layer, the height provided on the surface of the semiconductor substrate for forming the semiconductor element is high. A high frequency integrated circuit characterized in that a resistance layer is provided only in the vicinity of a semiconductor element, and a portion other than a semiconductor element that constitutes a matching circuit is provided with a metal layer between the insulating layer provided on the semiconductor substrate and the semiconductor substrate. circuit.
導体素子を形成するため、半導体基板の表面に高抵抗層
を設け、その他は接地導体との電気抵抗を減らすための
低抵抗層からなる半導体基板と、前記半導体基板と同一
の基板上に絶縁層を設けその上に金属層の線路により前
記半導体素子のインピーダンス整合回路を形成した集積
回路において、前記半導体素子以外の整合回路を構成す
る部分は前記半導体基板上に設けた前記絶縁層と前記半
導体基板の間に金属層を設け、前記金属層の下の少なく
とも１ヶ所に前記半導体基板の前記高抵抗層を貫通し下
の低抵抗層と接続する低抵抗層で出来た孔を設けたこと
を特徴とする高周波集積回路。2. A semiconductor substrate comprising a high resistance layer on the surface of a semiconductor substrate for forming a semiconductor element such as an FET or a bipolar transistor, and a low resistance layer for reducing the electric resistance with a ground conductor. In an integrated circuit in which an insulating layer is provided on the same substrate as the semiconductor substrate and an impedance matching circuit of the semiconductor element is formed on the insulating layer by a line of a metal layer, a portion constituting the matching circuit other than the semiconductor element is the semiconductor. A metal layer is provided between the insulating layer provided on the substrate and the semiconductor substrate, and a low resistance layer that penetrates the high resistance layer of the semiconductor substrate at least at one place under the metal layer and connects the low resistance layer therebelow. A high-frequency integrated circuit having a hole made of a resistance layer.
ンピーダンス整合回路を構成するスパイラルインダクタ
ンスの下の前記絶縁層と前記半導体基板の間に設けた前
記金属層を取り除いた高周波集積回路。3. The high frequency integrated circuit according to claim 1, wherein the metal layer provided between the insulating layer and the semiconductor substrate below the spiral inductance forming the impedance matching circuit is removed.
波集積回路を用いた増幅器において、入力側の前記イン
ピーダンス整合回路部の下は前記絶縁層と前記半導体基
板の間に設けた前記金属層を取り除き、出力側の前記イ
ンピーダンス整合回路部の下は前記絶縁層と前記半導体
基板の間に金属層を設けた高周波集積回路。4. The amplifier using the high frequency integrated circuit according to claim 1, wherein the metal provided between the insulating layer and the semiconductor substrate is below the impedance matching circuit section on the input side. A high-frequency integrated circuit in which a layer is removed and a metal layer is provided between the insulating layer and the semiconductor substrate under the output side impedance matching circuit section.
高周波集積回路を用いた無線装置。5. A wireless device using the high frequency integrated circuit according to claim 1. Description:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1124395A JPH08204133A (en) | 1995-01-27 | 1995-01-27 | High-frequency integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1124395A JPH08204133A (en) | 1995-01-27 | 1995-01-27 | High-frequency integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08204133A true JPH08204133A (en) | 1996-08-09 |
Family
ID=11772504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1124395A Pending JPH08204133A (en) | 1995-01-27 | 1995-01-27 | High-frequency integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08204133A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998012751A1 (en) * | 1996-09-20 | 1998-03-26 | Hitachi, Ltd. | High-frequency integrated circuit device and its manufacture |
| EP0940848A2 (en) * | 1998-03-05 | 1999-09-08 | Interuniversitair Micro-Elektronica Centrum Vzw | A low-loss conductive pattern and a method for fabrication thereof |
-
1995
- 1995-01-27 JP JP1124395A patent/JPH08204133A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998012751A1 (en) * | 1996-09-20 | 1998-03-26 | Hitachi, Ltd. | High-frequency integrated circuit device and its manufacture |
| EP0940848A2 (en) * | 1998-03-05 | 1999-09-08 | Interuniversitair Micro-Elektronica Centrum Vzw | A low-loss conductive pattern and a method for fabrication thereof |
| EP0940848A3 (en) * | 1998-03-05 | 2000-03-22 | Interuniversitair Micro-Elektronica Centrum Vzw | A low-loss conductive pattern and a method for fabrication thereof |
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