JPH0927594A - High-frequency monolithic integrated circuit - Google Patents
High-frequency monolithic integrated circuitInfo
- Publication number
- JPH0927594A JPH0927594A JP7177087A JP17708795A JPH0927594A JP H0927594 A JPH0927594 A JP H0927594A JP 7177087 A JP7177087 A JP 7177087A JP 17708795 A JP17708795 A JP 17708795A JP H0927594 A JPH0927594 A JP H0927594A
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- Prior art keywords
- circuit
- silicon substrate
- substrate
- integrated circuit
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高周波領域における半
導体集積回路、更に詳しく言えば、高出力増幅回路、低
雑音増幅回路、ミクサ、変復調回路等の異なった機能を
有する回路を１チップ内に構成する集積回路の回路形
態、および、トランジスタやダイオード等のような半導
体素子と同一基板上にインピーダンス整合回路としてマ
イクロストリップ線路やコプレナ線路の様な分布定数線
路やスパイラルインダクタを設けたＭＭＩＣ（モノリシ
ックマイクロ波ＩＣ）の回路形態に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in a high frequency region, more specifically, a high output amplifier circuit, a low noise amplifier circuit, a mixer, a circuit having different functions such as a modulator / demodulator circuit in one chip. The circuit form of the integrated circuit to be constructed and the MMIC (monolithic micro-circuit) in which a distributed constant line such as a microstrip line or a coplanar line or a spiral inductor is provided as an impedance matching circuit on the same substrate as a semiconductor element such as a transistor or a diode. Circuit IC).
【０００２】[0002]
【従来の技術】従来、シリコン基板を用いて高出力増幅
回路、低雑音増幅回路、ミクサ、変復調回路等の異なっ
た機能を有する回路を１チップ内に構成する集積回路は
殆ど使われていない。これは、個々の回路に要求される
性能が異なっているため、それに用いる基板や素子構造
が各々の回路特有のものとなるためである。例えば、ミ
クサや変復調回路等のＩＣでは比較的電気抵抗の高い
（１０Ω・ｃｍ程度）基板を用いその表面に素子や回路
を形成するが、高出力増幅回路用の素子では基板の裏面
をアース導体とし、ＦＥＴの場合にはソース接地、バイ
ポーラの場合はエミッタ接地とするために比較的電気抵
抗の低い（０．０２Ω・ｃｍ程度）基板を用る。また、
高周波領域においてマイクロストリップ線路やコプレナ
線路の様な分布定数線路から成るインピーダンス整合回
路をシリコン基板の様な導電性の半導体基板上に設ける
場合、一般的にはまず半導体基板上にＳｉＯ2等により
誘電体層を形成し、その上に金属の導体層により線路を
形成する例が学会（電子通信学会論文誌 ’７０／１０
Ｖｏｌ．５３−Ｂ Ｎｏ．１０）で報告されている。
以下、高周波領域の半導体素子として一般的に使用され
ているＳｉ−ＭＯＳＦＥＴを例に取り、高出力増幅回路
のインピーダンス整合回路の構成法の従来技術について
説明する。第４図にＳｉ−ＭＯＳＦＥＴの構造を、第５
図にそのＡ−Ａ’断面を示す。図において１−１はゲ−
ト電極、１−２はソース電極、１−３はドレイン電極で
ある。１−４は層間絶縁膜であり、一般にはＳｉＯ2や
ＰＳＧが良く使われる。１−５は素子を形成する為の高
抵抗層で低抵抗基板の上にイオン打ち込み等で作られ、
一般には厚さ数μｍ、電気抵抗１Ω・ｃｍ以上である。
１−６はソース抵抗を低減するための低抵抗層で一般に
は厚さ１００μｍ以上で０．１Ω・ｃｍ以下が使われ
る。また、１−７は基板の裏面に設けられた金属層によ
るアース導体である。ソース電極１−２の下にはソース
をアースに落した場合の抵抗を減らすため低抵抗層の孔
が設けられている。第６図は前記Ｓｉ−ＭＯＳＦＥＴの
ゲート電極とドレイン電極にマイクロストリップ線路を
接続した場合の断面構造を示す。層間絶縁膜を誘電体層
とし、ゲート電極とドレイン電極の金属層をそのまま線
路の導体として使用している。2. Description of the Related Art Conventionally, an integrated circuit in which a circuit having different functions such as a high-power amplifier circuit, a low-noise amplifier circuit, a mixer, and a modulator / demodulator circuit using a silicon substrate is constructed in one chip is rarely used. This is because the performance required for each circuit is different, and the substrate and element structure used for each circuit are unique to each circuit. For example, in an IC such as a mixer or a modulation / demodulation circuit, a substrate having a relatively high electric resistance (about 10 Ω · cm) is used to form an element or a circuit on its surface. However, in an element for a high-power amplifier circuit, the back surface of the substrate is a ground conductor. In the case of FET, the source is grounded, and in the case of bipolar, the grounded emitter is used. Therefore, a substrate having a relatively low electric resistance (about 0.02 Ω · cm) is used. Also,
When an impedance matching circuit composed of a distributed constant line such as a microstrip line or a coplanar line in a high frequency region is provided on a conductive semiconductor substrate such as a silicon substrate, generally, first, a dielectric such as SiO 2 is formed on the semiconductor substrate. An example in which a body layer is formed and a line is formed on the conductor layer by a metal is a society
Vol. 53-B No. 10).
Hereinafter, a conventional technique of a method of configuring an impedance matching circuit of a high output amplifier circuit will be described by taking a Si-MOSFET generally used as a semiconductor element in a high frequency region as an example. The structure of the Si-MOSFET is shown in FIG.
The figure shows the AA 'cross section. In the figure, 1-1 is a game
Electrode 1-2, source electrode 1-2, drain electrode 1-3. Reference numeral 1-4 is an interlayer insulating film, and generally SiO 2 or PSG is often used. 1-5 is a high resistance layer for forming an element, which is formed by ion implantation or the like on a low resistance substrate,
Generally, the thickness is several μm and the electric resistance is 1 Ω · cm or more.
Reference numeral 1-6 is a low resistance layer for reducing the source resistance, and a thickness of 100 μm or more and 0.1 Ω · cm or less is generally used. Further, 1-7 is a ground conductor formed of a metal layer provided on the back surface of the substrate. Below the source electrode 1-2, a hole of a low resistance layer is provided to reduce the resistance when the source is grounded. FIG. 6 shows a sectional structure when a microstrip line is connected to the gate electrode and the drain electrode of the Si-MOSFET. The interlayer insulating film is used as a dielectric layer, and the metal layers of the gate electrode and the drain electrode are used as they are as conductors of the line.
【０００３】[0003]
【発明が解決しようとする課題】第６図に示したような
従来構造のＭＭＩＣにおいて、マイクロストリップ線路
は１−１、１−３が線路導体として、１−４の絶縁膜が
誘電体層として働くが、１−５の導電性半導体基板であ
るシリコン基板は誘電体層と下部導体（アース導体）の
中間的な働きをするものと思われるが何れにしてもマイ
クロストリップ線路の損失を大幅に増加させる。この損
失を増加させないためには１−４の絶縁膜を厚くすれば
良いが、この膜は一般にはＳｉＯ2やＰＳＧが良く使わ
れ厚さは１０μｍ以下が一般的であり、これを厚くする
ことは極めて難しい。また、絶縁幕が薄いとマイクロス
トリップ線路の特性インピーダンスが極めて低いものと
成り回路設計が難しくなる。また、スパイラルインダク
タンスを形成した場合にもシリコン基板が損失を大幅に
増加させてしまう。このため、シリコン基板の電気抵抗
を高め、この層を損失の少ない誘電体層として用いる事
が出来れば損失の少ない整合回路が実現できる。また、
ミクサや変復調回路は高出力増幅回路や低雑音増幅回路
ほど回路損失を低減する必要が無いので一般に使われる
高抵抗なシリコン基板の表面に回路を形成すれば良い。In the MMIC having the conventional structure as shown in FIG. 6, the microstrip lines 1-1 and 1-3 are line conductors and the insulating film 1-4 is a dielectric layer. Although it works, the silicon substrate, which is a conductive semiconductor substrate of 1-5, seems to act as an intermediate between the dielectric layer and the lower conductor (earth conductor), but in any case, the loss of the microstrip line is greatly increased. increase. In order to prevent this loss from increasing, the insulating film 1-4 may be thickened. Generally, SiO 2 or PSG is often used for this film and the thickness is generally 10 μm or less. Is extremely difficult. Further, if the insulating curtain is thin, the characteristic impedance of the microstrip line becomes extremely low, which makes circuit design difficult. In addition, even if a spiral inductance is formed, the silicon substrate will greatly increase the loss. Therefore, if the electrical resistance of the silicon substrate is increased and this layer can be used as a dielectric layer with low loss, a matching circuit with low loss can be realized. Also,
Since the mixer and the modulation / demodulation circuit do not need to reduce the circuit loss as much as the high output amplification circuit and the low noise amplification circuit, the circuit may be formed on the surface of a commonly used high resistance silicon substrate.
【０００４】本発明の目的は、高出力増幅回路、低雑音
増幅回路、ミクサ、変復調回路等の異なった機能を有す
る回路を１チップ内に構成する際、各々の回路に適した
電気抵抗率を有するシリコン基板を用い、個々の特性を
劣化させること無く１チップ集積回路を実現することで
ある。An object of the present invention is to construct a circuit having different functions such as a high-power amplifier circuit, a low-noise amplifier circuit, a mixer, and a modulator / demodulator circuit in one chip so that the electrical resistivity suitable for each circuit can be obtained. It is to realize a one-chip integrated circuit by using the silicon substrate that it has without deteriorating individual characteristics.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目標を達
成するため、電気抵抗率の異なった複数のシリコン基板
を張り合わせた多層構造のシリコン基板を用い、基板の
高い電気抵抗率を有する方のシリコン基板上にミクサや
変復調回路及び高出力増幅回路、低雑音増幅回路の整合
回路部を形成すると共に高い電気抵抗率を有する方のシ
リコン基板の一部を取り除いた低い電気抵抗率を有する
方のシリコン基板の部分に高出力増幅素子、低雑音増幅
素子となるバイポーラトランジスタやＦＥＴ等のアクテ
ィブ素子を形成するような構成とした。In order to achieve the above-mentioned object, the present invention uses a silicon substrate having a multi-layered structure in which a plurality of silicon substrates having different electrical resistivities are bonded to each other and has a high electrical resistivity. Forming a matching circuit part of a mixer, a modulator / demodulator circuit, a high-power amplifier circuit, and a low-noise amplifier circuit on a silicon substrate of, and having a low electrical resistivity by removing a part of the silicon substrate of a higher electrical resistivity. The active elements such as bipolar transistors and FETs, which are high-power amplifying elements and low-noise amplifying elements, are formed on the silicon substrate.
【０００６】[0006]
【作用】高出力増幅回路の出力側整合回路の損失は増幅
器の効率を低減し、低雑音増幅回路の入力側整合回路の
損失は、増幅器の雑音指数を劣化させる。このため、前
記整合回路の損失を極力減らす必要がある。The loss of the output side matching circuit of the high power amplifier circuit reduces the efficiency of the amplifier, and the loss of the input side matching circuit of the low noise amplifier circuit deteriorates the noise figure of the amplifier. Therefore, it is necessary to reduce the loss of the matching circuit as much as possible.
【０００７】マイクロストリップ線路の損失は、一般に
次式(数１)で表わされる。 （ＩＥＥＥ Ｖｏｌ．ＭＴ
Ｔ−１６，ＮＯ．６ ＪＵＮＥ １９６８）The loss of the microstrip line is generally expressed by the following equation (Equation 1). (IEEE Vol. MT
T-16, NO. 6 JUNE 1968)
【０００８】[0008]
【数１】 [Equation 1]
【０００９】(数１)において、Ｐｏは線路の出力端電力
を、Ｐｉは線路の入力端電力を、αは減衰定数を、ｌは
線路長を表している。In (Equation 1), Po is the output power of the line, Pi is the input power of the line, α is the damping constant, and l is the line length.
【００１０】減衰定数αは、線路を構成する誘電体の誘
電体損（ｔａｎδ）で発生する損失で決まる減衰定数α
ｄと線路導体とアース導体の電気抵抗成分で発生する損
失で決まる減衰定数αｃの和となる。The attenuation constant α is determined by the loss generated by the dielectric loss (tan δ) of the dielectric material forming the line.
It is the sum of d and the damping constant αc determined by the loss generated by the electric resistance components of the line conductor and the ground conductor.
【００１１】このため、マイクロストリップ線路の損失
を低減するためには、誘電体の誘電体損を小さくすると
共に幅の広い線路導体を用い導体損を小さくする事が重
要である。マイクロストリップ線路の特性インピーダン
スは、線路導体幅が広いほど、誘電体層が薄いほど低い
値となる。例えば、誘電体層がＳｉＯ2で厚さが５μｍ
の場合、５０Ωの線路幅は約９μｍとなり、このままで
は線路幅が細くて導体損失が大きくなる。また、導体損
を減らすべく線路幅を増やすと特性インピーダンスが下
がり（線路幅を５０μｍにすると約１０Ω）回路設計が
難しくなる。このため、誘電体層の厚さを増し特性イン
ピーダンスを下げること無く線路導体の幅を増すことが
有効な手段と成って来る。また、スパイラルインダクタ
の損失を減らすにも誘電体基板の厚さを増すこと及び基
板の電気抵抗率を高くする事が有効である。このため、
電気抵抗率の異なったシリコン基板を張り合わせた構造
のシリコン基板を用い、高い電気抵抗率を有する方のシ
リコン基板上にミクサや変復調回路及び高出力増幅回
路、低雑音増幅回路の整合回路部を形成し、高出力増幅
素子や低雑音増幅素子のようにその素子構造の面から低
い電気抵抗率を有する基板を用いた方が有利なものは、
高い電気抵抗率を有する方のシリコン基板の一部を取り
除いた低い電気抵抗率を有する方のシリコン基板の部分
に形成するような構成とすれば個々の特性を劣化させる
こと無く１チップ集積回路が実現可能と成る。Therefore, in order to reduce the loss of the microstrip line, it is important to reduce the dielectric loss of the dielectric and use a wide line conductor to reduce the conductor loss. The characteristic impedance of the microstrip line becomes lower as the line conductor width becomes wider and the dielectric layer becomes thinner. For example, the dielectric layer is SiO 2 and the thickness is 5 μm
In the case of, the line width of 50Ω becomes about 9 μm, and if this is left as it is, the line width becomes thin and the conductor loss becomes large. Further, if the line width is increased to reduce the conductor loss, the characteristic impedance decreases (about 50Ω when the line width is 50 μm), which makes circuit design difficult. Therefore, increasing the width of the line conductor without increasing the thickness of the dielectric layer and lowering the characteristic impedance has become an effective means. Further, in order to reduce the loss of the spiral inductor, it is effective to increase the thickness of the dielectric substrate and increase the electric resistivity of the substrate. For this reason,
Using a silicon substrate with a structure in which silicon substrates with different electrical resistivities are bonded together, the mixer, modulator / demodulator circuit, high-power amplifier circuit, and low-noise amplifier circuit matching circuit section are formed on the silicon substrate with the higher electrical resistivity. However, it is advantageous to use a substrate having a low electrical resistivity in terms of its element structure, such as a high-power amplifier element or a low-noise amplifier element,
A single-chip integrated circuit can be formed without deteriorating individual characteristics by adopting a structure in which a silicon substrate having a high electric resistivity is partially removed to form a silicon substrate having a low electric resistivity. It becomes feasible.
【００１２】[0012]
【実施例】以下、本発明の実施例について詳細に説明す
る。第１図は、本発明による実施例の一つであり、高抵
抗基板の一部をエッチング等で取り除き低抵抗基板を露
出させその部分に素子を形成した場合の断面構造を示
す。図において１は半導体素子、２−１、２−２はマイ
クロストリップ線路であり前者は出力整合回路を、後者
は入力整合回路を形成する。３は高抵抗基板、５は低抵
抗基板、４は高抵抗基板と低抵抗基板を張り合わせるた
めの中間層となるＳｉＯ2膜、６はアース導体である。
第２図は第１図の上面図であり、素子としてＳｉ−ＭＯ
ＳＦＥＴを、整合回路としてマイクロストリップ線路を
用いた場合の構成を示す。図において１−１はゲート電
極で入力側の整合回路を構成するマイクロストリップ線
路２−２に接続されている。１−２はソ−ス電極であ
り、低抵抗基板５を通して下のアース導体６に接続され
ている。１−３はドレイン電極で出力側の整合回路を構
成するマイクロストリップ線路２−１に接続されてい
る。図において点線で囲まれたＦＥＴ近傍は高抵抗基板
３が取り除かれている。また、低抵抗基板部と高抵抗基
板の上面とは斜めにエッチングされており配線を容易に
している。EXAMPLES Examples of the present invention will be described in detail below. FIG. 1 is one of the embodiments according to the present invention, and shows a cross-sectional structure when a part of a high resistance substrate is removed by etching or the like to expose a low resistance substrate and an element is formed in that part. In the figure, 1 is a semiconductor element, 2-1, 2-2 are microstrip lines, the former forming an output matching circuit and the latter forming an input matching circuit. Reference numeral 3 is a high resistance substrate, 5 is a low resistance substrate, 4 is a SiO 2 film serving as an intermediate layer for bonding the high resistance substrate and the low resistance substrate, and 6 is a ground conductor.
FIG. 2 is a top view of FIG. 1 and shows Si-MO as an element.
The configuration when the SFET is a microstrip line as a matching circuit is shown. In the figure, reference numeral 1-1 is a gate electrode, which is connected to a microstrip line 2-2 that constitutes a matching circuit on the input side. Reference numeral 1-2 is a source electrode, which is connected to the ground conductor 6 below through the low resistance substrate 5. A drain electrode 1-3 is connected to the microstrip line 2-1 that constitutes an output side matching circuit. In the vicinity of the FET surrounded by the dotted line in the figure, the high resistance substrate 3 is removed. Further, the low resistance substrate portion and the upper surface of the high resistance substrate are obliquely etched to facilitate wiring.
【００１３】第６図は、本発明による実施例の一つであ
り、携帯電話等に代表される送受信端末に適用した場合
の構成をブロック図で示したものである。図において太
い点線で囲まれた範囲１１は各種の回路を搭載したＩＣ
チップ、細い点線の範囲１２は送信用の高出力増幅回
路、１３は送受アンテナ共用器、１４はアンテナ、細い
点線の範囲１５は受信用の低雑音増幅回路、１６は受信
ミクサ、１７は送信ミクサ、１８は周波数シンセサイ
ザ、１９は復調回路、２０は変調回路、２１はベースバ
ンド部である。図において各種の回路及び高出力増幅回
路、低雑音増幅回路の入出力整合回路１２−１、１２−
３、１５−１、１５−３は高抵抗基板の上に形成し、高
出力増幅回路１２に使われる高出力素子１２−２及び低
雑音増幅回路１５に使われる低雑音素子１５−２は高抵
抗基板３が取り除かれた部分に形成されている。FIG. 6 is one of the embodiments according to the present invention, and is a block diagram showing the configuration when applied to a transmission / reception terminal typified by a mobile phone. In the figure, an area 11 surrounded by a thick dotted line is an IC equipped with various circuits.
Chip, thin dotted range 12 is a high-power amplifier circuit for transmission, 13 is a transmitting / receiving antenna duplexer, 14 is an antenna, thin dotted range 15 is a low noise amplifying circuit for reception, 16 is a receiving mixer, 17 is a transmitting mixer , 18 is a frequency synthesizer, 19 is a demodulation circuit, 20 is a modulation circuit, and 21 is a baseband unit. In the figure, various circuits, input / output matching circuits 12-1 and 12- of high-power amplifier circuits and low-noise amplifier circuits are shown.
3, 15-1 and 15-3 are formed on a high resistance substrate, and the high output element 12-2 used in the high output amplifier circuit 12 and the low noise element 15-2 used in the low noise amplifier circuit 15 are high in resistance. The resistor substrate 3 is formed in the removed portion.
【００１４】[0014]
【発明の効果】本発明によれば、高出力増幅回路、低雑
音増幅回路、ミクサ、変復調回路等の異なった機能を有
する回路を１チップ内に構成する高周波モノリシック集
積回路において、各々の回路に必要な特性を劣化させる
こと無く１チップ内に集積化が可能と成り、もって携帯
電話等の無線端末の小型化や高性能化を図ることが可能
と成る。According to the present invention, in a high-frequency monolithic integrated circuit in which circuits having different functions such as a high-power amplifier circuit, a low-noise amplifier circuit, a mixer, and a modulator / demodulator circuit are formed in one chip, It is possible to integrate them in one chip without deteriorating the required characteristics, and it is possible to reduce the size and improve the performance of wireless terminals such as mobile phones.
【図１】本発明による高周波モノリシック集積回路の実
施例の構造を示す断面図。FIG. 1 is a sectional view showing the structure of an embodiment of a high frequency monolithic integrated circuit according to the present invention.
【図２】本発明による高周波モノリシック集積回路の実
施例の構造を示す上面図。FIG. 2 is a top view showing the structure of an embodiment of a high frequency monolithic integrated circuit according to the present invention.
【図３】本発明による高周波モノリシック集積回路の実
施例を示す機能ブロック図。FIG. 3 is a functional block diagram showing an embodiment of a high frequency monolithic integrated circuit according to the present invention.
【図４】従来の高周波用半導体素子（Ｓｉ−ＭＯＳＦＥ
Ｔ）の構造を示す上面図。FIG. 4 is a conventional high frequency semiconductor device (Si-MOSFE).
The top view which shows the structure of T).
【図５】従来の高周波用半導体素子（Ｓｉ−ＭＯＳＦＥ
Ｔ）の構造を示す断面図。FIG. 5 is a conventional high frequency semiconductor device (Si-MOSFE).
Sectional drawing which shows the structure of T).
【図６】従来のシリコン高周波モノリシック集積回路の
構造を示す断面図。FIG. 6 is a cross-sectional view showing the structure of a conventional silicon high frequency monolithic integrated circuit.
１…半導体素子、１−１…ゲ−ト電極、１−２…ソ−ス
電極、１−３…ドレイン電極、１−４…層間絶縁膜、１
−５…高抵抗層、１−６…低抵抗層、１−７…裏面導
体、２−１、２−２マイクロストリップ線路、３…高抵
抗基板、４…ＳｉＯ2膜、５…低抵抗基板、６…ア−ス
導体、１１…ＩＣチップ、１２…高出力増幅回路、１２
−１…出力整合回路、１２−２…高出力素子、１２−３
…入力整合回路、１３…アンテナ共用器、１４…アンテ
ナ、１５…低雑音増幅回路、１５−１…入力整合回路、
１５−２…低雑音素子、１５−３…出力整合回路、１６
…受信ミクサ、１７…送信ミクサ、１８…周波数シンセ
サイザ、１９…復調回路、２０…変調回路、２１…ベ−
スバンド部。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 1-1 ... Gate electrode, 1-2 ... Source electrode, 1-3 ... Drain electrode, 1-4 ... Interlayer insulating film, 1
-5 ... high resistance layer, 1-6 ... low-resistance layer, 1-7 ... back conductor, 2-1, 2-2 microstrip line, 3 ... high resistance substrate, 4 ... SiO 2 film, 5 ... resistance substrate , 6 ... Ground conductor, 11 ... IC chip, 12 ... High-power amplifier circuit, 12
-1 ... Output matching circuit, 12-2 ... High output element, 12-3
... input matching circuit, 13 ... antenna duplexer, 14 ... antenna, 15 ... low noise amplification circuit, 15-1 ... input matching circuit,
15-2 ... Low noise element, 15-3 ... Output matching circuit, 16
... reception mixer, 17 ... transmission mixer, 18 ... frequency synthesizer, 19 ... demodulation circuit, 20 ... modulation circuit, 21 ... base
Sband section.
Claims (4)
サ、変復調回路等の異なった機能を有する回路を１チッ
プ内に構成する集積回路において、回路を構成する基板
として電気抵抗率の異なった複数のシリコン基板を張り
合わせた多層構造のシリコン基板を用い、前記基板の高
い電気抵抗率を有する方のシリコン基板上に集積回路を
形成すると共に高い電気抵抗率を有する方のシリコン基
板の一部を取り除いた低い電気抵抗率を有する方のシリ
コン基板の部分を少なくとも１ヶ所以上設け、前記低い
電気抵抗率を有する方のシリコン基板の部分にバイポー
ラトランジスタやＦＥＴ等のアクティブ素子を形成した
ことを特徴とする高周波モノリシック集積回路。1. An integrated circuit in which a circuit having different functions such as a high-power amplifier circuit, a low-noise amplifier circuit, a mixer, and a modulator / demodulator circuit is formed in one chip, and a substrate constituting the circuit has a different electric resistivity. Using a silicon substrate having a multi-layer structure in which a plurality of silicon substrates are bonded together, an integrated circuit is formed on the silicon substrate having a higher electric resistivity of the substrate, and a part of the silicon substrate having a higher electric resistivity is formed. At least one portion of the removed silicon substrate having the lower electrical resistivity is provided, and an active element such as a bipolar transistor or FET is formed on the portion of the silicon substrate having the lower electrical resistivity. High frequency monolithic integrated circuit.
を張り合わせた多層構造のシリコン基板を用い、高い電
気抵抗を有するシリコン基板の一部を取り除いた低い電
気抵抗を有する基板の部分にバイポーラトトランジスタ
やＦＥＴ等のアクティブ素子を形成し、残っている高い
電気抵抗率を有する基板の部分にストリップ線路やスパ
イラルインダクタンスを用いたインピーダンス整合回路
を構成したことを特徴とする高周波モノリシック集積回
路。2. A silicon substrate having a multi-layer structure in which a plurality of silicon substrates having different electric resistivities are bonded together is used, and a part of the silicon substrate having a high electric resistance is removed to form a bipolar transistor in a portion of the substrate having a low electric resistance. A high frequency monolithic integrated circuit characterized in that an active element such as a transistor or an FET is formed, and a strip line or an impedance matching circuit using a spiral inductance is formed on the remaining portion of the substrate having a high electric resistivity.
の異なった複数のシリコン基板を張り合わせた多層構造
の基板として、シリコン基板の間にＳｉＯ2を用い多層
化したＳＯＩ基板を用い、高い電気抵抗層を有するシリ
コン基板の電気抵抗が１０Ω・ｃｍ以上、低い電気抵抗
層を有するシリコン基板の電気抵抗が０．１Ω・ｃｍ以
下としたことを特徴とした高周波モノリシック集積回
路。3. A multi-layered SOI substrate using SiO 2 between silicon substrates as a substrate having a multi-layer structure in which a plurality of silicon substrates having different electric resistivities according to claim 1 and 2 are bonded together. A high-frequency monolithic integrated circuit characterized in that a silicon substrate having a high electric resistance layer has an electric resistance of 10 Ω · cm or more and a silicon substrate having a low electric resistance layer has an electric resistance of 0.1 Ω · cm or less.
リシック集積回路を用いた無線装置。4. A radio device using the high frequency monolithic integrated circuit according to claim 1. Description:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7177087A JPH0927594A (en) | 1995-07-13 | 1995-07-13 | High-frequency monolithic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7177087A JPH0927594A (en) | 1995-07-13 | 1995-07-13 | High-frequency monolithic integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0927594A true JPH0927594A (en) | 1997-01-28 |
Family
ID=16024907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7177087A Pending JPH0927594A (en) | 1995-07-13 | 1995-07-13 | High-frequency monolithic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0927594A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002015274A1 (en) * | 2000-08-14 | 2002-02-21 | Niigata Seimitsu Co., Ltd. | Semiconductor device for communication |
| US6973290B2 (en) | 1997-02-05 | 2005-12-06 | Telefonaktiebolaget L M Ericsson (Publ) | Radio architecture |
| JP2007288210A (en) * | 2007-06-18 | 2007-11-01 | Renesas Technology Corp | Semiconductor integrated circuit |
| US7414821B2 (en) | 2000-02-21 | 2008-08-19 | Renesas Technology Corp. | Semiconductor integrated circuit device |
-
1995
- 1995-07-13 JP JP7177087A patent/JPH0927594A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6973290B2 (en) | 1997-02-05 | 2005-12-06 | Telefonaktiebolaget L M Ericsson (Publ) | Radio architecture |
| US7414821B2 (en) | 2000-02-21 | 2008-08-19 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| WO2002015274A1 (en) * | 2000-08-14 | 2002-02-21 | Niigata Seimitsu Co., Ltd. | Semiconductor device for communication |
| JP2007288210A (en) * | 2007-06-18 | 2007-11-01 | Renesas Technology Corp | Semiconductor integrated circuit |
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