JPH08204008A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor deviceInfo
- Publication number
- JPH08204008A JPH08204008A JP7012412A JP1241295A JPH08204008A JP H08204008 A JPH08204008 A JP H08204008A JP 7012412 A JP7012412 A JP 7012412A JP 1241295 A JP1241295 A JP 1241295A JP H08204008 A JPH08204008 A JP H08204008A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- plasma cvd
- film
- pillar
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に多層配線構造を有する半導体装置の層間絶
縁膜にビアホールを形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a via hole in an interlayer insulating film of a semiconductor device having a multilayer wiring structure.
【０００２】[0002]
【従来の技術】半導体装置の集積度が増大するのにつれ
て、基板上に配線材料を多層にわたって形成する、いわ
ゆる多層配線化が進んでおり、このような多層配線構造
を有する半導体装置の製造工程が複雑化、長工程化して
きている。2. Description of the Related Art As the degree of integration of semiconductor devices increases, so-called multi-layer wiring is being formed, in which wiring materials are formed in multiple layers on a substrate, and the manufacturing process of a semiconductor device having such a multi-layer wiring structure is It is becoming more complicated and longer.
【０００３】特に、多層配線の形成工程が半導体装置の
製造価格に占める割合は大きく、半導体装置のコストダ
ウンを図る上で多層配線工程の低減化の要求が高まって
きている。In particular, the step of forming the multi-layered wiring occupies a large portion of the manufacturing cost of the semiconductor device, and there is an increasing demand for reduction of the multi-layered wiring step in order to reduce the cost of the semiconductor device.
【０００４】ここで、従来の多層配線の形成工程につい
て説明する。まず、下層配線用の第１の配線材料を堆積
後、下層配線のパターニングを行い、この下層配線上に
第１の絶縁膜を形成すると共に下層配線相互間に絶縁膜
を埋め込む。この時点では、前記下層配線のパターンな
どに依存して第１の絶縁膜の表面に段差が存在し、この
ままでは、この後の上層配線用の第２の配線材料の堆積
時および上層配線のパターニング時に悪影響を及ぼし、
上層配線の段切れによる断線、短絡などの重大な欠陥を
もたらすおそれがある。Here, a conventional process for forming a multi-layer wiring will be described. First, after depositing the first wiring material for the lower layer wiring, the lower layer wiring is patterned to form a first insulating film on the lower layer wiring and to bury the insulating film between the lower layer wirings. At this point, there is a step on the surface of the first insulating film depending on the pattern of the lower layer wiring, etc., and if it is left as it is, during the subsequent deposition of the second wiring material for the upper layer wiring and patterning of the upper layer wiring. Sometimes has a negative effect,
There is a risk of causing serious defects such as disconnection and short circuit due to disconnection of upper layer wiring.
【０００５】そこで、通常は、前記第１の絶縁膜上に第
２の配線材料を堆積する前に、その下地である第１の絶
縁膜の表面をレジストエッチバックにより平坦化して段
差を緩和した後、その上に第２の絶縁膜を形成してい
る。Therefore, usually, before depositing the second wiring material on the first insulating film, the surface of the underlying first insulating film is flattened by resist etch back to alleviate the step. After that, a second insulating film is formed on it.
【０００６】上記したような第１の絶縁膜と第２の絶縁
膜とが積層された従来の層間絶縁膜の形成工程は、１回
目の成膜→平坦化→２回目の成膜と工程数が多く、前記
したような多層配線工程の低減化の要求に対する大きな
障害となっている。The conventional process for forming an interlayer insulating film in which the first insulating film and the second insulating film are laminated is as follows: first film formation → planarization → second film formation and the number of processes. This is a major obstacle to the demand for reduction of the multilayer wiring process as described above.
【０００７】また、上記したような第１の絶縁膜の表面
を平坦化する方法の代わりに、第１の絶縁膜上に絶縁材
料であるスピン・オン・グラス（Spin on Glass ；ＳＯ
Ｇ）膜を形成することにより、上層配線材料の下地の段
差を緩和する方法も知られている。Further, instead of the method of flattening the surface of the first insulating film as described above, spin on glass (SO) which is an insulating material is formed on the first insulating film.
G) There is also known a method of forming a film to mitigate the step difference in the underlying layer of the upper wiring material.
【０００８】ところで、最近、前記したような多層配線
工程の低減化の要求に応える層間絶縁膜表面の平坦化技
術の１つとして、ＡＰＬ（Advanced Planarisation Lay
er）プロセスが報告（文献；Matsuura et.al., IEEE Te
ch.Dig., pp117,1994 ）されている。By the way, recently, as one of the techniques for flattening the surface of an interlayer insulating film, which meets the above-mentioned demand for reducing the number of multilayer wiring processes, APL (Advanced Planning Lay)
er) process reported (reference; Matsuura et.al., IEEE Te
ch.Dig., pp117, 1994).
【０００９】このＡＰＬプロセスは、層間絶縁膜の形成
に際して、ＳｉＨ4 ガスと酸化剤であるＨ2 Ｏ2 （過酸
化水素水）とを低温（例えば０℃程度）・真空中で反応
させることにより、下層配線上に自己流動型（リフロ
ー）のＳｉＯ2 膜（以下、リフローＳｉＯ2 膜という）
を形成するものである。This APL process involves reacting SiH 4 gas and H 2 O 2 (hydrogen peroxide solution), which is an oxidant, in a vacuum at a low temperature (for example, about 0 ° C.) when forming an interlayer insulating film. , A self-flowing type (reflow) SiO 2 film on the lower wiring (hereinafter referred to as a reflow SiO 2 film)
Is formed.
【００１０】この方法は、下層配線の配線相互間の絶縁
膜の埋め込みと絶縁膜表面の平坦化を同時に達成でき、
１回の成膜で平坦化までの工程を終了するので、多層配
線工程の低減化を実現できる。According to this method, the filling of the insulating film between the wirings of the lower layer wiring and the flattening of the insulating film surface can be achieved at the same time,
Since the steps up to planarization are completed by one film formation, it is possible to reduce the number of multilayer wiring steps.
【００１１】なお、上記リフローＳｉＯ2 膜を形成する
前に、下層配線上に第１層間絶縁膜（ベース絶縁膜）と
して通常のプラズマＣＶＤ法により第１のプラズマＳｉ
Ｏ2膜を形成し、上記リフローＳｉＯ2 膜を形成した後
にリフローＳｉＯ2 膜上に第２層間絶縁膜（キャップ絶
縁膜）として通常のプラズマＣＶＤ法により第２のプラ
ズマＳｉＯ2 膜を形成した後、ファーネス・アニールを
行う。Before forming the reflow SiO 2 film, a first plasma Si film is formed as a first interlayer insulating film (base insulating film) on the lower wiring by a usual plasma CVD method.
O 2 film is formed, after forming the second plasma SiO 2 film by a conventional plasma CVD method as the second interlayer insulating film (cap insulating film) in the reflow SiO 2 film after forming the reflow SiO 2 film , Perform furnace annealing.
【００１２】図３は、ＡＰＬプロセスを用いた層間絶縁
膜にアスペクト比が小さいビアホールを形成する工程の
従来例を示している。図３において、３０は半導体基
板、３１は下地絶縁膜、３２は下層配線、３３は下層配
線３２を含む基板上を覆うように形成された第１のプラ
ズマＳｉＯ2 膜（ベース絶縁膜）、３４は第１のプラズ
マＳｉＯ2 膜３３上に形成されたリフローＳｉＯ2 膜、
３５はリフローＳｉＯ2 膜３４上に形成された第２のプ
ラズマＳｉＯ2 膜（キャップ絶縁膜）である。FIG. 3 shows a conventional example of a process of forming a via hole having a small aspect ratio in an interlayer insulating film using the APL process. In FIG. 3, 30 is a semiconductor substrate, 31 is a base insulating film, 32 is a lower layer wiring, 33 is a first plasma SiO 2 film (base insulating film) formed so as to cover the substrate including the lower layer wiring 32, 34 Is a reflow SiO 2 film formed on the first plasma SiO 2 film 33,
Reference numeral 35 is a second plasma SiO 2 film (cap insulating film) formed on the reflow SiO 2 film 34.
【００１３】層間絶縁膜にビアホールを形成する際、第
２のプラズマＳｉＯ2 膜３５およびリフローＳｉＯ2 膜
３４にビアホール３６を開口形成した後、プラズマＣＶ
Ｄ法により水分のブロッキング能力の高いプラズマＳｉ
Ｎ膜３７を全面に形成する。この後、ビアホールの側壁
部にプラズマＳｉＮ膜を残してプラズマＳｉＮ膜の不要
部分を除去するように全面エッチバックを行うことによ
り、サイドウォール絶縁膜を形成する。When forming a via hole in the interlayer insulating film, after forming a via hole 36 in the second plasma SiO 2 film 35 and the reflow SiO 2 film 34, a plasma CV is formed.
Plasma Si with high water blocking ability by method D
The N film 37 is formed on the entire surface. After that, the side wall insulating film is formed by performing the entire surface etch back so as to remove the unnecessary portion of the plasma SiN film while leaving the plasma SiN film on the side wall of the via hole.
【００１４】ところで、ＡＰＬプロセスを用いた層間絶
縁膜に図４に示すようにアスペクト比が大きいビアホー
ル３６を形成する場合には、プラズマＳｉＮ膜３７のカ
バレッジが悪化し、ビアホール３６の側壁部にプラズマ
ＳｉＮ膜３７を均一な膜厚で形成することが困難にな
り、プラズマＳｉＮ膜３７の全面エッチバック後にビア
ホール３６の側壁部の一部ＡにリフローＳｉＯ2 膜３４
が露出する。By the way, when the via hole 36 having a large aspect ratio is formed in the interlayer insulating film using the APL process as shown in FIG. 4, the coverage of the plasma SiN film 37 is deteriorated and the plasma is formed on the sidewall of the via hole 36. It becomes difficult to form the SiN film 37 with a uniform film thickness, and after the entire surface of the plasma SiN film 37 is etched back, the reflow SiO 2 film 34 is formed on a part A of the sidewall portion of the via hole 36.
Is exposed.
【００１５】しかし、このリフローＳｉＯ2 膜３４は、
その形成時の反応により発生する水分を膜中に多く含ん
でいるので、ビアホール３６の側壁部にリフローＳｉＯ
2 膜３４が露出すると、この後にビアホール３６に上層
金属配線材料を埋め込む際に上下配線間の導通不良やビ
アコロージョンが発生し、配線導通の信頼性の低下や不
良が発生するおそれがある。However, the reflow SiO 2 film 34 is
Since the film contains a large amount of water generated by the reaction at the time of its formation, the reflow SiO 2 is formed on the side wall of the via hole 36.
If the second film 34 is exposed, a conductive failure between the upper and lower wirings or via corrosion may occur when the upper layer metal wiring material is embedded in the via hole 36 after that, and the reliability of the wiring conduction may be reduced or a failure may occur.
【００１６】[0016]
【発明が解決しようとする課題】上記したようにリフロ
ー絶縁膜形成技術により形成されたリフローＳｉＯ2 膜
を用いた層間絶縁膜にビアホールを形成する従来の方法
は、ビアホール径が小さい場合には上下配線間の導通不
良やビアコロージョンが発生し、配線導通の信頼性の低
下や不良が発生するおそれがあるという問題があった。As described above, the conventional method of forming via holes in the interlayer insulating film using the reflow SiO 2 film formed by the reflow insulating film forming technique has been described above when the via hole diameter is small. There is a problem in that there is a possibility that a poor continuity between wirings or via corrosion may occur, resulting in a decrease in reliability of wiring continuity or a failure.
【００１７】本発明は上記の問題点を解決すべくなされ
たもので、自己平坦化能力を有する絶縁膜を用いた層間
絶縁膜にビアホールを形成する際、ビアホールの側壁部
に自己平坦化能力を有する絶縁膜が露出しないようにサ
イドウォール絶縁膜を形成することができ、上下配線間
の導通の信頼性の低下や不良の発生を防止し得る半導体
装置の製造方法を提供することを目的とする。The present invention has been made to solve the above problems, and when a via hole is formed in an interlayer insulating film using an insulating film having a self-planarizing ability, the side wall portion of the via hole is provided with the self-planarizing ability. It is an object of the present invention to provide a method for manufacturing a semiconductor device, in which a sidewall insulating film can be formed so as not to expose an existing insulating film, and a decrease in reliability of conduction between upper and lower wirings and a defect can be prevented. .
【００１８】[0018]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上の第１の絶縁膜上に第１層目の
配線材料およびピラーを順次堆積形成する工程と、第１
層目の配線材料のビアコンタクト予定領域上に上記ピラ
ーを残すと共に第１層目の配線パターンを残すように上
記ピラーおよび第１層目の配線材料を選択的にエッチン
グする工程と、この後、プラズマＣＶＤ法により基板上
全面に第１のプラズマＣＶＤ絶縁膜を形成する工程と、
上記第１のプラズマＣＶＤ絶縁膜上に自己平坦化能力を
有する第２の絶縁膜を形成する工程と、上記第２の絶縁
膜を前記ピラーの上面より低い位置まで全面エッチバッ
クする工程と、この後、プラズマＣＶＤ法により基板上
全面に第２のプラズマＣＶＤ絶縁膜を形成する工程と、
上記第２のプラズマＣＶＤ絶縁膜上にエッチバック用の
レジストを塗布する工程と、前記ピラーの上面上の第１
のプラズマＣＶＤ絶縁膜が露出するまで上記レジストと
前記第２のプラズマＣＶＤ絶縁膜を同じエッチングレー
トでエッチバックする工程と、上記工程により露出した
第１のプラズマＣＶＤ絶縁膜の上面を前記ピラーの一部
が露出するまでエッチングする工程と、上記工程により
露出したピラーを除去する工程とを具備することを特徴
とする。A method of manufacturing a semiconductor device according to the present invention comprises a step of sequentially depositing and forming a first layer wiring material and pillars on a first insulating film on a semiconductor substrate, and a first step.
A step of selectively etching the pillars and the wiring material of the first layer so that the pillars are left on the via contact planned region of the wiring material of the layer and the wiring pattern of the first layer is left; and A step of forming a first plasma CVD insulating film on the entire surface of the substrate by a plasma CVD method,
A step of forming a second insulating film having a self-planarizing ability on the first plasma CVD insulating film; a step of completely etching back the second insulating film to a position lower than the upper surface of the pillar; After that, a step of forming a second plasma CVD insulating film on the entire surface of the substrate by the plasma CVD method,
A step of applying a resist for etching back on the second plasma CVD insulating film, and a first step on the upper surface of the pillar.
The step of etching back the resist and the second plasma CVD insulating film at the same etching rate until the plasma CVD insulating film is exposed, and the upper surface of the first plasma CVD insulating film exposed by the step is removed from the pillar. The method is characterized by including a step of etching until the portion is exposed, and a step of removing the pillar exposed by the above step.
【００１９】[0019]
【作用】本発明は、多層配線の層間絶縁膜の形成工程に
おいて、自己平坦化能力を有する第２の絶縁膜を形成す
る際、予め第１層目の配線材料のビアコンタクト予定領
域上に残したピラーの側壁部に第１のプラズマＣＶＤ絶
縁膜を形成しておき、この第１のプラズマＣＶＤ絶縁膜
上に自己平坦化能力を有する第２の絶縁膜を形成する。
そして、層間絶縁膜の形成後にビアホールを形成する
際、ピラーを除去することにより、ビアホールの側壁部
に第１のプラズマＣＶＤ絶縁膜が残るようになる。According to the present invention, when the second insulating film having the self-planarizing ability is formed in the step of forming the interlayer insulating film of the multilayer wiring, it is left in advance on the via contact planned region of the wiring material of the first layer. A first plasma CVD insulating film is formed on the side wall of the pillar, and a second insulating film having a self-planarizing ability is formed on the first plasma CVD insulating film.
Then, when the via hole is formed after the interlayer insulating film is formed, the pillars are removed, so that the first plasma CVD insulating film remains on the sidewall portion of the via hole.
【００２０】このように、予めピラーの側壁部に第１の
プラズマＣＶＤ絶縁膜を形成することにより、ビアホー
ルの側壁部にビアホールのアスペクト比に関係なく良好
なカバレッジで第１のプラズマＣＶＤ絶縁膜を形成する
ことができ、ビアホール径が小さい（アスペクト比が大
きい）場合でもビアホールの側壁部に第１のプラズマＣ
ＶＤ絶縁膜を均一な膜厚で形成することができる。By thus forming the first plasma CVD insulating film on the side wall of the pillar in advance, the first plasma CVD insulating film can be formed on the side wall of the via hole with good coverage regardless of the aspect ratio of the via hole. The first plasma C can be formed on the side wall of the via hole even when the via hole diameter is small (aspect ratio is large).
The VD insulating film can be formed with a uniform thickness.
【００２１】従って、自己平坦化能力を有する第２の絶
縁膜が膜中に水分を多く含んでいるリフローＳｉＯ2 膜
である場合でも、リフローＳｉＯ2 膜がビアホールの側
壁部に露出しないので、上下配線間の導通不良やビアコ
ロージョンが発生しなくなり、上下配線間の導通の信頼
性の低下や不良の発生を防止することが可能になる。Therefore, even when the second insulating film having the self-planarizing ability is a reflow SiO 2 film containing a large amount of water in the film, the reflow SiO 2 film is not exposed at the side wall of the via hole. It is possible to prevent defective conduction between wirings and via corrosion from occurring, and it is possible to prevent a decrease in reliability of conduction between the upper and lower wirings and the occurrence of defectiveness.
【００２２】[0022]
【実施例】以下、図面を参照して本発明の一実施例を詳
細に説明する。図１（ａ）乃至（ｄ）および図２（ａ）
乃至（ｄ）は、本発明の半導体装置の製造方法に係る多
層配線工程の一例を示している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1 (a) to 1 (d) and FIG. 2 (a)
8D to 8D show an example of a multi-layer wiring process according to the method for manufacturing a semiconductor device of the present invention.
【００２３】まず、図１（ａ）に示すように、通常の方
法により、半導体基板（通常、シリコンウエハー）１０
上の第１の絶縁膜１１上に下層配線用の第１層目の配線
パターン１２およびピラー１３を形成する。上記ピラー
１３は、後述するアッシングに際して、その側壁部に形
成される絶縁膜との選択比が高い材料（例えばポリイミ
ド）を用いることが望ましい。First, as shown in FIG. 1 (a), a semiconductor substrate (usually a silicon wafer) 10 is formed by an ordinary method.
A first-layer wiring pattern 12 and pillars 13 for lower layer wiring are formed on the upper first insulating film 11. The pillar 13 is preferably made of a material (for example, polyimide) having a high selection ratio with the insulating film formed on the side wall of the pillar 13 at the time of ashing described later.
【００２４】この場合、第１層目の配線材料（例えばＳ
ｉ、Ｃｕを含むアルミニウム）１２およびピラー１３を
順次堆積形成した後、フォトリソグラフィ技術および反
応性イオンエッチング（ＲＩＥ）技術を用いて、第１層
目の配線材料１２のビアコンタクト予定領域上に上記ピ
ラー１３を残すと共に第１層目の配線パターンを残すよ
うに上記ピラー１３および第１層目の配線材料１３を選
択的にエッチングする。あるいは、第１層目の配線材料
１３を形成して第１層目の配線パターンを残すように選
択的にエッチングした後に、前記ピラー１３を形成する
ようにしてもよい。In this case, the wiring material of the first layer (for example, S
(i, aluminum containing Cu) 12 and pillars 13 are sequentially deposited and formed, and then the above photolithography technique and reactive ion etching (RIE) technique are used to form the above on the via contact planned region of the wiring material 12 of the first layer. The pillars 13 and the wiring material 13 of the first layer are selectively etched so that the pillars 13 are left and the wiring pattern of the first layer is left. Alternatively, the pillar 13 may be formed after the wiring material 13 of the first layer is formed and selectively etched so that the wiring pattern of the first layer is left.
【００２５】次に、基板上全面にベース絶縁層としてプ
ラズマＣＶＤ法により第１のプラズマＣＶＤ絶縁膜１４
（Ｐ−ＳｉＮ）を形成する。この場合、水分のブロッキ
ング能力の高いプラズマＣＶＤ絶縁膜、例えばプラズマ
ＳｉＮ膜を形成することが望ましい。Next, the first plasma CVD insulating film 14 is formed as a base insulating layer on the entire surface of the substrate by the plasma CVD method.
(P-SiN) is formed. In this case, it is desirable to form a plasma CVD insulating film having a high moisture blocking ability, for example, a plasma SiN film.
【００２６】次に、図１（ｂ）に示すように、上記第１
のプラズマＣＶＤ絶縁膜１４上に自己平坦化能力を有す
る第２の絶縁膜１５を形成する。この第２の絶縁膜１５
を形成する工程の一例としては、前記第１のプラズマＣ
ＶＤ絶縁膜１４を形成後の半導体基板を収容したチャン
バー内にＳｉＨ4 ガスおよびＨ2 Ｏ2 を導入し、５Ｔｏ
ｒｒ＝５×１３３．３２２Ｐａ（ほぼ６６５Ｐａ）以下
の真空中、−１０℃以上＋１０℃以下の温度範囲内（例
えば０℃）で上記ＳｉＨ4 ガスおよびＨ2 Ｏ2を互いに
反応させる低温・減圧ＣＶＤ法によってリフローＳｉＯ
2 膜を形成する。Next, as shown in FIG. 1B, the first
A second insulating film 15 having a self-planarizing ability is formed on the plasma CVD insulating film 14 of FIG. This second insulating film 15
As an example of the step of forming the
SiH 4 gas and H 2 O 2 were introduced into the chamber containing the semiconductor substrate after the VD insulating film 14 was formed, and 5 To
Low temperature / reduced pressure CVD in which the SiH 4 gas and H 2 O 2 are reacted with each other within a temperature range of −10 ° C. or higher and + 10 ° C. or lower (for example, 0 ° C.) in a vacuum of rr = 5 × 133.322 Pa (approximately 665 Pa) or less. Reflow SiO by method
2 Form a film.
【００２７】次に、図１（ｃ）に示すように、上記第２
の絶縁膜１５を前記ピラー１３の上面より低い位置まで
全面エッチバックする。次に、図１（ｄ）に示すよう
に、基板上全面にキャップ絶縁層としてプラズマＣＶＤ
法により第２のプラズマＣＶＤ絶縁膜１６（Ｐ−ＳｉＯ
Ｎ）を形成する。上記第２のプラズマＣＶＤ絶縁膜１６
として、ＳｉＯ2 膜を形成してもよいが、それより水分
のブロッキング能力の高いプラズマＳｉＯＮ膜を形成す
ることが望ましい。Next, as shown in FIG. 1C, the second
The insulating film 15 is completely etched back to a position lower than the upper surface of the pillar 13. Next, as shown in FIG. 1D, plasma CVD is performed as a cap insulating layer on the entire surface of the substrate.
Second plasma CVD insulating film 16 (P-SiO 2
N). The second plasma CVD insulating film 16
As an example, a SiO 2 film may be formed, but it is desirable to form a plasma SiON film having a higher water blocking ability.
【００２８】次に、図２（ａ）に示すように、上記第２
のプラズマＣＶＤ絶縁膜１６上にエッチバック用のレジ
スト１７を塗布する。次に、図２（ｂ）に示すように、
前記ピラー１３上の第１のプラズマＣＶＤ絶縁膜１４の
上面が露出するまで上記レジスト１７と前記第２のプラ
ズマＣＶＤ絶縁膜１６を同じエッチングレートでエッチ
バックする。Next, as shown in FIG.
A resist 17 for etch back is applied on the plasma CVD insulating film 16 of FIG. Next, as shown in FIG.
The resist 17 and the second plasma CVD insulating film 16 are etched back at the same etching rate until the upper surface of the first plasma CVD insulating film 14 on the pillar 13 is exposed.
【００２９】次に、上記工程により露出した第１のプラ
ズマＣＶＤ絶縁膜１４の上面を、図２（ｃ）に示すよう
に前記ピラー１３の一部が露出するまでエッチングす
る。このエッチングは、第１のプラズマＣＶＤ絶縁膜１
４と第２のプラズマＣＶＤ絶縁膜１６との選択比が大き
く得られる、ＣＦ4 とＯ2 とを用いるケミカルドライエ
ッチングを行うことが望ましいが、選択比が１０以上
（Ｐ−ＳｉＯＮのエッチングレート／Ｐ−ＳｉＮのエッ
チングレート≧１０）得られれば、他の等方性及び異方
性エッチングでもよい。Next, the upper surface of the first plasma CVD insulating film 14 exposed by the above process is etched until a part of the pillar 13 is exposed as shown in FIG. 2C. This etching is performed on the first plasma CVD insulating film 1
4 and the second plasma CVD insulating film 16 can be obtained with a large selection ratio, and it is preferable to perform chemical dry etching using CF 4 and O 2 , but the selection ratio is 10 or more (P-SiON etching rate / Other isotropic and anisotropic etching may be used as long as the etching rate of P-SiN ≧ 10) can be obtained.
【００３０】次に、上記工程により露出したピラー１３
を、図２（ｄ）に示すようにＯ2 アッシャーにより除去
する。次に、基板上全面に第２層目の配線材料（図示せ
ず）を堆積形成し、第２層目の配線パターンを残すよう
に上記第２層目の配線材料を選択的にエッチングを行っ
て上層配線を形成する。Next, the pillar 13 exposed by the above process
Are removed by an O 2 asher as shown in FIG. Next, a second-layer wiring material (not shown) is deposited and formed on the entire surface of the substrate, and the second-layer wiring material is selectively etched so as to leave the second-layer wiring pattern. To form the upper layer wiring.
【００３１】上記実施例によれば、多層配線の層間絶縁
膜の形成工程において、第１層目の配線材料１２のビア
コンタクト予定領域上に残したピラー１３の側壁部に第
１のプラズマＣＶＤ絶縁膜１４を形成しておき、この第
１のプラズマＣＶＤ絶縁膜１４上に自己平坦化能力を有
する第２の絶縁膜１５を形成する。そして、層間絶縁膜
の形成後にビアホールを形成する際、ピラー１３を除去
することにより、ビアホールの側壁部に第１のプラズマ
ＣＶＤ絶縁膜１２が残るようになる。According to the above-described embodiment, in the step of forming the interlayer insulating film of the multi-layer wiring, the first plasma CVD insulation is performed on the side wall portion of the pillar 13 left on the via contact planned region of the wiring material 12 of the first layer. The film 14 is formed in advance, and the second insulating film 15 having a self-planarizing ability is formed on the first plasma CVD insulating film 14. Then, when the via hole is formed after the interlayer insulating film is formed, the pillar 13 is removed, so that the first plasma CVD insulating film 12 is left on the sidewall portion of the via hole.
【００３２】このように、予めピラーの側壁部に第１の
プラズマＣＶＤ絶縁膜１２を形成することにより、ビア
ホールの側壁部にビアホールのアスペクト比に関係なく
良好なカバレッジで第１のプラズマＣＶＤ絶縁膜１２を
形成することができ、ビアホール径が小さい（アスペク
ト比が大きい）場合でもビアホールの側壁部に第１のプ
ラズマＣＶＤ絶縁膜１２を均一な膜厚で形成することが
できる。By thus forming the first plasma CVD insulating film 12 on the side wall of the pillar in advance, the first plasma CVD insulating film can be formed on the side wall of the via hole with good coverage regardless of the aspect ratio of the via hole. 12 can be formed, and even if the via hole diameter is small (the aspect ratio is large), the first plasma CVD insulating film 12 can be formed with a uniform film thickness on the sidewall portion of the via hole.
【００３３】従って、自己平坦化能力を有する第２の絶
縁膜１５が膜中に水分を多く含んでいるリフローＳｉＯ
2 膜である場合でも、リフローＳｉＯ2 膜がビアホール
の側壁部に露出しないので、上下配線間の導通不良やビ
アコロージョンが発生しなくなり、導通の信頼性の低下
や不良の発生を防止することが可能になる。Therefore, the second insulating film 15 having the self-planarizing ability contains reflow SiO containing a large amount of water.
Even in the case of two films, since the reflow SiO 2 film is not exposed on the side wall of the via hole, conduction failure between the upper and lower wirings and via corrosion do not occur, and it is possible to prevent deterioration of conduction reliability and occurrence of failure. It will be possible.
【００３４】なお、前記自己平坦化能力を有する第２の
絶縁膜を形成する工程では、ＳＯＧを形成する、あるい
は、ＴＥＯＳとＯ3 ガスとを用いた常圧ＣＶＤ法により
ＴＥＯＳ／Ｏ3 −ＣＶＤ膜を形成するようにしてもよ
い。In the step of forming the second insulating film having the self-planarizing ability, SOG is formed or TEOS / O 3 -CVD is performed by the atmospheric pressure CVD method using TEOS and O 3 gas. A film may be formed.
【００３５】[0035]
【発明の効果】上述したように本発明の半導体装置の製
造方法によれば、自己平坦化能力を有する絶縁膜を用い
た層間絶縁膜にビアホールを形成する際、ビアホールの
側壁部に自己平坦化能力を有する絶縁膜が露出しないよ
うにサイドウォール絶縁膜を形成することができ、上下
配線間の導通の信頼性の低下や不良の発生を防止するこ
とができる。As described above, according to the method of manufacturing a semiconductor device of the present invention, when a via hole is formed in an interlayer insulating film using an insulating film having a self-planarizing ability, the side wall portion of the via hole is self-planarized. The sidewall insulating film can be formed so that the insulating film having the capability is not exposed, and the decrease in reliability of conduction between the upper and lower wirings and the occurrence of defects can be prevented.
【図１】本発明の半導体装置の製造方法の一実施例に係
る多層配線工程の一部を示す断面図。FIG. 1 is a sectional view showing a part of a multi-layer wiring process according to an embodiment of a method for manufacturing a semiconductor device of the present invention.
【図２】図１の工程につづく工程を示す断面図。FIG. 2 is a sectional view showing a step that follows the step of FIG.
【図３】従来の多層配線工程において層間絶縁膜にアス
ペクト比が小さいビアホールを形成する場合を示す断面
図。FIG. 3 is a sectional view showing a case where a via hole having a small aspect ratio is formed in an interlayer insulating film in a conventional multilayer wiring process.
【図４】従来の多層配線工程において層間絶縁膜にアス
ペクト比が大きいビアホールを形成する場合を示す断面
図。FIG. 4 is a sectional view showing a case where a via hole having a large aspect ratio is formed in an interlayer insulating film in a conventional multilayer wiring process.
【符号の説明】 １０…半導体基板、１１…第１の絶縁膜、１２…第１の
配線材料、１３…ピラー、１４…第１のプラズマＣＶＤ
絶縁膜（ＳｉＮ膜）、１５…第２の絶縁膜（リフローＳ
ｉＯ2 膜）、１６…第２のプラズマＣＶＤ絶縁膜（Ｓｉ
ＯＮ膜）、１７…レジスト。[Description of Reference Signs] 10 ... Semiconductor substrate, 11 ... First insulating film, 12 ... First wiring material, 13 ... Pillar, 14 ... First plasma CVD
Insulating film (SiN film), 15 ... Second insulating film (reflow S
iO 2 film), 16 ... Second plasma CVD insulating film (Si
ON film), 17 ... Resist.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/316 Ｍ 21/318 Ｍ Ｈ０１Ｌ 21/90 Ｋ Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 21/316 M 21/318 M H01L 21/90 K
Claims (3)
目の配線材料およびピラーを順次堆積形成する工程と、
第１層目の配線材料のビアコンタクト予定領域上に上記
ピラーを残すと共に第１層目の配線パターンを残すよう
に上記ピラーおよび第１層目の配線材料を選択的にエッ
チングする工程と、この後、プラズマＣＶＤ法により基
板上全面に第１のプラズマＣＶＤ絶縁膜を形成する工程
と、上記第１のプラズマＣＶＤ絶縁膜上に自己平坦化能
力を有する第２の絶縁膜を形成する工程と、上記第２の
絶縁膜を前記ピラーの上面より低い位置まで全面エッチ
バックする工程と、この後、プラズマＣＶＤ法により基
板上全面に第２のプラズマＣＶＤ絶縁膜を形成する工程
と、上記第２のプラズマＣＶＤ絶縁膜上にエッチバック
用のレジストを塗布する工程と、前記ピラーの上面上の
第１のプラズマＣＶＤ絶縁膜が露出するまで上記レジス
トと前記第２のプラズマＣＶＤ絶縁膜を同じエッチング
レートでエッチバックする工程と、上記工程により露出
した第１のプラズマＣＶＤ絶縁膜の上面を前記ピラーの
一部が露出するまでエッチングする工程と、上記工程に
より露出したピラーを除去する工程とを具備することを
特徴とする半導体装置の製造方法。1. A step of sequentially depositing and forming a first-layer wiring material and pillars on a first insulating film on a semiconductor substrate,
A step of selectively etching the pillars and the wiring material of the first layer so that the pillars are left on the via contact planned region of the wiring material of the first layer and the wiring pattern of the first layer is left; After that, a step of forming a first plasma CVD insulating film on the entire surface of the substrate by a plasma CVD method, and a step of forming a second insulating film having a self-planarizing ability on the first plasma CVD insulating film, A step of completely etching back the second insulating film to a position lower than the upper surface of the pillar; a step of forming a second plasma CVD insulating film over the entire surface of the substrate by a plasma CVD method; A step of applying a resist for etching back on the plasma CVD insulating film, and the resist and the second resist until the first plasma CVD insulating film on the upper surface of the pillar is exposed. A step of etching back the Zuma CVD insulating film at the same etching rate, a step of etching the upper surface of the first plasma CVD insulating film exposed by the above step until a part of the pillar is exposed, and a pillar exposed by the above step. A method of manufacturing a semiconductor device, comprising:
する工程は、プラズマＳｉＮ膜を形成することを特徴と
する請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first plasma CVD insulating film, a plasma SiN film is formed.
膜を形成する工程は、前記第１のプラズマＣＶＤ絶縁膜
を形成後の半導体基板を収容したチャンバー内にＳｉＨ
4 ガスおよびＨ2 Ｏ2 を導入し、６６５Ｐａ以下の真空
中、−１０℃以上＋１０℃以下の温度範囲内で上記Ｓｉ
Ｈ4 ガスおよびＨ2 Ｏ2 を互いに反応させることにより
リフローＳｉＯ2 膜を形成することを特徴とする請求項
１記載の半導体装置の製造方法。3. The step of forming the second insulating film having the self-planarizing ability includes the step of forming SiH in a chamber accommodating a semiconductor substrate on which the first plasma CVD insulating film is formed.
4 gas and H 2 O 2 were introduced, and the above Si was introduced in a temperature range of -10 ° C to + 10 ° C in a vacuum of 665 Pa or less.
The method of manufacturing a semiconductor device according to claim 1, wherein the reflow SiO 2 film is formed by reacting H 4 gas and H 2 O 2 with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01241295A JP3400162B2 (en) | 1995-01-30 | 1995-01-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01241295A JP3400162B2 (en) | 1995-01-30 | 1995-01-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08204008A true JPH08204008A (en) | 1996-08-09 |
| JP3400162B2 JP3400162B2 (en) | 2003-04-28 |
Family
ID=11804556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01241295A Expired - Fee Related JP3400162B2 (en) | 1995-01-30 | 1995-01-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3400162B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6368951B2 (en) | 1998-01-13 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device |
| US7061570B2 (en) | 2003-03-26 | 2006-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US7202155B2 (en) | 2003-08-15 | 2007-04-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing wiring and method for manufacturing semiconductor device |
| US7554117B2 (en) | 2003-03-26 | 2009-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2010021444A (en) * | 2008-07-11 | 2010-01-28 | Fujitsu Ltd | Electronic device, and manufacturing method thereof |
-
1995
- 1995-01-30 JP JP01241295A patent/JP3400162B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6368951B2 (en) | 1998-01-13 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device |
| US7061570B2 (en) | 2003-03-26 | 2006-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US7554117B2 (en) | 2003-03-26 | 2009-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US7847873B2 (en) | 2003-03-26 | 2010-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US7955910B2 (en) | 2003-03-26 | 2011-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US8760594B2 (en) | 2003-03-26 | 2014-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| US7202155B2 (en) | 2003-08-15 | 2007-04-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing wiring and method for manufacturing semiconductor device |
| US7358183B2 (en) | 2003-08-15 | 2008-04-15 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing wiring and method for manufacturing semiconductor device |
| JP2010021444A (en) * | 2008-07-11 | 2010-01-28 | Fujitsu Ltd | Electronic device, and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3400162B2 (en) | 2003-04-28 |
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