JPH08182349A - Pulse power source apparatus - Google Patents
Pulse power source apparatusInfo
- Publication number
- JPH08182349A JPH08182349A JP6325401A JP32540194A JPH08182349A JP H08182349 A JPH08182349 A JP H08182349A JP 6325401 A JP6325401 A JP 6325401A JP 32540194 A JP32540194 A JP 32540194A JP H08182349 A JPH08182349 A JP H08182349A
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- Prior art keywords
- voltage
- capacitor
- switching element
- load
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、クライストロン用パル
ス電源などの大出力パルス電源装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high power pulse power supply device such as a pulse power supply for klystron.
【０００２】[0002]
【従来の技術】クライストロン用パルス電源装置などで
は、ピーク電力１０〜１００MWの大出力と共に、パルス
波形の中に、１０〜１００μｓのパルス幅で１〜０.１
％の平坦な部分が要求される。2. Description of the Related Art In a pulse power supply device for a klystron or the like, a peak power of 10 to 100 MW and a pulse waveform of 1 to 0.1 with a pulse width of 10 to 100 μs are provided.
% Flat portion is required.
【０００３】この様なパルス波形を実現するため、従来
の第１の装置としては、例えば文献（Proceedings of t
he 18th Linear Accelerator Meeting in Japan, Tsuku
ba,21-23 July 1993 p182-184）に開示されているよう
な図１４に示すPFN回路が用いられていた。この回路に
おいて、４はスイッチング素子、２０は誘導電圧調整
器、２１は変圧器と整流器、２２は充電回路、２３はDe
‘Qing回路、２４はシャントダイオード、２５はパルス
成型回路網、２６はパルストランス、２７はクライスト
ロンである。図１４に示すこの回路では、まず、誘導電
圧調整器２０、変圧器/整流器２１、充電回路２２によ
り、パルス成型回路網２５の中のＣが充電される。De
‘Qing回路２３は、パルス成型回路網２５の中のＣの充
電電圧が所定の値になったときに充電を停止するもので
ある。次に、パルス成型回路網２５の負荷側に接続され
たスイッチ素子４、例えば、サイラトロンをoff状態か
らon状態にすると、負荷のパルストランス２６に電流が
流れ、昇圧されてクライストロン２７に高電圧パルスが
印加される。パルス成型回路網２５の段数が少ない場合
は出力波形が正弦波に近くなり、パルス波形の平坦性が
悪くなるので、段数を１０〜２０段と多く取る必要があ
る。In order to realize such a pulse waveform, a conventional first device is, for example, a document (Proceedings of t).
he 18th Linear Accelerator Meeting in Japan, Tsuku
ba, 21-23 July 1993 p182-184) and the PFN circuit shown in FIG. 14 was used. In this circuit, 4 is a switching element, 20 is an induction voltage regulator, 21 is a transformer and a rectifier, 22 is a charging circuit, and 23 is De.
'Qing circuit, 24 is a shunt diode, 25 is a pulse shaping network, 26 is a pulse transformer, and 27 is a klystron. In this circuit shown in FIG. 14, first, C in the pulse shaping network 25 is charged by the induction voltage regulator 20, the transformer / rectifier 21, and the charging circuit 22. De
The'Qing circuit 23 stops charging when the charging voltage of C in the pulse shaping network 25 reaches a predetermined value. Next, when the switch element 4 connected to the load side of the pulse shaping network 25, for example, the thyratron is turned from the off state to the on state, a current flows through the pulse transformer 26 of the load, the voltage is boosted, and the klystron 27 receives a high voltage pulse. Is applied. When the number of stages of the pulse shaping circuit network 25 is small, the output waveform becomes close to a sine wave and the flatness of the pulse waveform deteriorates. Therefore, it is necessary to increase the number of stages to 10 to 20.
【０００４】また、従来の第２の装置として、図１５に
示す単純なキャパシタの放電回路が用いられていた。こ
の回路において、３は放電キャパシタ、２８はコンバー
タ、２９はインバータ、３０は充電抵抗である。図１５
に示すこの回路では、まず、コンバータ２８、インバー
タ２９、変圧器／整流器２１、充電抵抗３０により、大
容量の放電キャパシタ３が充電される。次に、放電キャ
パシタ３の負荷側に接続された通電中のon-off動作が可
能なスイッチング素子４、例えば、IGBTスイッチをoff
状態からon状態にすると、負荷のパルストランス２６に
電流が流れ、昇圧されてクライストロン２７に高電圧パ
ルスが印加される。所定のパルス幅が得られた時点でス
イッチング素子４をoff状態にする。As a second conventional device, a simple capacitor discharge circuit shown in FIG. 15 has been used. In this circuit, 3 is a discharging capacitor, 28 is a converter, 29 is an inverter, and 30 is a charging resistor. FIG.
In this circuit shown in (1), first, the large-capacity discharge capacitor 3 is charged by the converter 28, the inverter 29, the transformer / rectifier 21, and the charging resistor 30. Next, a switching element 4 connected to the load side of the discharge capacitor 3 and capable of on-off operation during energization, for example, an IGBT switch is turned off.
When the state is changed to the on state, a current flows through the pulse transformer 26 of the load, the voltage is boosted, and the high voltage pulse is applied to the klystron 27. When a predetermined pulse width is obtained, the switching element 4 is turned off.
【０００５】また、従来の第３の装置として、例えば特
開昭４８−１３０７３号公報に開示されているパルスト
ランスの２次側に電圧のクランプ回路が用いられてい
た。図１６に示すこの回路において、３１は放電防止用
ダイオード、３２は平滑用キャパシタ、３３はバイアス
電源である。図１６に示すこの回路では、まず、パルス
トランス２８の２次側電圧で平滑用キャパシタ３２がバ
イアス電源３３の電圧を越えて充電される。この時、平
滑用キャパシタ３２の容量が十分大きいと、パルストラ
ンス２８の２次側電圧はほぼ一定に保たれる。次に、パ
ルス休止期間中にバイアス電源３３を介して平滑用キャ
パシタ３２がバイアス電源３３の電圧まで放電する。放
電防止用ダイオード３１はパルス休止期間中に平滑用キ
ャパシタ３２が負荷２９を介して放電するのを防止する
ものである。As a third conventional device, for example, a voltage clamp circuit is used on the secondary side of a pulse transformer disclosed in Japanese Patent Laid-Open No. 48-13073. In this circuit shown in FIG. 16, 31 is a discharge prevention diode, 32 is a smoothing capacitor, and 33 is a bias power supply. In the circuit shown in FIG. 16, first, the smoothing capacitor 32 exceeds the voltage of the bias power supply 33 and is charged by the secondary voltage of the pulse transformer 28. At this time, if the capacity of the smoothing capacitor 32 is sufficiently large, the secondary voltage of the pulse transformer 28 is kept substantially constant. Next, during the pulse pause period, the smoothing capacitor 32 is discharged to the voltage of the bias power source 33 via the bias power source 33. The discharge prevention diode 31 prevents the smoothing capacitor 32 from discharging through the load 29 during the pulse pause period.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記の
ような従来のパルス電源装置では、次に記載されるよう
な問題点があった。まず、第１の装置では、パルス成型
回路網２５が多数のキャパシタとインダクタで構成され
るため、電源装置が大型化し、高価になるという欠点が
あった。特に、パルス成型回路網２５は高電圧で充電さ
れているため、大型化は絶縁破壊に対する信頼性の低下
を招くなどの欠点もあった。また、第２の装置では、放
電キャパシタ３の放電に伴い出力電圧が低下する（すな
わちサグ電圧が発生する）ため、極めて大容量の放電キ
ャパシタ３を用いる必要があり、電源装置が大型化し、
高価になるという欠点があった。また、第３の装置で
は、電圧のクランプ回路が多数のキャパシタ３２、ダイ
オード３１、バイアス電源３３で高電圧部位に接続され
て構成されるため、電源装置が大型化し、高価になると
いう欠点があった。特に、高電圧部位に接続されている
ことは、大型化により絶縁破壊に対する信頼性の低下を
招くなどの欠点もあった。However, the conventional pulse power supply device as described above has the following problems. First, in the first device, since the pulse shaping circuit network 25 is composed of a large number of capacitors and inductors, the power supply device becomes large and expensive. In particular, since the pulse shaping circuit network 25 is charged at a high voltage, there is a drawback that an increase in size leads to a decrease in reliability against dielectric breakdown. Further, in the second device, the output voltage decreases (that is, a sag voltage is generated) as the discharge capacitor 3 discharges, so it is necessary to use the discharge capacitor 3 having an extremely large capacity, and the power supply device becomes large,
It had the drawback of being expensive. Further, in the third device, since the voltage clamp circuit is configured by being connected to the high voltage portion by the large number of capacitors 32, diodes 31, and bias power supply 33, there is a drawback that the power supply device becomes large and expensive. It was In particular, the connection to the high-voltage portion has a drawback that the size is increased and the reliability against dielectric breakdown is lowered.
【０００７】本発明は、かかる問題点を解決するために
なされたもので、装置が大型化し、高価になったり絶縁
破壊に対する信頼性が低下したりすることなく平坦なパ
ルス波形が得られるパルス電源装置を提供することを目
的とする。The present invention has been made in order to solve the above problems, and a pulse power supply capable of obtaining a flat pulse waveform without increasing the size of the device, increasing the cost, and lowering the reliability against dielectric breakdown. The purpose is to provide a device.
【０００８】[0008]
【課題を解決するための手段】請求項１記載の発明に係
るパルス電源装置は、充電されたキャパシタと、スイッ
チング素子と、負荷と、可変インピーダンスまたは出力
可変に構成された電源とが直列に接続され、上記スイッ
チング素子がオンした後の上記キャパシタの放電電圧の
低下分であるサグ電圧または上記負荷の両端電圧を検出
する手段と、上記検出手段の検出値を基準電圧と比較し
上記負荷の両端電圧を一定に保つように上記インピーダ
ンスまたは電源の電圧を制御する手段とを備えたもので
ある。According to another aspect of the pulse power supply device of the present invention, a charged capacitor, a switching element, a load, and a variable impedance or variable output power supply are connected in series. And a means for detecting a sag voltage or a voltage across the load, which is a decrease in the discharge voltage of the capacitor after the switching element is turned on, and a detection value of the detection means is compared with a reference voltage to compare the voltage across the load. And a means for controlling the impedance or the voltage of the power source so as to keep the voltage constant.
【０００９】また、請求項２記載の発明に係るパルス電
源装置は、請求項１の可変インピーダンスがトランジス
タであり、上記トランジスタのゲート電圧を放電電圧の
低下に伴って段階的に上昇させるものである。According to a second aspect of the pulse power supply device of the present invention, the variable impedance of the first aspect is a transistor, and the gate voltage of the transistor is increased stepwise as the discharge voltage decreases. .
【００１０】また、請求項３記載の発明に係るパルス電
源装置は、請求項１の可変インピーダンスが、直列に接
続されそれぞれにサグ補償用スイッチング素子が並列に
接続された複数の制御抵抗であり、放電電圧の低下に伴
って上記サグ補償用スイッチング素子を順次短絡させる
ものである。According to a third aspect of the pulse power supply device of the present invention, the variable impedance of the first aspect is a plurality of control resistors in which the variable impedances are connected in series and the sag compensation switching elements are connected in parallel. The sag compensation switching elements are sequentially short-circuited as the discharge voltage decreases.
【００１１】また、請求項４記載の発明に係るパルス電
源装置は、請求項１の可変インピーダンスが、並列に接
続されそれぞれにサグ補償用スイッチング素子が直列に
接続された複数の制御抵抗であり、放電電圧の低下に伴
って上記サグ補償用スイッチング素子を順次短絡させる
かまたは短絡させた後に開放させるものである。According to a fourth aspect of the pulse power supply device of the present invention, the variable impedances of the first aspect are a plurality of control resistors connected in parallel and each of which has a sag compensation switching element connected in series. The sag compensating switching elements are sequentially short-circuited or short-circuited with the decrease of the discharge voltage, and then opened.
【００１２】また、請求項５記載の発明に係るパルス電
源装置は、請求項１の出力可変に構成された電源が、直
列に接続されそれぞれにサグ補償用スイッチング素子が
並列に接続され正に充電された複数の制御キャパシタで
あり、放電電圧の低下に伴って上記サグ補償用スイッチ
ング素子を順次短絡させるものである。According to a fifth aspect of the present invention, there is provided a pulse power supply device in which the power sources having variable output according to the first aspect are connected in series, and sag compensation switching elements are connected in parallel to each other to positively charge them. The plurality of control capacitors are provided to sequentially short-circuit the sag compensation switching elements as the discharge voltage decreases.
【００１３】また、請求項６記載の発明に係るパルス電
源装置は、請求項１の出力可変に構成された電源が、並
列に接続されそれぞれにサグ補償用スイッチング素子が
直列に接続され正に充電された複数の制御キャパシタで
あり、放電電圧の低下に伴って上記サグ補償用スイッチ
ング素子を順次短絡させた後に開放させるものである。According to a sixth aspect of the present invention, there is provided a pulse power supply device in which the power sources having variable output according to the first aspect are connected in parallel, and a sag compensation switching element is connected in series to each of them to positively charge them. The plurality of control capacitors are arranged so that the sag compensation switching elements are sequentially short-circuited and then opened as the discharge voltage decreases.
【００１４】また、請求項７記載の発明に係るパルス電
源装置は、請求項１の出力可変に構成された電源が、直
列に接続されそれぞれにサグ補償用スイッチング素子が
接続され負に充電された複数の制御キャパシタであり、
放電電圧の低下に伴って上記サグ補償用スイッチング素
子で上記キャパシタを負荷電流の通路に順次接続させる
ものである。According to a seventh aspect of the present invention, the pulse power supply device according to the first aspect is configured such that the variable output power supplies of the first aspect are connected in series, and a sag compensation switching element is connected to each of them, so that the pulsed power supply is negatively charged. Multiple control capacitors,
With the decrease of the discharge voltage, the sag compensation switching element sequentially connects the capacitors to the path of the load current.
【００１５】また、請求項８記載の発明に係るパルス電
源装置は、請求項１の出力可変に構成された電源が、並
列に接続されそれぞれにサグ補償用スイッチング素子が
直列に接続され負に充電された複数の制御キャパシタで
あり、放電電圧の低下に伴って上記サグ補償用スイッチ
ング素子を順次短絡させるかまたは短絡させた後に開放
させるものである。According to an eighth aspect of the present invention, there is provided a pulse power supply device in which the power sources having variable output according to the first aspect are connected in parallel, and a sag compensation switching element is connected in series to each of the negative power sources. The plurality of control capacitors are provided, and the sag compensating switching elements are sequentially short-circuited with a decrease in discharge voltage, or short-circuited and then opened.
【００１６】また、請求項９記載の発明に係るパルス電
源装置は、充電された第１のキャパシタと、第２のキャ
パシタと、スイッチング素子と、負荷とが直列に接続さ
れ、上記スイッチング素子がオンした後の上記第１と第
２のキャパシタの和の電圧の低下分を検出する手段と、
上記検出手段の検出値を基準電圧と比較して上記負荷に
流れる電流を一定に保つように上記第２のキャパシタに
電流を流す手段とを備えたものである。According to a ninth aspect of the pulse power supply device of the present invention, the charged first capacitor, the second capacitor, the switching element, and the load are connected in series, and the switching element is turned on. Means for detecting a decrease in voltage of the sum of the first and second capacitors after
The detection value of the detection means is compared with a reference voltage to supply a current to the second capacitor so as to keep the current flowing through the load constant.
【００１７】[0017]
【作用】請求項１記載の発明によれば、キャパシタの放
電電圧または負荷電圧の低下分を検出し、基準電圧と比
較して、負荷に直列に挿入されたインピーダンスまたは
電源の電圧を制御する負帰還回路を構成し、負荷の両端
電圧を一定に保つので、パルス成形回路網を用いないた
め、多数のキャパシタやインダクタンスの代わりに１個
のキャパシタで構成でき、装置が小型で低コストとな
る。また、高電圧部が小型化されるので、絶縁破壊に対
する信頼性が大幅に向上する。さらに、キャパシタの放
電に伴う出力電圧の低下を補償しているため、小さい容
量のキャパシタの放電においても平坦なパルス波形が得
られる。According to the first aspect of the present invention, a decrease in the discharge voltage or the load voltage of the capacitor is detected and compared with the reference voltage to control the impedance inserted in series with the load or the voltage of the power supply. Since the feedback circuit is configured and the voltage across the load is kept constant, the pulse shaping circuit network is not used. Therefore, a single capacitor can be used instead of a large number of capacitors and inductances, and the device is small and low cost. Further, since the high voltage part is downsized, the reliability against dielectric breakdown is significantly improved. Furthermore, since the output voltage drop due to the discharge of the capacitor is compensated, a flat pulse waveform can be obtained even when the capacitor having a small capacitance is discharged.
【００１８】請求項２記載の発明によれば、請求項１の
可変インピーダンスがトランジスタであり、上記トラン
ジスタのゲート電圧を放電電圧の低下に伴って段階的に
上昇させるので、キャパシタの放電に伴う出力電圧の低
下の補償を段階的に行っており、請求項１の効果に加え
て、通常の負帰還回路に比較して安定な高速応答が実現
できる。According to the invention of claim 2, the variable impedance of claim 1 is a transistor, and since the gate voltage of the transistor is increased stepwise as the discharge voltage decreases, the output accompanying the discharge of the capacitor is increased. The voltage drop is compensated stepwise, and in addition to the effect of the first aspect, a stable high-speed response can be realized as compared with a normal negative feedback circuit.
【００１９】請求項３記載の発明によれば、請求項１の
可変インピーダンスが、直列に接続されそれぞれにサグ
補償用スイッチング素子が並列に接続された複数の制御
抵抗であり、放電電圧の低下に伴って上記サグ補償用ス
イッチング素子を順次短絡させるので、可変インピーダ
ンスをトランジスタの代わりに抵抗で構成しており、上
記請求項２の効果に加えて冷却構造が簡略化できると共
に、装置の信頼性が向上する。According to the third aspect of the present invention, the variable impedance of the first aspect is a plurality of control resistors which are connected in series and each of which has a sag compensation switching element connected in parallel, thereby reducing the discharge voltage. Accordingly, since the sag compensation switching elements are sequentially short-circuited, the variable impedance is configured by a resistor instead of a transistor, and in addition to the effect of claim 2, the cooling structure can be simplified and the reliability of the device can be improved. improves.
【００２０】請求項４記載の発明によれば、請求項１の
可変インピーダンスが、並列に接続されそれぞれにサグ
補償用スイッチング素子が直列に接続された複数の制御
抵抗であり、放電電圧の低下に伴って上記サグ補償用ス
イッチング素子を順次短絡させるかまたは短絡させた後
に開放させるので、各サグ補償用スイッチング素子を同
一電位で駆動でき、上記請求項３の効果に加えて回路構
成が簡単になる。According to a fourth aspect of the present invention, the variable impedance of the first aspect is a plurality of control resistors which are connected in parallel and each of which has a sag compensation switching element connected in series. Accordingly, the sag compensation switching elements are sequentially short-circuited or short-circuited and then opened, so that the sag compensation switching elements can be driven at the same potential, and the circuit configuration is simplified in addition to the effect of the third aspect. .
【００２１】請求項５記載の発明によれば、請求項１の
出力可変に構成された電源が、直列に接続されそれぞれ
にサグ補償用スイッチング素子が並列に接続され正に充
電された複数の制御キャパシタであり、放電電圧の低下
に伴って上記サグ補償用スイッチング素子を順次短絡さ
せるので、キャパシタの放電に伴う出力電圧の低下の補
償を正に充電されたキャパシタの切り換えにより行って
おり、電力を損失させる部分が少なく、上記請求項３の
効果に加えて、高効率の電源が実現できる。According to the invention as defined in claim 5, a plurality of control devices are provided in which the power sources having variable output according to claim 1 are connected in series and the sag compensation switching elements are connected in parallel to each other and are positively charged. Since it is a capacitor and the switching elements for sag compensation are sequentially short-circuited as the discharge voltage drops, the output voltage drop caused by the discharge of the capacitor is compensated by switching the positively charged capacitor, and the power is reduced. A portion to be lost is small, and in addition to the effect of claim 3, a highly efficient power source can be realized.
【００２２】請求項６記載の発明によれば、請求項１の
出力可変に構成された電源が、並列に接続されそれぞれ
にサグ補償用スイッチング素子が直列に接続され正に充
電された複数の制御キャパシタであり、放電電圧の低下
に伴って上記サグ補償用スイッチング素子を順次短絡さ
せた後に開放させるので、キャパシタを切り替える各サ
グ補償用スイッチング素子を同一電位で駆動でき、上記
請求項５の効果に加えて、回路構成が簡単になる。According to a sixth aspect of the present invention, a plurality of control sources in which the variable output power sources of the first aspect are connected in parallel and the sag compensation switching elements are connected in series to each other and are positively charged. The sag compensation switching element is a capacitor, and the sag compensation switching elements are sequentially short-circuited and then opened as the discharge voltage decreases. Therefore, the sag compensation switching elements for switching the capacitors can be driven at the same potential, and the effect of claim 5 can be obtained. In addition, the circuit configuration becomes simple.
【００２３】請求項７記載の発明によれば、請求項１の
出力可変に構成された電源が、直列に接続されそれぞれ
にサグ補償用スイッチング素子が接続され負に充電され
た複数の制御キャパシタであり、放電電圧の低下に伴っ
て上記サグ補償用スイッチング素子で上記キャパシタを
負荷電流の通路に順次接続させるので、キャパシタの放
電に伴う出力電圧の低下の補償を負に充電されたキャパ
シタの切り替えにより行っており、請求項５のものに比
較して電力を損失させる部分がさらに少なく、上記請求
項５の効果に加えて、より高効率の電源が実現できる。According to a seventh aspect of the present invention, the power source with variable output according to the first aspect is connected in series with a plurality of sag compensation switching elements connected to each other and a plurality of negatively charged control capacitors are provided. Yes, as the discharge voltage decreases, the sag compensation switching element sequentially connects the capacitors to the path of the load current.Therefore, compensation of the decrease in output voltage due to discharge of the capacitors is compensated by switching the negatively charged capacitors. In addition to the effect of the fifth aspect, a power source with higher efficiency can be realized, as compared with the fifth aspect.
【００２４】請求項８記載の発明によれば、請求項１の
出力可変に構成された電源が、並列に接続されそれぞれ
にサグ補償用スイッチング素子が直列に接続され負に充
電された複数の制御キャパシタであり、放電電圧の低下
に伴って上記サグ補償用スイッチング素子を順次短絡さ
せるかまたは短絡させた後に開放させるので、キャパシ
タを切り替える各サグ補償用スイッチング素子を同一電
位で駆動でき、上記請求項７の効果に加えて、回路構成
が簡単になる。According to an eighth aspect of the present invention, a plurality of control units in which the variable output power sources of the first aspect are connected in parallel and the sag compensation switching elements are connected in series to each of the negatively charged power sources. The sag compensation switching element is a capacitor, and the sag compensation switching elements are sequentially short-circuited with a decrease in discharge voltage or are opened after short-circuiting, so that each sag compensation switching element can be driven at the same potential. In addition to the effect of 7, the circuit configuration becomes simple.
【００２５】請求項９記載の発明によれば、充電された
第１のキャパシタと、第２のキャパシタと、スイッチン
グ素子と、負荷とが直列に接続され、上記スイッチング
素子がオンした後の上記第１と第２のキャパシタの和の
電圧の低下分を検出する手段と、上記検出手段の検出値
を基準電圧と比較して上記負荷に流れる電流を一定に保
つように上記第２のキャパシタに電流を流す手段とを備
えたので、パルス成形回路網を用いないため、多数のキ
ャパシタやインダクタンスの代わりに２個のキャパシタ
で構成でき、装置が小型で低コストとなる。また、高電
圧部が小型化されるので、絶縁破壊に対する信頼性が大
幅に向上する。また、キャパシタの放電に伴う出力電圧
の低下を補償しているため、小さい容量のキャパシタの
放電においても平坦なパルス波形が得られる。さらに、
キャパシタの放電に伴う出力電圧の低下の補償を連続的
に行えるので、請求項２〜８のものに比較してより平坦
なパルス波形が得られる。According to the ninth aspect of the invention, the charged first capacitor, the second capacitor, the switching element, and the load are connected in series, and the first capacitor after the switching element is turned on is connected. Means for detecting a decrease in voltage of the sum of the first and second capacitors, and a current flowing through the second capacitor so as to keep the current flowing through the load constant by comparing the detection value of the detection means with a reference voltage. Since the pulse shaping circuit network is not used, the device can be configured with two capacitors instead of a large number of capacitors and inductances, and the device is small in size and low in cost. Further, since the high voltage part is downsized, the reliability against dielectric breakdown is significantly improved. Further, since the output voltage drop due to the discharge of the capacitor is compensated for, a flat pulse waveform can be obtained even when the capacitor having a small capacitance is discharged. further,
Since the compensation of the decrease of the output voltage due to the discharge of the capacitor can be continuously performed, a flatter pulse waveform can be obtained as compared with the second to eighth aspects.
【００２６】[0026]
実施例１．図１は本発明の実施例１を説明する構成図で
ある。図において、１は直流電源、２は充電リアクト
ル、３は容量Ｃ1の放電キャパシタ、４はIGBT等通電中
にon-off動作が可能なスイッチング素子、５はパルスト
ランス等の負荷、６は放電キャパシタ３の放電電圧また
は負荷５の両端電圧検出用の分圧抵抗器、７は誤差アン
プ、７０は絶縁アンプ、８は基準電源、１０は出力可変
に構成されたインピーダンスであり例えばトランジスタ
など、９はトランジスタ１０のドライブ回路である。図
から明らかなように、放電キャパシタ３とスイッチング
素子４と負荷５とトランジスタ１０とが直列に接続され
ている。また、図２（ａ）〜（ｅ）は図１の回路の各部
の電圧波形を示し、（ａ）は放電キャパシタ３の両端電
圧Ｖ1(t) 、（ｂ）はスイッチング素子４のスイッチン
グ信号ｖ0(t) 、（ｃ）はスイッチング素子４の出力電
圧Ｖ2(t) 、（ｄ）はトランジスタ１０の両端電圧Ｖ
3(t) 、（ｅ）は負荷５の両端電圧Ｖ2(t)−Ｖ3(t) をそ
れぞれ示す。また、Ｖ0は放電キャパシタ３の充電電
圧、ΔＶはサグ電圧である。Example 1. First Embodiment FIG. 1 is a configuration diagram illustrating a first embodiment of the present invention. In the figure, 1 is a DC power source, 2 is a charging reactor, 3 is a discharge capacitor having a capacity of C 1 , 4 is a switching element capable of on-off operation during energization such as IGBT, 5 is a load such as a pulse transformer, and 6 is discharging. A voltage dividing resistor for detecting the discharge voltage of the capacitor 3 or the voltage across the load 5, 7 is an error amplifier, 70 is an isolation amplifier, 8 is a reference power supply, 10 is an impedance variable output, for example, a transistor, etc. Is a drive circuit of the transistor 10. As is clear from the figure, the discharge capacitor 3, the switching element 4, the load 5, and the transistor 10 are connected in series. 2 (a) to 2 (e) show voltage waveforms at various portions of the circuit of FIG. 1, (a) is a voltage V 1 (t) across the discharge capacitor 3, and (b) is a switching signal of the switching element 4. v 0 (t) and (c) are the output voltage V 2 (t) of the switching element 4, and (d) is the voltage V across the transistor 10.
3 (t) and (e) show the voltage V 2 (t) −V 3 (t) across the load 5, respectively. Further, V 0 is the charging voltage of the discharge capacitor 3, and ΔV is the sag voltage.
【００２７】上記のように構成された回路では、まず、
図１（ａ）では、放電キャパシタ３が充電リアクトル２
を介して直流電源１により充電される。次に、スイッチ
ング素子４がoff状態からon状態になると、放電キャパ
シタ３が放電し、負荷５に電流ｉ1が流れる。負荷５の
両端電圧は分圧抵抗器６でモニターされており、基準電
圧８と誤差アンプ７で付き合わされて誤差電圧v1(t) を
発生する。誤差電圧v1(t) はドライブ回路９に入力し、
トランジスタ１０の直流抵抗分 (トランジスタのon電
圧) を制御して、負荷５の両端電圧が一定になるように
動作させる。所定のパルス幅τが得られると、スイッチ
ング素子４がoff状態となる。図１（ａ）の回路の場
合、図２（ｅ）のように、負荷５の両端は、Ｖ0−ΔＶ
の一定電圧に保たれる。ここで、ΔＶ＝ｉ1τ／Ｃ1で表
される。In the circuit configured as described above, first,
In FIG. 1A, the discharge capacitor 3 is the charging reactor 2
It is charged by the DC power supply 1 via the. Next, when the switching element 4 changes from the off state to the on state, the discharge capacitor 3 discharges and the current i 1 flows through the load 5. The voltage across the load 5 is monitored by the voltage dividing resistor 6 and is matched with the reference voltage 8 by the error amplifier 7 to generate the error voltage v 1 (t). The error voltage v 1 (t) is input to the drive circuit 9,
The direct current resistance of the transistor 10 (on-voltage of the transistor) is controlled so that the voltage across the load 5 becomes constant. When the predetermined pulse width τ is obtained, the switching element 4 is turned off. In the case of the circuit of FIG. 1A, both ends of the load 5 are V 0 −ΔV as shown in FIG.
Maintained at a constant voltage. Here, it is represented by ΔV = i 1 τ / C 1 .
【００２８】このように構成されたパルス電源装置にお
いては、従来例のようにパルス成形回路網を用いないた
め、多数のキャパシタやインダクタンスの代わりに１個
のキャパシタで構成でき、装置が小型で低コストとな
る。また、高電圧部が小型化されるので、絶縁破壊に対
する信頼性が大幅に向上する。さらに、キャパシタの放
電に伴う出力電圧の低下を補償しているため、小さい容
量のキャパシタの放電においても平坦なパルス波形が得
られる。In the pulse power supply device configured as described above, since the pulse shaping circuit network is not used unlike the conventional example, it is possible to configure a single capacitor instead of a large number of capacitors and inductances, and the device is small and low in size. It will be a cost. Further, since the high voltage part is downsized, the reliability against dielectric breakdown is significantly improved. Furthermore, since the output voltage drop due to the discharge of the capacitor is compensated, a flat pulse waveform can be obtained even when the capacitor having a small capacitance is discharged.
【００２９】なお、この回路の動作は通常の負帰還回路
のように連続的に行われても良いが、帰還ループの利得
が高い場合は系の発振などの悪影響が現れる。この場合
は、トランジスタ１０のゲートに印加する電圧をあらか
じめ数種類用意しておき、それをディスクリート（段階
的）に切り替えて動作させれば良い。この動作について
は図１（ｂ）を用いて説明する。図１（ｂ）では、放電
キャパシタ３の電圧を分圧抵抗器６でモニターしてい
る。図３（ａ）〜（ｃ）はこの動作における制御系の電
圧波形であり、（ａ）は基準電源の出力電圧ｖ
s（ｔ）、（ｂ）は誤差アンプ７の出力電圧ｖ1(t) 、
（ｃ）はトランジスタ１０のドライブ電圧ｖ2(t) を示
している。図４（ａ）〜（ｅ）は段階的に切り替えて動
作させた場合の電圧波形であり、ΔＶ0は補償後のサグ
電圧である。この動作においては、切り替え数ｎに応じ
たリップル（脈動電圧）ΔＶ0が発生し、その値はΔＶ0
＝ΔＶ／ｎで与えられ、ｎ＝１０の場合、サグ電圧は１
／１０に低減される。負荷５の両端電圧は、Ｖ0−ΔＶ
−ΔＶ0／２ ±ΔＶ0／２ に保たれる。また、この段階
的に制御する動作においては、基準電源の出力電圧は図
３（ａ）に示すように、段階的に減少する波形を用い
る。なお、紙面の都合上、図４は図３より縮小されて示
されている。The operation of this circuit may be continuously performed like an ordinary negative feedback circuit, but when the gain of the feedback loop is high, an adverse effect such as system oscillation appears. In this case, several kinds of voltages to be applied to the gate of the transistor 10 may be prepared in advance, and these may be discretely (stepwise) switched to operate. This operation will be described with reference to FIG. In FIG. 1B, the voltage of the discharge capacitor 3 is monitored by the voltage dividing resistor 6. 3A to 3C are voltage waveforms of the control system in this operation, and FIG. 3A is an output voltage v of the reference power source.
s (t) and (b) are the output voltage v 1 (t) of the error amplifier 7,
(C) shows the drive voltage v 2 (t) of the transistor 10. FIGS. 4A to 4E are voltage waveforms in the case where they are switched and operated stepwise, and ΔV 0 is a sag voltage after compensation. In this operation, ripple (pulsation voltage) ΔV 0 is generated according to the switching number n, and its value is ΔV 0.
= ΔV / n, and when n = 10, the sag voltage is 1
It is reduced to / 10. The voltage across the load 5 is V 0 −ΔV
It is kept to -ΔV 0/2 ± ΔV 0/ 2. Further, in this step-by-step control operation, the output voltage of the reference power supply has a waveform that gradually decreases as shown in FIG. Note that, due to space limitations, FIG. 4 is shown in a reduced scale compared to FIG.
【００３０】実施例２．図５は本発明の実施例２を説明
する構成図であり、図において、１１は制御抵抗、１２
はサグ補償用スイッチング素子である。上記実施例１に
示した構成ではトランジスタ１０のon電圧をディスクリ
ート（段階的に）に切り替えたが、負荷５と直列に制御
抵抗１１を接続し、各制御抵抗１１を並列に接続された
サグ補償用スイッチング素子１２を順次on状態にして制
御抵抗１１を短絡し、放電キャパシタ３の両端電圧Ｖ
1(t) が垂下しても負荷５の両端電圧が一定になるよう
に制御する。負荷５の両端電圧は、Ｖ0−ΔＶ−ΔＶ0／
２ ±ΔＶ0／２ に保たれる。このように、可変インピ
ーダンスを実施例１のトランジスタ１０の代わりに発熱
により動作が不安定にならない抵抗１１で構成すること
により、冷却構造が簡略化できると共に、装置の信頼性
が向上する。Example 2. FIG. 5 is a configuration diagram illustrating a second embodiment of the present invention, in which 11 is a control resistor and 12 is a control resistor.
Is a switching element for sag compensation. In the configuration shown in the first embodiment, the on voltage of the transistor 10 is switched to discrete (stepwise), but the control resistor 11 is connected in series with the load 5 and the sag compensation in which the control resistors 11 are connected in parallel is performed. The switching element 12 is turned on sequentially to short-circuit the control resistor 11 and the voltage V across the discharge capacitor 3 is increased.
Control so that the voltage across load 5 remains constant even if 1 (t) droops. The voltage across the load 5 is V 0 −ΔV−ΔV 0 /
It is maintained at 2 ± ΔV 0/2. As described above, by configuring the variable impedance with the resistor 11 which does not become unstable due to heat generation instead of the transistor 10 of the first embodiment, the cooling structure can be simplified and the reliability of the device is improved.
【００３１】この例では制御抵抗１１は直列に接続され
ており、各サグ補償用スイッチング素子１２の耐電圧を
同じにすることができる。図７は誤差アンプの出力電圧
ｖ1(t) に対するサグ補償用スイッチング素子１２のド
ライブ信号の説明図であり、図５の回路では図７（ｂ）
に示すｖ3(t) の信号がｂ−１、ｂ−２、…と順に各サ
グ補償用スイッチング素子１２に印加され、１度短絡さ
れた制御抵抗１１はパルス動作の１サイクル中は短絡さ
れたままである。In this example, the control resistors 11 are connected in series, and the sag compensation switching elements 12 can have the same withstand voltage. FIG. 7 is an explanatory diagram of the drive signal of the sag compensation switching element 12 with respect to the output voltage v 1 (t) of the error amplifier. In the circuit of FIG. 5, FIG.
The signal of v 3 (t) shown in FIG. 2 is applied to each sag compensation switching element 12 in the order of b-1, b-2, ..., The control resistor 11 short-circuited once is short-circuited during one cycle of pulse operation. It remains.
【００３２】実施例３．また、抵抗群は図６に示す様に
並列接続でも良く、サグ補償用スイッチング素子１２は
制御抵抗１１と直列に接続され、この場合は各サグ補償
用スイッチング素子１２は同一ポテンシャルでドライブ
（駆動）でき、回路構成が簡単になる。図６の回路では
図７（ｂ）に示すｖ3(t) または図７（ｃ）に示すｖ
4(t) の信号がｂ−１、ｂ−２、…またはｃ−１、ｃ−
２、…と順に各サグ補償用スイッチング素子１２に印加
される。ｖ4(t) の信号を印加する場合は制御抵抗１１
を完全に切り替える。ｖ3(t) の信号を印加する場合は
制御抵抗１１の組み合わせで所望の抵抗値を得るもの
で、サグ補償用スイッチング素子１２のスイッチング回
数を減らすことができる。Example 3. Further, the resistance group may be connected in parallel as shown in FIG. 6, and the sag compensation switching element 12 is connected in series with the control resistor 11. In this case, each sag compensation switching element 12 is driven by the same potential. And the circuit configuration becomes simple. In the circuit of FIG. 6, v 3 (t) shown in FIG. 7B or v 3 (t) shown in FIG. 7C is used.
4 (t) signal is b-1, b-2, ... Or c-1, c-
2, ... Are sequentially applied to each sag compensation switching element 12. When applying the signal of v 4 (t), the control resistor 11
To switch completely. When the signal of v 3 (t) is applied, a desired resistance value is obtained by combining the control resistors 11, and the number of times of switching of the sag compensation switching element 12 can be reduced.
【００３３】実施例４．図８は本発明の実施例４を説明
する構成図であり、図において、１３は制御キャパシ
タ、１４は短絡防止用ダイオード、１５は放電抵抗、１
６は充電用電源である。上記実施例１に示した構成では
トランジスタ１０のon電圧をディスクリートに切り替え
たが、負荷５と直列にあらかじめ正に充電された制御キ
ャパシタ１３を接続し、各制御キャパシタ１３に並列接
続されたサグ補償用スイッチング素子１２を順次on状態
にして制御キャパシタ１３の回路を短絡し、放電キャパ
シタ３の両端電圧V１(t) が垂下しても負荷５の両端電
圧が一定になるように制御する。制御キャパシタ１３は
正に充電されているため、パルスの初期段階では放電キ
ャパシタ３の両端電圧を打ち消す方向に働き、放電キャ
パシタ３の両端電圧Ｖ1(t) が垂下するに従って、順次
打ち消し電圧を短絡するように働く。負荷５の両端電圧
は、Ｖ0−ΔＶ−ΔＶ0／２ ±ΔＶ0／２ に保たれる。
短絡防止用ダイオード１４は制御キャパシタ１３の放電
を防止するものである。また、制御キャパシタ１３は動
作中に負荷５を流れる電流で充電されて制御キャパシタ
１３の両端電圧が少し上昇するため、パルスの休止期間
中に放電抵抗１５を介して初期の電圧値まで放電させ
る。このように、キャパシタの放電に伴う出力電圧の低
下の補償を正に充電されたキャパシタ１３の切り換えに
より行うことにより、電力を損失させる部分が少なく、
高効率の電源が実現できる。Example 4. 8 is a configuration diagram illustrating a fourth embodiment of the present invention, in which 13 is a control capacitor, 14 is a short-circuit prevention diode, 15 is a discharge resistor, and 1 is a discharge resistor.
6 is a charging power source. In the configuration shown in the first embodiment, the on voltage of the transistor 10 is switched to discrete, but the control capacitors 13 that are positively charged in advance are connected in series with the load 5, and the sag compensation connected in parallel to each control capacitor 13. The switching elements 12 are sequentially turned on to short-circuit the circuit of the control capacitor 13 so that the voltage across the load 5 is constant even if the voltage V1 (t) across the discharge capacitor 3 drops. Since the control capacitor 13 is positively charged, it works in the direction of canceling the voltage across the discharge capacitor 3 in the initial stage of the pulse, and as the voltage V 1 (t) across the discharge capacitor 3 drops, the cancel voltage is sequentially short-circuited. Work to do. Voltage across the load 5 is kept at V 0 -ΔV-ΔV 0/2 ± ΔV 0/2.
The short-circuit prevention diode 14 prevents the control capacitor 13 from discharging. Further, the control capacitor 13 is charged by the current flowing through the load 5 during operation, and the voltage across the control capacitor 13 rises a little, so the control capacitor 13 is discharged to the initial voltage value through the discharge resistor 15 during the pulse rest period. In this way, by compensating for the decrease in the output voltage due to the discharge of the capacitor by switching the positively charged capacitor 13, there is little loss of power,
A highly efficient power supply can be realized.
【００３４】この例では制御キャパシタ１３は直列に接
続されており、各サグ補償用スイッチング素子１２の耐
電圧を同じにすることができる。この回路のサグ補償用
スイッチング素子１２のドライブ信号は図７（ｂ）のｖ
3(t) であり、１度短絡された制御キャパシタ１３はパ
ルス動作の１サイクル中は短絡されたままである。In this example, the control capacitors 13 are connected in series, and the sag compensation switching elements 12 can have the same withstand voltage. The drive signal of the sag compensation switching element 12 of this circuit is represented by v in FIG.
3 (t), the control capacitor 13 which has been short-circuited once remains short-circuited during one cycle of the pulse operation.
【００３５】実施例５．また、制御キャパシタ１３は図
９に示す様に並列接続でも良く、サグ補償用スイッチン
グ素子１２は制御キャパシタ１３と直列に接続され、こ
の場合は各サグ補償用スイッチング素子１２は同一ポテ
ンシャルでドライブでき、回路構成が簡単になる。この
回路のサグ補償用スイッチング素子１２のドライブ信号
は図７（ｃ）のｖ4(t) である。また、この回路では短
絡防止用ダイオード１４は必要としない。Example 5. The control capacitor 13 may be connected in parallel as shown in FIG. 9, and the sag compensation switching element 12 is connected in series with the control capacitor 13. In this case, each sag compensation switching element 12 can be driven with the same potential. The circuit configuration becomes simple. The drive signal of the sag compensation switching element 12 of this circuit is v 4 (t) in FIG. 7C. Further, this circuit does not require the short-circuit prevention diode 14.
【００３６】実施例６．図１０は本発明の実施例６を説
明する構成図、図１１（ａ）〜（ｅ）は図１０の回路の
各部の電圧波形を示す説明図である。上記実施例４に示
した構成では負荷５と直列にあらかじめ正に充電された
制御キャパシタ１３を接続したが、負荷と直列にあらか
じめ負に充電された制御キャパシタ１３を接続し、サグ
補償用スイッチング素子１２を順次on状態にして制御キ
ャパシタ１３を接続していき、放電キャパシタ３の両端
電圧Ｖ1(t) が垂下しても負荷５の両端電圧が一定にな
るように制御する。制御キャパシタ１３は負に充電され
ているため、パルスの初期段階では動作しないが、放電
キャパシタ３の両端電圧Ｖ1(t) が垂下するに従って、
順次、垂下分の電圧を補償するように働く。負荷５の両
端電圧は、図１１に示すように、Ｖ0−ΔＶ0／２ ±Δ
Ｖ0／２ に保たれる。制御キャパシタ１３に蓄積された
エネルギーは動作中に負荷５で消費されるため、上記実
施例４のように余分なエネルギーを放電抵抗１５を介し
て消費させる必要はなく、電力効率の高い補償回路が構
成できる。この例では制御キャパシタ１３は直列に接続
されており、各サグ補償用スイッチング素子１２の耐電
圧を同じにすることができる。この回路のサグ補償用ス
イッチング素子１２のドライブ信号は図７（ｂ）のｖ
3(t) であり、１度短絡された制御キャパシタ１３はパ
ルス動作の１サイクル中は短絡されたままである。Example 6. FIG. 10 is a configuration diagram illustrating a sixth embodiment of the present invention, and FIGS. 11A to 11E are explanatory diagrams showing voltage waveforms of respective parts of the circuit of FIG. In the configuration shown in the fourth embodiment, the control capacitor 13 that is positively charged in advance is connected in series with the load 5, but the control capacitor 13 that is negatively charged in advance is connected in series with the load, and the sag compensation switching element is connected. 12 is sequentially turned on and the control capacitor 13 is connected to control so that the voltage across the load 5 is constant even if the voltage V 1 (t) across the discharge capacitor 3 drops. Since the control capacitor 13 is negatively charged, it does not operate in the initial stage of the pulse, but as the voltage V 1 (t) across the discharge capacitor 3 drops,
Sequentially, it works to compensate the drooping voltage. Voltage across the load 5, as shown in FIG. 11, V 0 -ΔV 0/2 ± Δ
It is maintained at V 0/2. Since the energy stored in the control capacitor 13 is consumed by the load 5 during operation, it is not necessary to consume extra energy through the discharge resistor 15 as in the fourth embodiment, and a compensation circuit with high power efficiency can be provided. Can be configured. In this example, the control capacitors 13 are connected in series so that the sag compensation switching elements 12 can have the same withstand voltage. The drive signal of the sag compensation switching element 12 of this circuit is represented by v in FIG.
3 (t), the control capacitor 13 which has been short-circuited once remains short-circuited during one cycle of the pulse operation.
【００３７】実施例７．また、制御キャパシタ１３は図
１２に示す様に並列接続でも良く、サグ補償用スイッチ
ング素子１２は制御キャパシタ１３と直列に接続され、
この場合は各サグ補償用スイッチング素子１２は同一ポ
テンシャルでドライブでき、回路構成が簡単になる。こ
の回路のサグ補償用スイッチング素子１２のドライブ信
号は図７（ｂ）、（ｃ）のｖ3(t) 、ｖ4(t) のいずれを
用いても良い。Example 7. The control capacitor 13 may be connected in parallel as shown in FIG. 12, and the sag compensation switching element 12 is connected in series with the control capacitor 13.
In this case, each sag compensation switching element 12 can be driven with the same potential, and the circuit configuration is simplified. As the drive signal of the sag compensation switching element 12 of this circuit, any of v 3 (t) and v 4 (t) in FIGS. 7B and 7C may be used.
【００３８】実施例８．図１３は本発明の実施例８を説
明する構成図であり、図において、１７は補償用直流電
源、１８は定電流制御用キャパシタ、１９は定電流制御
回路である。上記のように構成された回路では、直流電
源１と第１のキャパシタすなわち放電キャパシタ３の他
にサグ補償用の直流電源１７と第２のキャパシタすなわ
ち定電流制御用キャパシタ１８とを別に持ち、第１、第
２のキャパシタ３、１８と、スイッチング素子４と、負
荷５とが直列に接続され、定電流制御用キャパシタ１８
に放電キャパシタ３の電圧のサグを補償する電圧を発生
するような電流を流すことにより負荷５にかかる電圧を
一定にする。Example 8. 13 is a configuration diagram for explaining an eighth embodiment of the present invention. In the figure, 17 is a compensation DC power supply, 18 is a constant current control capacitor, and 19 is a constant current control circuit. In the circuit configured as described above, in addition to the DC power supply 1 and the first capacitor, that is, the discharge capacitor 3, the sag compensation DC power supply 17 and the second capacitor, that is, the constant current control capacitor 18, are separately provided. The first and second capacitors 3 and 18, the switching element 4, and the load 5 are connected in series, and the constant current control capacitor 18
In order to make the voltage applied to the load 5 constant, a current is generated so as to generate a voltage that compensates the sag of the voltage of the discharge capacitor 3.
【００３９】まず、容量Ｃ1の放電キャパシタ３が充電
リアクトル２を介して直流電源１により電圧Ｖ0に充電
される。次に、スイッチング素子４がoff状態からon状
態になると、放電キャパシタ３が放電し、容量Ｃ2の定
電流制御用キャパシタ１８を介して負荷５に電流ｉ1が
流れる。同時に、定電流制御回路１９が作動し定電流制
御用キャパシタ１８に電流ｉ2を流し、放電キャパシタ
３の電圧低下を補償する。今、放電キャパシタ３の電圧
をＶ1(t)、定電流制御用キャパシタ１８の両端電圧をＶ
2(t)とすると、負荷５の両端電圧Ｖ(t)は Ｖ(t) ＝ Ｖ0 − ∫ｉ1ｄｔ／Ｃ1 ｉ1〜constantだから Ｖ(t) ＝ Ｖ0 − ｉ1ｔ／Ｃ1 Ｖ2(t)は Ｖ2(t) ＝ （ｉ2 − ｉ1）ｔ／Ｃ2 ｉ1ｔ／Ｃ1 ＝ （ｉ2 − ｉ1）ｔ／Ｃ2のとき負荷電圧
Ｖ(t) は一定となる。即ち、 ｉ1／Ｃ1 ＝ （ｉ2 − ｉ1）／Ｃ2 （１／Ｃ1 ＋ １／Ｃ2）ｉ1 ＝ ｉ2／Ｃ2 ｉ2 ＝ （Ｃ1 ＋ Ｃ2）ｉ1／Ｃ1 Ｃ1 ＝ Ｃ2とすると、ｉ2 ＝ ２ｉ1となり、負荷電圧Ｖ
(t)は一定となる。First, the discharge capacitor 3 having the capacity C 1 is charged to the voltage V 0 by the DC power supply 1 via the charging reactor 2. Next, when the switching element 4 changes from the off state to the on state, the discharge capacitor 3 discharges, and the current i 1 flows through the load 5 through the constant current control capacitor 18 having the capacitance C 2 . At the same time, the constant current control circuit 19 operates to allow the current i 2 to flow through the constant current control capacitor 18 to compensate for the voltage drop of the discharge capacitor 3. Now, the voltage of the discharge capacitor 3 is V 1 (t) and the voltage across the constant current control capacitor 18 is V 1 (t).
When 2 (t), the load 5 voltage across V (t) is V (t) = V 0 - ∫i 1 dt / C 1 i 1 ~constant So V (t) = V 0 - i 1 t / C 1 V 2 (t) is the load voltage V (t) when V 2 (t) = (i 2 − i 1 ) t / C 2 i 1 t / C 1 = (i 2 − i 1 ) t / C 2. Is constant. That, i 1 / C 1 = ( i 2 - i 1) / C 2 (1 / C 1 + 1 / C 2) i 1 = i 2 / C 2 i 2 = (C 1 + C 2) i 1 / If C 1 C 1 = C 2 , then i 2 = 2i 1 and the load voltage V
(t) is constant.
【００４０】この動作において、放電キャパシタ３の放
電電圧は分圧抵抗器６でモニターされており、基準電圧
８と誤差アンプ７で付き合わされて誤差電圧ｖ1(t) を
発生する。誤差電圧ｖ1(t) はドライブ回路９に入力
し、定電流制御回路１９を制御して、定電流制御用キャ
パシタ１８に所望の一定電流を流す。所定のパルス幅が
得られると、スイッチング素子４がoff状態となる。図
１３の回路の場合、負荷５の両端は、Ｖ0の一定電圧に
保たれる。In this operation, the discharge voltage of the discharge capacitor 3 is monitored by the voltage dividing resistor 6 and is matched with the reference voltage 8 by the error amplifier 7 to generate the error voltage v 1 (t). The error voltage v 1 (t) is input to the drive circuit 9 to control the constant current control circuit 19 so that a desired constant current flows through the constant current control capacitor 18. When the predetermined pulse width is obtained, the switching element 4 is turned off. In the case of the circuit of FIG. 13, both ends of the load 5 are kept at a constant voltage V 0 .
【００４１】このように構成されたパルス電源装置にお
いては、従来例のようにパルス成形回路網を用いないた
め、多数のキャパシタやインダクタンスの代わりに２個
のキャパシタで構成でき、装置が小型で低コストとな
る。また、高電圧部が小型化されるので、絶縁破壊に対
する信頼性が大幅に向上する。また、キャパシタの放電
に伴う出力電圧の低下を補償しているため、小さい容量
のキャパシタの放電においても平坦なパルス波形が得ら
れる。さらに、キャパシタの放電に伴う出力電圧の低下
の補償を連続的に行えるので、実施例１〜７のものに比
較してより平坦なパルス波形が得られる。In the pulse power supply device configured as described above, since the pulse shaping circuit network is not used as in the conventional example, it is possible to configure with two capacitors instead of many capacitors and inductances, and the device is small and low in size. It will be a cost. Further, since the high voltage part is downsized, the reliability against dielectric breakdown is significantly improved. Further, since the output voltage drop due to the discharge of the capacitor is compensated for, a flat pulse waveform can be obtained even when the capacitor having a small capacitance is discharged. Further, since the decrease of the output voltage due to the discharge of the capacitor can be continuously compensated, a flatter pulse waveform can be obtained as compared with those of the first to seventh embodiments.
【００４２】なお、上記実施例１〜７ではサグ補償回路
が負荷の接地側（低電圧側）に直列に接続されており、
サグ補償回路の絶縁構造が容易に達成でき、電源が小型
・軽量・安価になるが、接地構造の都合により高圧側に
配置しても良い。逆に実施例８では高圧側に配置されて
いるが低圧側であっても良い。In the first to seventh embodiments, the sag compensation circuit is connected in series to the ground side (low voltage side) of the load,
Although the insulating structure of the sag compensation circuit can be easily achieved, and the power supply is small, lightweight and inexpensive, it may be arranged on the high voltage side due to the grounding structure. On the contrary, in the eighth embodiment, it is arranged on the high pressure side, but it may be arranged on the low pressure side.
【００４３】また、上記実施例１〜７のサグ補償を段階
的に行う例では基準電圧も段階的に変化させたが、図１
（ａ）に示すように負荷の両端電圧を絶縁アンプ７０を
介して検出して、一定の基準電圧と比較しても良い。Further, in the example of performing the sag compensation stepwise in the first to seventh embodiments, the reference voltage is also stepwise changed.
As shown in (a), the voltage across the load may be detected via the isolation amplifier 70 and compared with a constant reference voltage.
【００４４】また、上記各実施例はすべて正極性パルス
の発生について説明したが、負極正パルスの発生に対し
ても、キャパシタ、ダイオード、トランジスタ等の極性
を逆に配置することにより、類似の構成で実現できる。Although the above-mentioned embodiments have all described the generation of the positive polarity pulse, the polarity of the capacitors, the diodes, the transistors, etc. is arranged in the opposite manner also for the generation of the negative polarity positive pulse, so that a similar configuration is obtained. Can be achieved with.
【００４５】[0045]
【発明の効果】以上のように、請求項１記載の発明によ
れば、充電されたキャパシタと、スイッチング素子と、
負荷と、可変インピーダンスまたは出力可変に構成され
た電源とが直列に接続され、上記スイッチング素子がオ
ンした後の上記キャパシタの放電電圧の低下分であるサ
グ電圧または上記負荷の両端電圧を検出する手段と、上
記検出手段の検出値を基準電圧と比較し上記負荷の両端
電圧を一定に保つように上記インピーダンスまたは電源
の電圧を制御する手段とを備えたので、パルス成形回路
網を用いないため、多数のキャパシタやインダクタンス
の代わりに１個のキャパシタで構成でき、装置が小型で
低コストとなる。また、高電圧部が小型化されるので、
絶縁破壊に対する信頼性が大幅に向上する。さらに、キ
ャパシタの放電に伴う出力電圧の低下を補償しているた
め、小さい容量のキャパシタの放電においても平坦なパ
ルス波形が得られる。As described above, according to the invention described in claim 1, the charged capacitor, the switching element, and
A load and a variable-impedance or variable-output power source are connected in series, and a means for detecting a sag voltage or a voltage across the load, which is a decrease in the discharge voltage of the capacitor after the switching element is turned on. And a means for controlling the impedance or the voltage of the power source so as to keep the voltage across the load constant by comparing the detection value of the detection means with a reference voltage, so that the pulse shaping network is not used, A single capacitor can be used instead of a large number of capacitors and inductances, and the device is small and low cost. Also, since the high voltage part is downsized,
The reliability against dielectric breakdown is greatly improved. Furthermore, since the output voltage drop due to the discharge of the capacitor is compensated, a flat pulse waveform can be obtained even when the capacitor having a small capacitance is discharged.
【００４６】請求項２記載の発明によれば、請求項１の
可変インピーダンスがトランジスタであり、上記トラン
ジスタのゲート電圧を放電電圧の低下に伴って段階的に
上昇させるので、キャパシタの放電に伴う出力電圧の低
下の補償を段階的に行っており、請求項１の効果に加え
て、通常の負帰還回路に比較して安定な高速応答が実現
できる。According to the invention of claim 2, the variable impedance of claim 1 is a transistor, and since the gate voltage of the transistor is increased stepwise as the discharge voltage decreases, the output accompanying the discharge of the capacitor is increased. The voltage drop is compensated stepwise, and in addition to the effect of the first aspect, a stable high-speed response can be realized as compared with a normal negative feedback circuit.
【００４７】請求項３記載の発明によれば、請求項１の
可変インピーダンスが、直列に接続されそれぞれにサグ
補償用スイッチング素子が並列に接続された複数の制御
抵抗であり、放電電圧の低下に伴って上記サグ補償用ス
イッチング素子を順次短絡させるので、可変インピーダ
ンスをトランジスタの代わりに抵抗で構成しており、上
記請求項２の効果に加えて冷却構造が簡略化できると共
に、装置の信頼性が向上する。According to the third aspect of the invention, the variable impedance of the first aspect is a plurality of control resistors connected in series and each of which has a sag compensation switching element connected in parallel. Accordingly, since the sag compensation switching elements are sequentially short-circuited, the variable impedance is configured by a resistor instead of a transistor, and in addition to the effect of claim 2, the cooling structure can be simplified and the reliability of the device can be improved. improves.
【００４８】請求項４記載の発明によれば、請求項１の
可変インピーダンスが、並列に接続されそれぞれにサグ
補償用スイッチング素子が直列に接続された複数の制御
抵抗であり、放電電圧の低下に伴って上記サグ補償用ス
イッチング素子を順次短絡させるかまたは短絡させた後
に開放させるので、各サグ補償用スイッチング素子を同
一電位で駆動でき、上記請求項３の効果に加えて回路構
成が簡単になる。According to the invention of claim 4, the variable impedance of claim 1 is a plurality of control resistors which are connected in parallel and each of which has a sag compensation switching element connected in series. Accordingly, the sag compensation switching elements are sequentially short-circuited or short-circuited and then opened, so that the sag compensation switching elements can be driven at the same potential, and the circuit configuration is simplified in addition to the effect of the third aspect. .
【００４９】請求項５記載の発明によれば、請求項１の
出力可変に構成された電源が、直列に接続されそれぞれ
にサグ補償用スイッチング素子が並列に接続され正に充
電された複数の制御キャパシタであり、放電電圧の低下
に伴って上記サグ補償用スイッチング素子を順次短絡さ
せるので、キャパシタの放電に伴う出力電圧の低下の補
償を正に充電されたキャパシタの切り換えにより行って
おり、電力を損失させる部分が少なく、上記請求項３の
効果に加えて、高効率の電源が実現できる。According to the fifth aspect of the present invention, the plurality of power sources having variable output according to the first aspect are connected in series, the sag compensation switching elements are connected in parallel, and the plurality of positively charged controls are provided. Since it is a capacitor and the switching elements for sag compensation are sequentially short-circuited as the discharge voltage drops, the output voltage drop caused by the discharge of the capacitor is compensated by switching the positively charged capacitor, and the power is reduced. A portion to be lost is small, and in addition to the effect of claim 3, a highly efficient power source can be realized.
【００５０】請求項６記載の発明によれば、請求項１の
出力可変に構成された電源が、並列に接続されそれぞれ
にサグ補償用スイッチング素子が直列に接続され正に充
電された複数の制御キャパシタであり、放電電圧の低下
に伴って上記サグ補償用スイッチング素子を順次短絡さ
せた後に開放させるので、キャパシタを切り替える各サ
グ補償用スイッチング素子を同一電位で駆動でき、上記
請求項５の効果に加えて、回路構成が簡単になる。According to the sixth aspect of the present invention, the plurality of control sources are connected in parallel, the sag compensating switching elements are connected in series, and the positively charged plural power sources are connected in parallel. The sag compensation switching element is a capacitor, and the sag compensation switching elements are sequentially short-circuited and then opened as the discharge voltage decreases. Therefore, the sag compensation switching elements for switching the capacitors can be driven at the same potential, and the effect of claim 5 can be obtained. In addition, the circuit configuration becomes simple.
【００５１】請求項７記載の発明によれば、請求項１の
出力可変に構成された電源が、直列に接続されそれぞれ
にサグ補償用スイッチング素子が接続され負に充電され
た複数の制御キャパシタであり、放電電圧の低下に伴っ
て上記サグ補償用スイッチング素子で上記キャパシタを
負荷電流の通路に順次接続させるので、キャパシタの放
電に伴う出力電圧の低下の補償を負に充電されたキャパ
シタの切り替えにより行っており、請求項５のものに比
較して電力を損失させる部分がさらに少なく、上記請求
項５の効果に加えて、より高効率の電源が実現できる。According to a seventh aspect of the present invention, the power source having variable output according to the first aspect is connected in series, and a plurality of sag compensation switching elements are connected to each of the plurality of negatively charged control capacitors. Yes, as the discharge voltage decreases, the sag compensation switching element sequentially connects the capacitors to the path of the load current.Therefore, compensation of the decrease in output voltage due to discharge of the capacitors is compensated by switching the negatively charged capacitors. In addition to the effect of the fifth aspect, a power source with higher efficiency can be realized, as compared with the fifth aspect.
【００５２】請求項８記載の発明によれば、請求項１の
出力可変に構成された電源が、並列に接続されそれぞれ
にサグ補償用スイッチング素子が直列に接続され負に充
電された複数の制御キャパシタであり、放電電圧の低下
に伴って上記サグ補償用スイッチング素子を順次短絡さ
せるかまたは短絡させた後に開放させるので、キャパシ
タを切り替える各サグ補償用スイッチング素子を同一電
位で駆動でき、上記請求項７の効果に加えて、回路構成
が簡単になる。According to the invention described in claim 8, a plurality of control devices in which the power sources configured to output variable according to claim 1 are connected in parallel and the sag compensating switching elements are connected in series to each of which are negatively charged. The sag compensation switching element is a capacitor, and the sag compensation switching elements are sequentially short-circuited with a decrease in discharge voltage or are opened after short-circuiting, so that each sag compensation switching element can be driven at the same potential. In addition to the effect of 7, the circuit configuration becomes simple.
【００５３】請求項９記載の発明によれば、充電された
第１のキャパシタと、第２のキャパシタと、スイッチン
グ素子と、負荷とが直列に接続され、上記スイッチング
素子がオンした後の上記第１と第２のキャパシタの和の
電圧の低下分を検出する手段と、上記検出手段の検出値
を基準電圧と比較して上記負荷に流れる電流を一定に保
つように上記第２のキャパシタに電流を流す手段とを備
えたので、パルス成形回路網を用いないため、多数のキ
ャパシタやインダクタンスの代わりに２個のキャパシタ
で構成でき、装置が小型で低コストとなる。また、高電
圧部が小型化されるので、絶縁破壊に対する信頼性が大
幅に向上する。また、キャパシタの放電に伴う出力電圧
の低下を補償しているため、小さい容量のキャパシタの
放電においても平坦なパルス波形が得られる。さらに、
キャパシタの放電に伴う出力電圧の低下の補償を連続的
に行えるので、請求項２〜８のものに比較してより平坦
なパルス波形が得られる。According to the invention described in claim 9, the charged first capacitor, the second capacitor, the switching element, and the load are connected in series, and the first capacitor after the switching element is turned on is connected. Means for detecting a decrease in voltage of the sum of the first and second capacitors, and a current flowing through the second capacitor so as to keep the current flowing through the load constant by comparing the detection value of the detection means with a reference voltage. Since the pulse shaping circuit network is not used, the device can be configured with two capacitors instead of a large number of capacitors and inductances, and the device is small in size and low in cost. Further, since the high voltage part is downsized, the reliability against dielectric breakdown is significantly improved. Further, since the output voltage drop due to the discharge of the capacitor is compensated for, a flat pulse waveform can be obtained even when the capacitor having a small capacitance is discharged. further,
Since the compensation of the decrease of the output voltage due to the discharge of the capacitor can be continuously performed, a flatter pulse waveform can be obtained as compared with the second to eighth aspects.
【図１】 本発明の実施例１を説明する全体構成図であ
る。FIG. 1 is an overall configuration diagram illustrating a first embodiment of the present invention.
【図２】 本発明の実施例１の動作を説明する各部の電
圧波形図である。FIG. 2 is a voltage waveform diagram of each part for explaining the operation of the first embodiment of the present invention.
【図３】 本発明の実施例１の動作を説明する制御部の
電圧波形図である。FIG. 3 is a voltage waveform diagram of the control unit for explaining the operation of the first embodiment of the present invention.
【図４】 本発明の実施例１の変形例の動作を説明する
各部の電圧波形図である。FIG. 4 is a voltage waveform diagram of each part for explaining the operation of the modified example of the first exemplary embodiment of the present invention.
【図５】 本発明の実施例２を説明する構成図である。FIG. 5 is a configuration diagram illustrating a second embodiment of the present invention.
【図６】 本発明の実施例３を説明する構成図である。FIG. 6 is a configuration diagram illustrating a third embodiment of the present invention.
【図７】 本発明の実施例２〜５の動作を説明する制御
部の電圧波形図である。FIG. 7 is a voltage waveform diagram of the control unit for explaining the operation of Examples 2 to 5 of the present invention.
【図８】 本発明の実施例４を説明する構成図である。FIG. 8 is a configuration diagram illustrating a fourth embodiment of the present invention.
【図９】 本発明の実施例５を説明する構成図である。FIG. 9 is a configuration diagram illustrating a fifth embodiment of the present invention.
【図１０】 本発明の実施例６を説明する構成図であ
る。FIG. 10 is a configuration diagram illustrating a sixth embodiment of the present invention.
【図１１】 本発明の実施例６および７の動作を説明す
る各部の電圧波形図である。FIG. 11 is a voltage waveform diagram of each part for explaining the operation of Examples 6 and 7 of the present invention.
【図１２】 本発明の実施例７を説明する構成図であ
る。FIG. 12 is a configuration diagram illustrating a seventh embodiment of the present invention.
【図１３】 本発明の実施例８を説明する構成図であ
る。FIG. 13 is a configuration diagram illustrating an eighth embodiment of the present invention.
【図１４】 従来例１を説明する構成図である。FIG. 14 is a configuration diagram illustrating a first conventional example.
【図１５】 従来例２を説明する構成図である。FIG. 15 is a configuration diagram illustrating a second conventional example.
【図１６】 従来例３を説明する構成図である。FIG. 16 is a configuration diagram illustrating a third conventional example.
１ 直流電源、 ２ 充電リアクトル、 ３ 放電キャ
パシタ、 ４ スイッチング素子、 ５ 負荷、 ６
分圧抵抗器、 ７ 誤差アンプ、 ７０ 絶縁アンプ、
８ 基準電圧、 ９ ドライブ回路、 １０ トラン
ジスタ、 １１制御抵抗、 １２ サグ補償用スイッチ
ング素子、 １３ 制御キャパシタ、１４ 短絡防止用
ダイオード、 １５ 放電抵抗、 １６ 充電用電源、
１７ 補償用直流電源、 １８ 定電流制御用キャパ
シタ、 １９ 定電流制御回路、 ２０ 誘導電圧調整
器、 ２１ 変圧器／整流器、 ２２ 充電回路、２３
De‘Qing回路、 ２４ シャントダイオード、 ２５
パルス成型回路網、 ２６ パルストランス、 ２７
クライストロン、 ２８ コンバータ、２９ インバ
ータ、 ３０ 充電抵抗、 ３１ 放電防止用ダイオー
ド、 ３２平滑用キャパシタ、 ３３ バイアス電源。1 DC power supply, 2 charging reactor, 3 discharging capacitor, 4 switching element, 5 load, 6
Voltage divider, 7 error amplifier, 70 isolation amplifier,
8 reference voltage, 9 drive circuit, 10 transistor, 11 control resistance, 12 sag compensation switching element, 13 control capacitor, 14 short circuit prevention diode, 15 discharge resistance, 16 charging power supply,
17 DC power supply for compensation, 18 Capacitor for constant current control, 19 Constant current control circuit, 20 Induction voltage regulator, 21 Transformer / rectifier, 22 Charging circuit, 23
De'Qing circuit, 24 shunt diode, 25
Pulse shaping circuit network, 26 pulse transformer, 27
Klystron, 28 converter, 29 inverter, 30 charging resistor, 31 discharge prevention diode, 32 smoothing capacitor, 33 bias power supply.
Claims (9)
素子と、負荷と、可変インピーダンスまたは出力可変に
構成された電源とが直列に接続され、上記スイッチング
素子がオンした後の上記キャパシタの放電電圧の低下分
であるサグ電圧または上記負荷の両端電圧を検出する手
段と、上記検出手段の検出値を基準電圧と比較し上記負
荷の両端電圧を一定に保つように上記インピーダンスま
たは電源の電圧を制御する手段とを備えたパルス電源装
置。1. A charged capacitor, a switching element, a load, and a power source configured to have variable impedance or variable output are connected in series, and the discharge voltage of the capacitor decreases after the switching element is turned on. Means for detecting the sag voltage or the voltage across the load, and means for comparing the detected value of the detection means with a reference voltage and controlling the impedance or the voltage of the power source so as to keep the voltage across the load constant. And a pulse power supply device.
り、上記トランジスタのゲート電圧を放電電圧の低下に
伴って段階的に上昇させる請求項１記載のパルス電源装
置。2. The pulse power supply device according to claim 1, wherein the variable impedance is a transistor, and the gate voltage of the transistor is increased stepwise as the discharge voltage decreases.
それぞれにサグ補償用スイッチング素子が並列に接続さ
れた複数の制御抵抗であり、放電電圧の低下に伴って上
記サグ補償用スイッチング素子を順次短絡させる請求項
１記載のパルス電源装置。3. The variable impedance is a plurality of control resistors connected in series, and each sag compensation switching element is connected in parallel, and the sag compensation switching element is sequentially short-circuited as the discharge voltage decreases. The pulse power supply device according to claim 1.
それぞれにサグ補償用スイッチング素子が直列に接続さ
れた複数の制御抵抗であり、放電電圧の低下に伴って上
記サグ補償用スイッチング素子を順次短絡させるかまた
は短絡させた後に開放させる請求項１記載のパルス電源
装置。4. The variable impedance is a plurality of control resistors connected in parallel and each of which has a sag compensation switching element connected in series, and the sag compensation switching element is sequentially short-circuited as the discharge voltage decreases. The pulse power supply device according to claim 1, wherein the pulse power supply device is opened after being short-circuited or short-circuited.
続されそれぞれにサグ補償用スイッチング素子が並列に
接続され正に充電された複数の制御キャパシタであり、
放電電圧の低下に伴って上記サグ補償用スイッチング素
子を順次短絡させる請求項１記載のパルス電源装置。5. A plurality of control capacitors, in which a power source configured to output variable is connected in series and a sag compensating switching element is connected in parallel to each of the plurality of positively charged capacitors.
The pulse power supply device according to claim 1, wherein the sag compensation switching elements are sequentially short-circuited as the discharge voltage decreases.
続されそれぞれにサグ補償用スイッチング素子が直列に
接続され正に充電された複数の制御キャパシタであり、
放電電圧の低下に伴って上記サグ補償用スイッチング素
子を順次短絡させた後に開放させる請求項１記載のパル
ス電源装置。6. A plurality of control capacitors in which a power source configured to output variable is connected in parallel and a sag compensation switching element is connected in series to each of the positively charged control capacitors,
2. The pulse power supply device according to claim 1, wherein the sag compensation switching elements are sequentially short-circuited and then opened as the discharge voltage decreases.
続されそれぞれにサグ補償用スイッチング素子が接続さ
れ負に充電された複数の制御キャパシタであり、放電電
圧の低下に伴って上記サグ補償用スイッチング素子で上
記キャパシタを負荷電流の通路に順次接続させる請求項
１記載のパルス電源装置。7. A plurality of control capacitors in which a power source configured to output variable is connected in series and a sag compensating switching element is connected to each of them and negatively charged, and the sag compensating is performed as the discharge voltage decreases. 2. The pulse power supply device according to claim 1, wherein the capacitors are sequentially connected to the path of the load current by a switching element for use.
続されそれぞれにサグ補償用スイッチング素子が直列に
接続され負に充電された複数の制御キャパシタであり、
放電電圧の低下に伴って上記サグ補償用スイッチング素
子を順次短絡させるかまたは短絡させた後に開放させる
請求項１記載のパルス電源装置。8. A plurality of control capacitors in which a power source configured to output variable is connected in parallel, and each of which has a sag compensation switching element connected in series, and which is negatively charged.
2. The pulse power supply device according to claim 1, wherein the sag compensating switching elements are short-circuited sequentially or short-circuited after the discharge voltage decreases, and then opened.
キャパシタと、スイッチング素子と、負荷とが直列に接
続され、上記スイッチング素子がオンした後の上記第１
と第２のキャパシタの和の電圧の低下分を検出する手段
と、上記検出手段の検出値を基準電圧と比較して上記負
荷に流れる電流を一定に保つように上記第２のキャパシ
タに電流を流す手段とを備えたパルス電源装置。9. A charged first capacitor, a second capacitor, a switching element, and a load are connected in series, and the first element after the switching element is turned on.
And a means for detecting a decrease in the sum voltage of the second capacitor, and a current to the second capacitor so as to keep the current flowing through the load constant by comparing the detection value of the detection means with a reference voltage. And a pulse power supply device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32540194A JP3303573B2 (en) | 1994-12-27 | 1994-12-27 | Pulse power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32540194A JP3303573B2 (en) | 1994-12-27 | 1994-12-27 | Pulse power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08182349A true JPH08182349A (en) | 1996-07-12 |
| JP3303573B2 JP3303573B2 (en) | 2002-07-22 |
Family
ID=18176439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32540194A Expired - Fee Related JP3303573B2 (en) | 1994-12-27 | 1994-12-27 | Pulse power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3303573B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003028997A (en) * | 2001-07-18 | 2003-01-29 | National Institute Of Advanced Industrial & Technology | Pulse power source |
| JP2006094681A (en) * | 2004-09-27 | 2006-04-06 | Toshiba Mitsubishi-Electric Industrial System Corp | High voltage pulse power supply |
| JP2009284664A (en) * | 2008-05-22 | 2009-12-03 | Yokohama Rubber Co Ltd:The | Power output circuit for electrostatic induction conversion device |
| JP2013061918A (en) * | 2011-09-15 | 2013-04-04 | Renesas Electronics Corp | Semiconductor device |
| WO2018038398A1 (en) * | 2016-08-25 | 2018-03-01 | 한국전기연구원 | Pulse power compensation device and high-voltage pulse power supply system comprising same |
| CN115494420A (en) * | 2022-10-21 | 2022-12-20 | 哈尔滨工业大学 | Method for testing output performance of high-power pulse power supply |
| CN117674395A (en) * | 2024-01-31 | 2024-03-08 | 湖南北顺源智能科技有限公司 | Multi-module serial high-voltage direct-current shore-based power redundancy switching method |
-
1994
- 1994-12-27 JP JP32540194A patent/JP3303573B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003028997A (en) * | 2001-07-18 | 2003-01-29 | National Institute Of Advanced Industrial & Technology | Pulse power source |
| JP2006094681A (en) * | 2004-09-27 | 2006-04-06 | Toshiba Mitsubishi-Electric Industrial System Corp | High voltage pulse power supply |
| JP2009284664A (en) * | 2008-05-22 | 2009-12-03 | Yokohama Rubber Co Ltd:The | Power output circuit for electrostatic induction conversion device |
| JP2013061918A (en) * | 2011-09-15 | 2013-04-04 | Renesas Electronics Corp | Semiconductor device |
| WO2018038398A1 (en) * | 2016-08-25 | 2018-03-01 | 한국전기연구원 | Pulse power compensation device and high-voltage pulse power supply system comprising same |
| CN115494420A (en) * | 2022-10-21 | 2022-12-20 | 哈尔滨工业大学 | Method for testing output performance of high-power pulse power supply |
| CN115494420B (en) * | 2022-10-21 | 2023-04-18 | 哈尔滨工业大学 | Method for testing output performance of high-power pulse power supply |
| CN117674395A (en) * | 2024-01-31 | 2024-03-08 | 湖南北顺源智能科技有限公司 | Multi-module serial high-voltage direct-current shore-based power redundancy switching method |
| CN117674395B (en) * | 2024-01-31 | 2024-04-16 | 湖南北顺源智能科技有限公司 | Multi-module serial high-voltage direct-current shore-based power redundancy switching method |
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|---|---|
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