JPH0783244B2 - Pulse circuit - Google Patents
Pulse circuitInfo
- Publication number
- JPH0783244B2 JPH0783244B2 JP61005855A JP585586A JPH0783244B2 JP H0783244 B2 JPH0783244 B2 JP H0783244B2 JP 61005855 A JP61005855 A JP 61005855A JP 585586 A JP585586 A JP 585586A JP H0783244 B2 JPH0783244 B2 JP H0783244B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- waveform
- differential
- absolute value
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Digital Magnetic Recording (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は磁気ディスク装置における再生信号の復調回路
であって、差動微分回路を利用しその平衡な微分出力に
対して電位差を与え、比較回路によりパルス化を行うこ
とにより、部品点数を少なく、かつ高速信号の処理を可
能にするものである。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is a reproduction signal demodulation circuit in a magnetic disk device, wherein a differential differentiation circuit is used to apply a potential difference to the balanced differential output, and a pulse is converted by a comparison circuit. By doing so, the number of parts can be reduced and high-speed signal processing can be performed.
本発明は磁気ディスク装置において、再生信号の復調の
ためのパルス化回路に関する。The present invention relates to a pulse conversion circuit for demodulating a reproduction signal in a magnetic disk device.
近年、磁気ディスク装置に対しては記録容量の拡大、デ
ータ転送速度の高速化等が要求されているが、これに伴
い再生信号のパルス化回路に対しても信号処理の高速
化、高精度化が要求されている。このため、再生信号の
高速復調処理を高精度に、かつ安価に実現できるパルス
化回路の開発が要望されている。In recent years, magnetic disk devices have been required to have an increased recording capacity and an increased data transfer rate, and along with this, the signal processing speed and accuracy of the reproduction signal pulsing circuit have also been improved. Is required. Therefore, there is a demand for the development of a pulse conversion circuit that can realize high-speed demodulation processing of a reproduced signal with high accuracy and at low cost.
第４図は従来のパルス化回路の構成図を示す。図におい
て、１は再生（アナログ入力）信号のピーク点を検出す
るためのピーク検出回路で、アナログ入力信号を微分す
る微分回路11とその出力の零クロス点を検出する比較回
路12とから構成されている。２はフローティングスライ
ス回路であって、ピークホールド回路21と比較回路22と
から構成され、次に述べる固定スライス回路と同様に所
要のスライスレベル以下の振幅の信号をパルスとして検
出しない機能を持つ。また、正のピークの次には必ず負
のピークを検出（あるいはその逆）する様な順序回路を
構成している。FIG. 4 shows a configuration diagram of a conventional pulse conversion circuit. In the figure, reference numeral 1 is a peak detection circuit for detecting a peak point of a reproduction (analog input) signal, which is composed of a differentiation circuit 11 for differentiating an analog input signal and a comparison circuit 12 for detecting a zero cross point of its output. ing. Reference numeral 2 denotes a floating slice circuit, which is composed of a peak hold circuit 21 and a comparison circuit 22 and has a function of not detecting a signal having an amplitude below a required slice level as a pulse, like the fixed slice circuit described below. In addition, a sequential circuit is constructed so that a negative peak is always detected after the positive peak (or vice versa).
３は固定スライス回路であって、アナログ入力信号の中
で所要のスライスレベル以上の振幅を持つピークのみが
意味を持つためのゲートパルスを形成する回路である。
データパルスは上記の３種類の回路出力を４の論理回路
で処理することにより得られる。Reference numeral 3 denotes a fixed slice circuit, which is a circuit that forms a gate pulse so that only a peak having an amplitude of a required slice level or more has a meaning in an analog input signal.
The data pulse is obtained by processing the above three types of circuit outputs by four logic circuits.
従来のパルス化回路では、前述のように回路が複雑で部
品点数が多くなっている。また、フローティングスライ
ス回路２に用いられるピークホールド回路21では、基本
的にはコンデンサの充放電を行っているため高速動作に
問題がある。In the conventional pulse circuit, the circuit is complicated and the number of parts is large as described above. Further, the peak hold circuit 21 used in the floating slice circuit 2 has a problem in high-speed operation because the capacitor is basically charged and discharged.
本発明は上記従来の欠点に鑑みて創作されたもので、構
成回路の簡易化と高速動作に対応可能なパルス化回路の
提供を目的とする。The present invention was created in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a pulsing circuit capable of simplifying a constituent circuit and operating at high speed.
本発明のパルス化回路は第１図に示すように、アナログ
入力信号をパルス化するための回路であって、該アナロ
グ入力信号の絶対値波形を得る絶対値回路（51）と、前
記絶対値波形にオフセットを与えて所要レベル以上の波
形を得るレベルスライス回路（52）と、前記レベルスラ
イス回路（52）の出力を微分すると共に、該微分波形と
その反転波形とを平衡出力する微分回路（53）とからな
る差動微分回路（５）と、該差動微分回路（５）の平衡
出力波形のそれぞれに正負のバイアス電圧を賦与するバ
イアス回路（６）と、該バイアス回路（６）の平衡出力
を比較し、当該アナログ入力信号に対応するパルスを出
力する比較回路（７）とから構成されたことを特徴とす
る。As shown in FIG. 1, the pulsing circuit of the present invention is a circuit for pulsing an analog input signal, and includes an absolute value circuit (51) for obtaining an absolute value waveform of the analog input signal and the absolute value circuit. A level slicing circuit (52) that gives a waveform of a required level or more by giving an offset to the waveform, and a differentiation circuit that differentiates the output of the level slicing circuit (52) and balance-outputs the differential waveform and its inverted waveform ( 53), a bias circuit (6) for applying positive and negative bias voltages to the balanced output waveforms of the differential differentiation circuit (5), and the bias circuit (6). And a comparator circuit (7) for comparing the balanced outputs and outputting a pulse corresponding to the analog input signal.
差動微分回路５では第２図に示すようにアナログ入力信
号波形の絶対値波形Ｂに対してレベルスライスを行い、
このスライスレベル以上の振幅を持つ部分について微分
を行っている。In the differential differentiation circuit 5, level slicing is performed on the absolute value waveform B of the analog input signal waveform as shown in FIG.
Differentiation is performed on a portion having an amplitude equal to or higher than the slice level.
このように絶対値波形Ｂについて微分を行うためアナロ
グ入力信号のピーク点付近の微分波形の傾きが正のピー
ク，負のピーク共に同じとなり、直流成分遮断用コンデ
ンサC2,C3とバイアス回路６によって波形Ｄのようにそ
の零レベル電位に電位差を与えることにより比較回路７
でパルス化を行うことができる。Since the absolute value waveform B is differentiated in this way, the slope of the differential waveform near the peak point of the analog input signal is the same for both the positive and negative peaks, and the DC component blocking capacitors C 2 and C 3 and the bias circuit 6 are the same. By applying a potential difference to the zero level potential as shown by the waveform D, the comparison circuit 7
Can be pulsed.
しかも従来例で述べたピークホールド回路21の充放電用
のコンデンサを含まないため高速化に対応可能でかつ回
路も簡単になる。Moreover, since the charging / discharging capacitor of the peak hold circuit 21 described in the conventional example is not included, it is possible to cope with high speed and the circuit becomes simple.
以下本発明の実施例を図面によって詳述する。なお、構
成、動作の説明を理解し易くするために全図を通じて同
一部分には同一符号を付してその重複説明を省略する。Embodiments of the present invention will be described in detail below with reference to the drawings. In addition, in order to make the description of the configuration and the operation easy to understand, the same reference numerals are given to the same portions throughout the drawings, and the duplicated description will be omitted.
第１図は本発明のパルス化回路の構成図、第２図は第１
図各部の波形図を示し、以下第２図を参照しながら第１
図の説明を行う。FIG. 1 is a block diagram of a pulse conversion circuit of the present invention, and FIG.
Figure 1 shows the waveform diagram of each part.
The figure will be described.
５は差動微分回路であって、絶対値回路51とレベルスラ
イス回路52と微分回路53とから構成されている。絶対値
回路51は磁気ディスク装置の再生信号すなわちアナログ
入力信号Ａの波形（データ“1"に対して正または負側に
ピークを有する）を絶対値波形Ｂのように負側波形を正
側に反転形成する。次に外部から所要のスライスレベル
電圧をレベルスライス回路52に印加することにより、そ
のスライスレベル以上の波形を抽出する。Reference numeral 5 denotes a differential differentiation circuit, which is composed of an absolute value circuit 51, a level slice circuit 52, and a differentiation circuit 53. The absolute value circuit 51 changes the waveform of the reproduction signal of the magnetic disk device, that is, the waveform of the analog input signal A (having a peak on the positive or negative side with respect to the data "1") to the negative side waveform on the positive side like the absolute value waveform B. Inversion is formed. Next, a required slice level voltage is externally applied to the level slice circuit 52 to extract a waveform above the slice level.
次に微分回路53を用いて前記レベルスライス回路52の出
力を微分すると共に、波形Ｃに示すように該微分波形
（実線表示）とその反転波形（破線表示）とを平衡出力
させる。しかして、該差動微分回路５の平衡出力波形Ｃ
のそれぞれを直流成分遮断用コンデンサC2,C3を介して
バイアス回路６に入力する。Next, the output of the level slice circuit 52 is differentiated by using the differentiating circuit 53, and the differentiated waveform (displayed by a solid line) and its inverted waveform (displayed by a broken line) are balanced-outputted as shown by the waveform C. Then, the balanced output waveform C of the differential differentiation circuit 5
Are input to the bias circuit 6 via the DC component blocking capacitors C 2 and C 3 .
バイアス回路６は波形Ｄに示すように直流成分を遮断さ
れた平衡出力波形Ｃのそれぞれに電位差を与え、この波
形Ｄを比較回路７で比較することにより、破線で示す側
の波形が実線で示す側の波形より大きくなった時間だけ
比較器７は所定レベルの信号（パルス）を出力する。The bias circuit 6 gives a potential difference to each of the balanced output waveforms C in which the DC component is blocked as shown in the waveform D, and the waveform D on the side indicated by the broken line is indicated by the solid line by comparing the waveform D with the comparison circuit 7. The comparator 7 outputs a signal (pulse) of a predetermined level only for the time when it becomes larger than the waveform on the side.
第３図は本発明の具体例回路図を示す。図において、絶
対値回路51はトランジスタQ1とQ2とから構成され、レベ
ルスライス回路52はトランジスタQ3とQ4およびその中間
に印加されるスライスレベル電圧の供給回路から構成さ
れている。微分回路53はコンデンサC1と抵抗R3とからな
り、抵抗R1とR2はそれぞれ差動微分回路の出力負荷抵抗
となり、その時定数はC1R3で決定される。FIG. 3 shows a specific circuit diagram of the present invention. In the figure, an absolute value circuit 51 is composed of transistors Q 1 and Q 2, and a level slice circuit 52 is composed of transistors Q 3 and Q 4 and a supply circuit of a slice level voltage applied in the middle thereof. The differentiating circuit 53 is composed of a capacitor C 1 and a resistor R 3 , and the resistors R 1 and R 2 are output load resistances of the differential differentiating circuit, and the time constant is determined by C 1 R 3 .
VcとVeはそれぞれ供給電源の＋側と−側を示し、I1〜I4
はそれぞれ電流源（例えばカレントミラー回路のような
定電流回路）を示す。差動微分回路５の出力はレベルス
ライス回路52の出力を微分した微分波形とその反転波形
との平衡波形が出力され、直流遮断用コンデンサC2とC3
を介して平衡型のバイアス回路６に入力される。Vc and Ve indicate the positive and negative sides of the power supply, respectively, and I 1 to I 4
Are current sources (eg, constant current circuits such as current mirror circuits). The output of the differential differentiating circuit 5 is the balanced waveform of the differential waveform obtained by differentiating the output of the level slice circuit 52 and its inverted waveform, and the DC blocking capacitors C 2 and C 3
Is input to the balanced type bias circuit 6 via.
バイアス回路６は電流源I3とI4およびバイアス抵抗R4と
R5ならびに可変抵抗Rvとから構成され、直流成分を遮断
された差動微分回路５の出力平衡波形にそれぞれ正側と
負側のバイアス電圧を賦与し、比較回路７によりパルス
化される。Bias circuit 6 includes current sources I 3 and I 4 and bias resistor R 4
A bias voltage on the positive side and a bias voltage on the negative side are respectively applied to the output balanced waveform of the differential differentiating circuit 5 which is composed of R 5 and the variable resistor Rv and whose DC component is blocked, and is pulsed by the comparison circuit 7.
この具体例回路によればパルス化回路の基本構成がトラ
ンジスタ４個と比較器１個で構成できるため、高速なア
ナログ信号の処理を高精度、かつ安価に実現できる。According to this specific example circuit, since the basic configuration of the pulse conversion circuit can be configured with four transistors and one comparator, high-speed analog signal processing can be realized with high accuracy and at low cost.
以上詳細に説明したように本発明のパルス化回路によれ
ば、部品点数を大幅に削減することができ、またその構
成要素としてコンデンサの充放電を利用することがない
ので、高速信号の処理を高精度、かつ安価に実現するパ
ルス化回路を提供できる。As described in detail above, according to the pulsing circuit of the present invention, the number of parts can be significantly reduced, and since charging / discharging of a capacitor is not used as its constituent element, high-speed signal processing can be performed. A pulsed circuit that can be realized with high accuracy and at low cost can be provided.
第１図は本発明のパルス化回路の構成図、 第２図は第１図各部の波形図、 第３図は本発明の具体例回路図、 第４図は従来のパルス化回路の構成図を示す。 図において、５は差動微分回路、６はバイアス回路、７
は比較回路、51は絶対値回路、52はレベルスライス回
路、53は微分回路をそれぞれ示す。FIG. 1 is a block diagram of the pulse circuit of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a circuit diagram of a specific example of the present invention, and FIG. 4 is a block diagram of a conventional pulse circuit. Indicates. In the figure, 5 is a differential differentiation circuit, 6 is a bias circuit, and 7
Is a comparison circuit, 51 is an absolute value circuit, 52 is a level slice circuit, and 53 is a differentiation circuit.
Claims (1)
路であって、 該アナログ入力信号の絶対値波形を得る絶対値回路（5
1）と、 前記絶対値波形にオフセットを与えて所要レベル以上の
波形を得るレベルスライス回路（52）と、 該レベルスライス回路（52）の出力を微分すると共に、
該微分波形とその反転波形とを平衡出力する微分回路
（53）とからなる差動微分回路（５）と、 該差動微分回路（５）の平衡出力波形のそれぞれに正，
負のバイアス電圧を賦与するバイアス回路（６）と、 該バイアス回路（６）の平衡出力を比較し、前記アナロ
グ入力信号に対応するパルスを出力する比較回路（７）
とから構成されたことを特徴とするパルス化回路。1. A circuit for pulsing an analog input signal, the absolute value circuit (5) obtaining an absolute value waveform of the analog input signal.
1), a level slice circuit (52) for obtaining a waveform of a required level or more by applying an offset to the absolute value waveform, and differentiating the output of the level slice circuit (52),
A differential differentiating circuit (5) comprising a differential circuit (53) for balanced output of the differential waveform and its inverted waveform, and a positive output for a balanced output waveform of the differential differentiating circuit (5),
A bias circuit (6) that applies a negative bias voltage and a comparator circuit (7) that compares the balanced output of the bias circuit (6) and outputs a pulse corresponding to the analog input signal.
A pulsing circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61005855A JPH0783244B2 (en) | 1986-01-13 | 1986-01-13 | Pulse circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61005855A JPH0783244B2 (en) | 1986-01-13 | 1986-01-13 | Pulse circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62163416A JPS62163416A (en) | 1987-07-20 |
| JPH0783244B2 true JPH0783244B2 (en) | 1995-09-06 |
Family
ID=11622593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61005855A Expired - Lifetime JPH0783244B2 (en) | 1986-01-13 | 1986-01-13 | Pulse circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783244B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0727696Y2 (en) * | 1987-08-07 | 1995-06-21 | 日本電気株式会社 | Peak detection circuit |
| JP2795647B2 (en) * | 1988-03-16 | 1998-09-10 | 富士通株式会社 | Differentiating circuit and magnetic recording / reproducing circuit using the differentiating circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249618B2 (en) * | 1973-06-04 | 1977-12-19 | ||
| JPS5318376A (en) * | 1976-08-04 | 1978-02-20 | Fujitsu Ltd | Receiving circuit |
-
1986
- 1986-01-13 JP JP61005855A patent/JPH0783244B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62163416A (en) | 1987-07-20 |
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