JPH077843B2 - Amorphous multi-element semiconductor device - Google Patents
Amorphous multi-element semiconductor deviceInfo
- Publication number
- JPH077843B2 JPH077843B2 JP3198724A JP19872491A JPH077843B2 JP H077843 B2 JPH077843 B2 JP H077843B2 JP 3198724 A JP3198724 A JP 3198724A JP 19872491 A JP19872491 A JP 19872491A JP H077843 B2 JPH077843 B2 JP H077843B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor
- amorphous
- electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Carbon And Carbon Compounds (AREA)
- Photovoltaic Devices (AREA)
- Glass Compositions (AREA)
- Silicon Compounds (AREA)
- Physical Or Chemical Processes And Apparatus (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はアモルフアス多元系半導
体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to amorphous semiconductor devices.
【０００２】[0002]
【従来の技術】太陽電池や光検出器のような光電素子及
び装置は太陽光線を直接電気エネルギに変換することが
できるが、この種装置の最大の問題として、他の電気エ
ネルギ発生手段と比較して発電費用が極めて大きいこと
が言われている。その主な原因は、装置の主体を構成す
る半導体材料の利用効率が低いこと、更には斯る材料を
製造するに要するエネルギが多いことにある。2. Description of the Related Art Photovoltaic devices and devices such as solar cells and photodetectors can directly convert sunlight into electric energy, but the biggest problem with such devices is that they are compared with other electric energy generating means. It is said that the power generation cost is extremely high. The main reason for this is that the utilization efficiency of the semiconductor material that constitutes the main body of the device is low, and moreover, much energy is required to manufacture such material.
【０００３】最近この欠点を解決する可能性のある技術
として、上記半導体材料に非晶質シリコンを使用するこ
とが提案された。即ち、非晶質シリコンはシランやフロ
ルシリコンなどのシリコン化合物雰囲気中でのグロー放
電によつて安価かつ大量に形成することができ、その場
合の非晶質シリコン（以下ＧＤ−ａＳｉと略記する）で
は、禁止帯の幅中の平均局在状態密度が１０17cm-3以下
と小さく、結晶シリコンと同じ様にｐ型、ｎ型の不純物
制御が可能となるのである。Recently, it has been proposed to use amorphous silicon as the semiconductor material as a technique that may solve this drawback. That is, amorphous silicon can be formed inexpensively and in large quantities by glow discharge in a silicon compound atmosphere such as silane or fluorosilicon, and amorphous silicon in that case (hereinafter abbreviated as GD-aSi). Then, the average localized density of states in the width of the band gap is as small as 10 17 cm −3 or less, and p-type and n-type impurities can be controlled in the same manner as in crystalline silicon.
【０００４】ＧＤ−ａＳｉを用いた典型的な従来の太陽
電池は、可視光を透過するガラス基板上に透明電極を形
成し、該透明電極上にＧＤ−ａＳｉのｐ型層、ＧＤ−ａ
Ｓｉのノンドープ（不純物無添加）層及びＧＤ−ａＳｉ
のｎ型層を順次形成し該ｎ型層上にオーミツクコンタク
ト用電極を設けてなるものである。上記太陽電池におい
て、ガラス基板及び透明電極を介して光がＧＤ−ａＳｉ
からなるｐ型層、ノンドープ層及びｎ型層に入ると、主
にノンドープ層において自由状態の電子及び／又は正孔
が発生し、これらは上記各層の作るｐｉｎ接合電界によ
り引かれて移動した後透明電極やオーミツクコンタクト
用電極に集められ両電極間に電圧が発生する。In a typical conventional solar cell using GD-aSi, a transparent electrode is formed on a glass substrate which transmits visible light, and a p-type layer of GD-aSi, GD-a, is formed on the transparent electrode.
Si non-doped (impurity-free) layer and GD-aSi
The n-type layer is sequentially formed, and the ohmic contact electrode is provided on the n-type layer. In the solar cell, light is emitted from the GD-aSi through the glass substrate and the transparent electrode.
When entering the p-type layer, the non-doped layer and the n-type layer, the electrons and / or holes in the free state are mainly generated in the non-doped layer, and these are attracted and moved by the pin junction electric field created by each layer. A voltage is generated between both electrodes by being collected by the transparent electrode and the ohmic contact electrode.
【０００５】ところが、以下に述べる理由によつて、エ
ネルギー変換効率は制約を受けており、各方面でこれら
の改善を目指して活発な研究が行われている。 (1) 光の入射側のドーピング層（上記の場合はｐ層）
で吸収された光は有効なキヤリアーにならず、ロスとな
る。 (2) 有効なキヤリアーを発生するノンドープ層のエネ
ルギーギヤツプが約１．８ｅＶであり、長波長の光を利
用できない。 (3) 光の入射側と反対の層のドーピング層（上記の場
合はｎ層）で吸収された光もロスとなり、裏面電極で反
射され、ノンドープ層に導入される光が少なくなる。 (4) 上記の一例とは別に、広い波長範囲の太陽スペク
トルを有効に利用する為、多層構造の太陽電池が提案さ
れているが、それぞれの層に適したアモルフアス材料は
一部しか見い出されていない。However, the energy conversion efficiency is limited for the reasons described below, and active research is being conducted in various fields with the aim of improving these. (1) Doping layer on the light incident side (p layer in the above case)
The light absorbed at does not become an effective carrier and becomes a loss. (2) The energy gap of the non-doped layer that generates an effective carrier is about 1.8 eV, and long wavelength light cannot be used. (3) Light absorbed in the doping layer (n layer in the above case) opposite to the light incident side also becomes a loss, and less light is reflected by the back electrode and introduced into the non-doped layer. (4) In addition to the above example, a solar cell with a multilayer structure has been proposed in order to effectively use the solar spectrum in a wide wavelength range, but only some amorphous materials suitable for each layer have been found. Absent.
【０００６】特に上記(1) の理由によつて小さな短絡電
流（Jsc)しか得られず、さらに付随的な現象ではある
が、開放電圧（Voc)も０．８ボルトと低い値しか示さな
かつた。これに対して本発明者等は、特願昭５６−１２
３１３号、特願昭５６−２２６９０号、特願昭５６−６
６６８９号に示すようなワイドギヤツプでｐ又はｎ型に
価電子制御できる非晶質半導体を発明し、さらに非晶質
シリコンとヘテロ接合ｐｉｎを形成することにより大き
いＪｓｃとＶｏｃが得られることを見い出した。Due to the reason (1) above, in particular, a small short-circuit current (Jsc) is obtained, and although it is an incidental phenomenon, the open-circuit voltage (Voc) is as low as 0.8 V. . On the other hand, the inventors of the present invention filed Japanese Patent Application No. 56-12.
313, Japanese Patent Application No. 56-22690, Japanese Patent Application No. 56-6
Inventing an amorphous semiconductor capable of controlling valence electrons to p-type or n-type with a wide gearup as shown in No. 6689, and further finding that larger Jsc and Voc can be obtained by forming a heterojunction pin with amorphous silicon. .
【０００７】[0007]
【発明が解決しようとする課題】本発明の課題は、上記
(1)〜(4)のすべてを満足させ得る非晶質材料を構成要
素として持つアモルフアス多元系半導体素子を提供する
ことにある。The problems of the present invention are as described above.
An object of the present invention is to provide an amorphous multi-element semiconductor device having an amorphous material capable of satisfying all of (1) to (4) as a constituent element.
【０００８】[0008]
【課題を解決するための手段】即ち、本発明はＣ、Ｎ、
Ｏ及びＳよりなる元素と、Ｈ並びにハロゲンよりなる元
素の群から選ばれた１種以上の元素、及びＳｉ、Ｇｅ、
Ｓｎよりなる元素の群から選ばれた１種以上の元素とか
らなるアモルフアス多元系半導体を構成要素として持つ
グレーデツド型半導体素子を１つ以上含むタンデムおよ
び／またはマルチスタツクド半導体素子を内容とする。That is, the present invention relates to C, N,
One or more elements selected from the group of elements consisting of O and S, H and halogen, and Si, Ge,
A tandem and / or multi-stacked semiconductor device including at least one graded semiconductor device having as a constituent an amorphous multi-element semiconductor composed of one or more elements selected from the group of elements consisting of Sn.
【０００９】[0009]
【実施例】以下に、その詳細を説明する。本発明に用い
るアモルフアス多元系半導体はＣ、Ｎ、Ｏ及びＳとＨ、
ハロゲンからなる群から選ばれた１種以上と、Ｓｉ、Ｇ
ｅ、Ｓｎからなる群から選ばれた１種以上とから適宜組
み合わされたガス状の或はガス化せしめた化合物をグロ
ー放電分解することによつて得られる。また、上記から
適宜組み合わされた固体化合物をターゲツトとして、ス
パツタするか、もしくはＣ、Ｎ、Ｏ、Ｓ、及びＨ、ハロ
ゲンから適宜組み合わされた気体の存在下で前記ターゲ
ツトをスパツタすることによつても得られる。前記グロ
ー放電法及びスパツタ法を実施する際の基板温度につい
ては特に制限はないが、通常２００℃〜４５０℃が用い
られる。EXAMPLES The details will be described below. The amorphous semiconductors used in the present invention are C, N, O and S and H,
One or more selected from the group consisting of halogen, Si, and G
It can be obtained by glow discharge decomposition of a gaseous or gasified compound appropriately combined with one or more selected from the group consisting of e and Sn. In addition, by using the solid compound appropriately combined from the above as a target, the target is sputtered, or the target is sputtered in the presence of a gas appropriately combined from C, N, O, S, and H, and halogen. Can also be obtained. The substrate temperature at the time of performing the glow discharge method and the sputtering method is not particularly limited, but usually 200 ° C to 450 ° C is used.
【００１０】本発明に用いるアモルフアス多元系半導体
中に含まれるＳｉの量は５０原子％以上が好ましく、さ
らに好ましくはＣ、Ｎ、Ｏ及びＳよりなる元素の合計量
が半導体中で３０原子％以下含まれるのが良い。さらに
好ましくは、半導体中に含まれるＨとハロゲンの合計量
が、約１原子％から約４０原子％の範囲で含まれるのが
良い。また、ハロゲンの中ではフツ素が最も好ましい元
素である。The amount of Si contained in the amorphous semiconductor used in the present invention is preferably 50 atomic% or more, and more preferably the total amount of elements consisting of C, N, O and S is 30 atomic% or less in the semiconductor. Good to be included. More preferably, the total amount of H and halogen contained in the semiconductor should be in the range of about 1 atom% to about 40 atom%. Further, among halogens, fluorine is the most preferable element.
【００１１】ドーピングする場合は、製膜時にIII 族の
元素の化合物例えばＢ2 Ｈ6 、又はＶ族の元素の化合物
例えばＰＨ3等を添加するか、或は製膜後イオンインプ
ランテーシヨン法を用いることができる。そのドープ量
は２０℃に於ける暗伝動度が１０-8（Ω・cm）-1以上と
なるよう、さらに太陽電池として用いるべく接合を形成
した場合、その拡散電位が所望の値になるよう選ばれ
る。In the case of doping, a compound of a group III element such as B 2 H 6 or a compound of a group V element such as PH 3 is added at the time of film formation, or an ion implantation method after film formation is carried out. Can be used. The doping amount is such that the dark conductivity at 20 ° C. is 10 −8 (Ω · cm) −1 or more, and when the junction is formed to be used as a solar cell, the diffusion potential is set to a desired value. To be elected.
【００１２】以下、上記アモルフアス多元系半導体を太
陽電池に適用した場合について説明する。The case where the amorphous semiconductor is applied to a solar cell will be described below.
【００１３】アモルフアス多元系半導体はそのエネルギ
ー・ギヤツプをかなり任意に選ぶことができるから、ア
モルフアス太陽電池のそれぞれの層に適した組成を有す
る材料が使用できる。バンドギヤツプのグレーデイング
は連続状、間欠状、階段状等の所望の形に調整できる。
ドーピング層としてはエネルギー・ギヤツプの大きな材
料が適しており、特に光の入射側に用いられる窓材料の
光学的バンドギヤツプ（Ｅｇ・ｏｐｔ）は１．８５ｅＶ
以上が好ましい。また、有効なキヤリヤーを発生し得る
ノンドープ層のＥｇ・ｏｐｔはそのＥｇ・ｏｐｔが単一
の値を有する場合、小さい方が好ましい。しかし、さら
に好ましくはノンドープ層のＥｇ・ｏｐｔが光の入射側
では２ｅＶ或はそれ以上と大きな値を有し、光の入射側
と反対の方向に向かつて小さくなり、最終的には１ｅＶ
程度になるのが最も良い。Since the energy gap of the amorphous semiconductor is arbitrarily selected, a material having a composition suitable for each layer of the amorphous solar cell can be used. The grading of the bandgear can be adjusted to a desired shape such as continuous, intermittent or stepped.
A material having a large energy gap is suitable for the doping layer, and in particular, the optical band gap (Eg · opt) of the window material used on the light incident side is 1.85 eV.
The above is preferable. Further, the Eg · opt of the non-doped layer capable of generating an effective carrier is preferably small when the Eg · opt has a single value. However, more preferably, the Eg · opt of the non-doped layer has a large value of 2 eV or more on the light incident side, becomes small in the direction opposite to the light incident side, and finally becomes 1 eV.
It is best to be around.
【００１４】アモルフアス多元系半導体を上記太陽電池
に適用することによつて、広い波長範囲を有する太陽ス
ペクトルを有効に利用することが可能となる。また、こ
のような複雑な構造の太陽電池でなくても、一般的な構
造を有する、例えばｐｉｎ型の太陽電池のそれぞれの層
に対してアモルフアス多元系半導体を用いるだけで、従
来よりも改善された性能を得ることができる。また、こ
れらの太陽電池に於て、少なくとも１つの接合について
はその拡散電位が１．１ボルト以上になるようにするの
が好ましく、また、少なくとも１つのドーピング層、好
ましくは光の入射側のドーピング層の厚みは約３０〜３
００Åであるのが好ましい。また、ノンドープ層のＥｇ
・ｏｐｔを小さくする目的には、多元系半導体の中で
も、特にＳｉ、Ｇｅ、Ｓｎよりなる元素の群から選ばれ
た１種以上の元素とＨ、Ｆよりなる元素の群から選ばれ
た１種以上の元素とからなる真性アモルフアス半導体を
用いるのが好ましいが、III 族の元素で補償して実質的
に真性にしてもよい。By applying the amorphous semiconductor to the above solar cell, it becomes possible to effectively use the solar spectrum having a wide wavelength range. Further, even if the solar cell does not have such a complicated structure, it is possible to improve the conventional structure by using an amorphous multi-element semiconductor for each layer of a general structure such as a pin solar cell. You can get good performance. In these solar cells, it is preferable that at least one junction has a diffusion potential of 1.1 V or more, and at least one doping layer, preferably a light incident side doping layer. Layer thickness is about 30-3
It is preferably 00Å. In addition, Eg of the non-doped layer
For the purpose of reducing opt, among multi-element semiconductors, one or more elements selected from the group of elements consisting of Si, Ge, and Sn and one kind selected from the group of elements consisting of H and F It is preferable to use an intrinsic amorphous semiconductor composed of the above elements, but it may be substantially intrinsic by compensating with a Group III element.
【００１５】以下、ｎｉｐ型のグレーデツド型で、タン
デム且つマルチスタツクド構造太陽電池を一例として具
体的に本発明を説明するが、本発明はこの構造に限定さ
れるものではない。Hereinafter, the present invention will be specifically described by taking an example of a nip type graded type tandem and multi-stack structure solar cell, but the present invention is not limited to this structure.
【００１６】この構造の代表的なものの一つは透明電極
／ｎ型アモルフアス半導体／ｉ型アモルフアス半導体／
ｐ型アモルフアス半導体／電極／絶縁膜／金属箔の構造
で、透明電極側から光を照射する。光を照射する側のｎ
型アモルフアス半導体の厚みは約３０Åから３００Å、
好ましくは５０Å〜２００Å、ｉ層の厚みは限定されな
いが約１０００Å〜１００００Åが通常用いられる。ｐ
層の厚みは限定されないが約１００Å〜６００Åが用い
られる。One of the typical ones of this structure is a transparent electrode / n-type amorphous semiconductor / i-type amorphous semiconductor /
Light is emitted from the transparent electrode side in the structure of p-type amorphous semiconductor / electrode / insulating film / metal foil. N on the side that emits light
Type amorphous semiconductors have a thickness of about 30Å to 300Å,
The thickness of the i layer is preferably 50 Å to 200 Å, and the thickness of the i layer is not limited, but about 1000 Å to 10000 Å is usually used. p
The thickness of the layer is not limited, but about 100Å to 600Å is used.
【００１７】透明電極はＩＴＯやＳｎＯ2 特にＩＴＯが
好ましく、ｎ型アモルフアス半導体上に直接蒸着して得
られる。又ＩＴＯとｎ型アモルフアス半導体の界面に３
０〜５００ÅのＳｎＯ2 をつけると更に好ましい。The transparent electrode is preferably ITO or SnO 2, and particularly ITO, and can be obtained by vapor deposition directly on an n-type amorphous semiconductor. At the interface between ITO and n-type amorphous semiconductor, 3
It is more preferable to add SnO 2 of 0 to 500Å.
【００１８】ｎ型アモルフアス半導体はＥｇ・ｏｐｔが
１．８５ｅＶ以上が好ましく、特にＳｉを主体として、
これにＣ、Ｎ、Ｏ、Ｓ、及びこれらにＨ、ハロゲンを添
加したものが好ましい。さらに好ましくは、光の入射側
程Ｃ、Ｎ、Ｏ、Ｓ、及びＨ、ハロゲンの添加量を多く
し、ｉ層に向かつて漸次Ｃ、Ｎ、Ｏ、Ｓの添加量を減少
させるのが良い。The n-type amorphous semiconductor preferably has an Eg · opt of 1.85 eV or more.
It is preferable to add C, N, O, S, and H and halogen to these. More preferably, the amounts of C, N, O, S, and H and halogen added are increased toward the light incident side, and the amounts of C, N, O, and S added are gradually decreased toward the i layer. .
【００１９】ｉ型アモルフアス半導体は光の入射側から
ｉ層の厚みの約１／３から半分程度まではＳｉにＨやハ
ロゲンを添加した半導体が好ましく、残りのｉ層はこれ
にＧｅやＳｎを添加し、しかもその添加量をｐ層側に向
かつてだんだん高め、最終的にはそのＥｇ・ｏｐｔを１
ｅＶ程度にするのが好ましい。The i-type amorphous semiconductor is preferably a semiconductor obtained by adding H or halogen to Si from about 1/3 to half of the thickness of the i-layer from the light incident side, and the remaining i-layer contains Ge or Sn. Addition, and the amount added was gradually increased toward the p-layer side, and finally the Eg · opt was increased to 1
It is preferably about eV.
【００２０】ｐ型アモルフアス半導体は、裏面電極から
の反射光を有効に利用する為には比較的Ｅｇ・ｏｐｔの
大きな材料が好ましい。The p-type amorphous semiconductor is preferably a material having a relatively large Eg · opt in order to effectively use the reflected light from the back electrode.
【００２１】基板は、太陽電池に一般的に使用されてい
る透明電極付きガラス基板、ステンレス等の金属基板、
ポリイミド等の耐熱性高分子フイルムを使用できる。ま
た、アルミニウム、銅、鉄、ニツケル、ステンレス等の
金属箔又はこれに耐熱性高分子或はＳｉＯ1 、Ｓｉ
Ｏ2 、Ａｌ2 Ｏ3 、アモルフアス又は結晶性のＳｉ
(1-X) Ｃ(X) 、Ｓｉ(1-y) Ｎｙ、Ｓｉ(1-X-y) Ｃ(X) Ｎ
(y) 等又はその水素及び／又はハロゲン化物等の絶縁性
物質をコーテイングした基板も使用できる。The substrate is a glass substrate with a transparent electrode generally used for solar cells, a metal substrate such as stainless steel,
A heat resistant polymer film such as polyimide can be used. Also, metal foil such as aluminum, copper, iron, nickel, and stainless steel, or heat-resistant polymer or SiO 1 , Si
O 2 , Al 2 O 3 , amorphous or crystalline Si
(1-X) C (X) , Si (1-y) Ny, Si (1-Xy) C (X) N
A substrate coated with an insulating substance such as (y) or its hydrogen and / or halide may also be used.
【００２２】特に、発電区域を複数に分割し、その各々
を並列或は直列に接続する場合は、絶縁性基板を用いる
必要があり、この目的に添つた基板としてはガラス、又
は耐熱性高分子フイルム、更には金属箔上に前記絶縁性
物質をコーテイングした基板が好ましく、この上に電極
をパターン化して形成した基板を用いて、これにアモル
フアス半導体を形成すればよい。In particular, when the power generation area is divided into a plurality of parts and each of them is connected in parallel or in series, it is necessary to use an insulating substrate. As a substrate for this purpose, glass or heat resistant polymer is used. A substrate in which the above-mentioned insulating material is coated on a film, and further on a metal foil is preferable, and a substrate on which an electrode is patterned is used, and an amorphous semiconductor may be formed thereon.
【００２３】金属箔上に絶縁性物質をコーテイングする
場合、この絶縁性薄膜の電気伝導度は約１０-7（Ω・c
m）-1以下が好ましい。また、金属箔の厚みは特に制限
はないが、５μｍ〜２mmが好ましく、特に５０μｍ〜１
mmが好ましい。絶縁膜の厚みも金属箔を絶縁できればよ
いので任意であるが、通常１０００Åから２０μｍ程度
の範囲で用いられる。When an insulating material is coated on the metal foil, the electric conductivity of this insulating thin film is about 10 −7 (Ω · c).
m) -1 or less is preferable. The thickness of the metal foil is not particularly limited, but is preferably 5 μm to 2 mm, particularly 50 μm to 1
mm is preferred. The thickness of the insulating film is optional as long as it can insulate the metal foil, but it is usually used in the range of about 1000 Å to 20 μm.
【００２４】図１乃至図３に本発明実施例としての光起
電力装置を示すが、１１は金属箔、１２は絶縁膜で１
３、１４、１５は該絶縁基板上に膜状に形成された第
１、第２、第３の発電区域である。該発電区域の各々は
アモルファス多元系半導体層１６と該層を挟んで対向す
る第１電極１７及び第２電極１８から構成されている。
半導体層１６は図示していないが例えば基板側から順次
堆積されたｐ層、ノンドープ層（ｉ層）及びｎ層の半導
体層からなり、斯る半導体層１６は第１〜第３の発電区
域に連続して延びている。1 to 3 show a photovoltaic device as an embodiment of the present invention, in which 11 is a metal foil and 12 is an insulating film.
Reference numerals 3, 14, and 15 are first, second, and third power generation areas formed in a film shape on the insulating substrate. Each of the power generation areas is composed of an amorphous multi-component semiconductor layer 16 and a first electrode 17 and a second electrode 18 which are opposed to each other with the layer sandwiched therebetween.
Although not shown, the semiconductor layer 16 is composed of, for example, a p-layer, a non-doped layer (i-layer), and an n-layer semiconductor layer sequentially deposited from the substrate side. The semiconductor layer 16 is provided in the first to third power generation areas. It extends continuously.
【００２５】第１電極１７はｐ層とオーミツク接触する
金属又は酸化錫、酸化インジウム、ＩＴＯ（Ｉｎ2 Ｏ3
＋ｘＳｎＯ2 ，ｘ≦０．１）などで構成することができ
るが、ＩＴＯの上に５０〜５００ÅのＳｎＯ2 をつけた
ものが特に好ましい。第２電極１８は透明な酸化錫Ｉｎ
2 Ｏ3 ，ＩＴＯ又はＳｎＯ2 の上にＩＴＯをつけた電極
などで構成される。第１〜第３発電区域１３〜１５の夫
々の第１電極１７及び第２電極１８は基板１２上におい
て夫々の発電区域の外へ延びる延長部１９及び２０を有
し、第１発電区域１３の第２電極１８の延長部２０と第
２発電区域１４の第１電極１７の延長部１９とが、又第
２発電区域１４の第２電極１８の延長部２０と第３発電
区域１５の第１電極１７の延長部１９とが夫々互いに重
畳して電気的に接続されている。又第１発電区域１３の
第１電極１７の延長部１９には第２電極１８と同材料か
らなる接続部２１が重畳被着されている。なお、２１は
なくてもよい。上記装置の製造方法を簡単に説明する
と、その第１工程で基板（１１＋１２）上に延長部１９
を含んだ第１電極１７の各々が選択エツチング手法又は
選択スパツタ又は蒸着付着手法により形成され、第２工
程で第１〜第３発電区域に連続して半導体層１６が形成
される。The first electrode 17 is made of metal or tin oxide, indium oxide, ITO (In 2 O 3) which makes ohmic contact with the p layer.
+ XSnO 2 , x ≦ 0.1) or the like, but one having ITO with 50 to 500 Å SnO 2 is particularly preferable. The second electrode 18 is transparent tin oxide In
2 O 3 , ITO, or an electrode in which ITO is attached on SnO 2 or the like. The first electrode 17 and the second electrode 18 of each of the first to third power generation zones 13-15 have extensions 19 and 20 on the substrate 12 that extend out of the respective power generation zone, and The extension portion 20 of the second electrode 18 and the extension portion 19 of the first electrode 17 of the second power generation section 14, and the extension portion 20 of the second electrode 18 of the second power generation section 14 and the first portion of the third power generation section 15 The extension portions 19 of the electrodes 17 are overlapped with each other and are electrically connected. Further, a connection portion 21 made of the same material as that of the second electrode 18 is superposed on the extension portion 19 of the first electrode 17 in the first power generation area 13. It should be noted that 21 may be omitted. The method of manufacturing the device will be briefly described. In the first step, the extension portion 19 is formed on the substrate (11 + 12).
Each of the first electrodes 17 including is formed by a selective etching method, a selective sputtering method, or a vapor deposition deposition method, and in the second step, the semiconductor layer 16 is formed continuously in the first to third power generation areas.
【００２６】このとき、該層は上記延長部１９、２０に
存在してはならないので、基板７上全面に上記半導体層
を形成した後、選択エツチング手法により不要部を除去
するか、あるいは不要部を覆うマスクを用いることによ
り所望部のみに上記半導体層が形成される。続く最終工
程において延長部２０を含む第２電極１８及び接続部２
１が選択スパツタ又は蒸着手法などにより形成される。
本実施例装置において、第２電極１８を介して光が半導
体層１６に入ると、第１〜第３発電区域１３〜１５の夫
々において起電圧が生じ、各区域の第１、第２電極１
７、１８はその延長部において交互に接続されているの
で各区域の起電圧は直列的に相加され、第１発電区域１
３に連なる接続部２１を＋極、第３発電区域１５の第２
電極１８に連なる延長部２０を−極として両極の間に上
記の如く相加された電圧が発生する。At this time, since the layer should not exist in the extension portions 19 and 20, after forming the semiconductor layer on the entire surface of the substrate 7, the unnecessary portion is removed by the selective etching method, or the unnecessary portion is removed. The semiconductor layer is formed only in a desired portion by using a mask that covers the. In the subsequent final step, the second electrode 18 including the extension portion 20 and the connection portion 2
1 is formed by selective sputtering or vapor deposition.
In the device of this embodiment, when light enters the semiconductor layer 16 through the second electrode 18, an electromotive voltage is generated in each of the first to third power generation areas 13 to 15, and the first and second electrodes 1 in each area are generated.
Since 7 and 18 are alternately connected in the extension, the electromotive voltages of the respective areas are added in series, and the first power generation area 1
The connecting portion 21 connected to 3 is the positive electrode, and the second connecting portion of the third power generation area 15 is
The voltage applied as described above is generated between the two electrodes with the extension 20 connected to the electrode 18 as the negative electrode.
【００２７】又上記装置において、各発電区域の隣接間
隔が小さいと、隣り合う区域の第１電極１７どうし、あ
るいは第２電極１８どうしの間で直接電流が流れる現
象、即ち漏れ電流の発生が認められるが半導体層１６の
光照射時の抵抗値が数〜数十ＭΩであることを考慮する
と、上記隣接間隔を１μｍ以上に設定することにより、
上記漏れ電流の影響は実質的に問題とならない。必要に
より半導体層１６を各発電区域に分離して形成し、裏面
電極と隣接する受光側電極とを直列に接続してもよい。
又実用に供する場合には第２電極側から密着包囲する透
明な高分子絶縁膜又は、ＳｉＯ2 ，ａ−ＳｉＣ，ａ−Ｓ
ｉＮ，ａ−ＳｉＣＮ等の透明な絶縁膜を設けて保護する
のがよい。当然のことながら透光性基板で実施すること
も良い。Further, in the above-mentioned device, when the adjacent intervals between the power generation areas are small, a phenomenon in which a current directly flows between the first electrodes 17 or the second electrodes 18 in the adjacent areas, that is, a leakage current is generated. However, considering that the resistance value of the semiconductor layer 16 at the time of light irradiation is several to several tens of MΩ, by setting the above-mentioned adjacent interval to 1 μm or more,
The influence of the leakage current does not substantially cause a problem. If necessary, the semiconductor layer 16 may be formed separately in each power generation area, and the back surface electrode and the adjacent light receiving side electrode may be connected in series.
In practical use, a transparent polymer insulating film or SiO 2 , a-SiC, a-S that closely surrounds the second electrode side is used.
It is preferable to provide a transparent insulating film such as iN or a-SiCN for protection. As a matter of course, a translucent substrate may be used.
【００２８】以上の説明より明らかな如く、本発明の構
造によれば、アモルフアス多元系半導体を用い、同一基
板上にて複数の発電区域を直列接続したものであつて、
可撓性で小型にしてかつ任意の高電圧を発生する装置が
得られ、従来のガラス基板と同じ方法で作ることができ
るのは金属箔を絶縁した基板を用いたが故に実現された
ものであり、その製造に際しても従来の製造工程とほと
んど変わるところなく簡単な膜形成工程のみで製造する
ことができ、量産的にも極めて優れたものである。な
お、このような太陽電池は蛍光灯下で作動させる電池と
して小型の電子装置に組み込むことができるが、ＡＭ−
１ １００ｍｗ／cm2のような強い光の下で使用される
場合もあり、このような場合、通常保護回路を必要とす
るが絶縁膜１２としてアモルフアスシリコンのような光
照射時の電気伝導度の大きな材料を用いれば、蛍光灯下
では電気伝導度が小さいのでリークは少ないが、屋外光
のように強い光が当たると電気伝導度が大きくなり、光
電流がリークして保護回路の役割をするので好ましい。As is apparent from the above description, according to the structure of the present invention, a plurality of power generation areas are connected in series on the same substrate by using the amorphous multi-component semiconductor,
It is possible to obtain a device that is flexible and small, and that can generate an arbitrary high voltage, and it is possible to make it in the same way as a conventional glass substrate because it was realized by using a substrate with insulated metal foil. Also, the manufacturing process is almost the same as the conventional manufacturing process, and can be manufactured only by a simple film forming process, which is extremely excellent in mass production. It should be noted that such a solar cell can be incorporated into a small electronic device as a battery operated under a fluorescent lamp, but AM-
It may be used under strong light such as 1 100 mw / cm 2. In such a case, a protection circuit is usually required, but the electrical conductivity at the time of light irradiation such as amorphous silicon is used as the insulating film 12. If a large material is used, the electrical conductivity will be small under a fluorescent lamp, so there will be little leakage, but when exposed to strong light such as outdoor light, the electrical conductivity will increase and the photocurrent will leak, thus acting as a protective circuit. Therefore, it is preferable.
【００２９】また、本発明に用いるアモルフアス多元系
半導体は元素の組み合せとその組成を適宜選択すること
により感光体用の材料としても有用となる。即ち、太陽
電池の場合と異なつて２０℃に於ける暗伝導度が１０
-11 （Ω・cm）-1以下でかつ該伝導度の２０℃に於ける
光伝導度に対する比が１／１０００以下になるように元
素の組み合せとその組成を選ぶのが好ましい。The amorphous amorphous semiconductor used in the present invention is also useful as a material for a photoconductor by appropriately selecting the combination of elements and the composition thereof. That is, the dark conductivity at 20 ° C. is 10 unlike that of the solar cell.
It is preferable to select the combination of elements and their composition so that the conductivity is -11 (Ω · cm) -1 or less and the ratio of the conductivity to the photoconductivity at 20 ° C is 1/1000 or less.
【００３０】以上の本発明に用いるアモルフアス多元系
半導体はその製造条件によつては一部又は全部が微結晶
化する場合が認められるが、本発明に用いるアモルフア
ス多元系半導体はこのような微結晶化した部分を有して
いても良い。Although some or all of the amorphous amorphous semiconductors used in the present invention may be microcrystallized depending on the production conditions, the amorphous amorphous semiconductors used in the present invention have such fine crystallites. It may have a converted portion.
【００３１】さらに、グロー放電分解によつて本発明に
用いるアモルフアス多元系半導体を製造する場合、ｒｆ
電界と少なくとも部分的には直交した領域を有する磁界
を備えている装置を用いて、製膜速度の増大と膜質の向
上を図ることができる。Further, in the case of producing the amorphous amorphous semiconductor used in the present invention by glow discharge decomposition, rf
An apparatus provided with a magnetic field having a region at least partially orthogonal to the electric field can be used to increase the film formation speed and improve the film quality.
【００３２】[0032]
【発明の効果】叙上の通り、本発明によれば、広い波長
範囲を有する太陽スペクトルを有効に利用できる。また
化学組成比の大巾且つ急激な変化がないので接合界面の
欠陥が低減するとともに、バンドプロフアイルのフレキ
シビリテイによるキヤリヤー（電子及び正孔）の走行の
スムージング効果が得られ、キヤリヤーの移動度を大き
く且つ導電率を高めることが可能である。As described above, according to the present invention, the solar spectrum having a wide wavelength range can be effectively used. In addition, since the chemical composition ratio does not change significantly and does not change abruptly, defects at the bonding interface are reduced, and the smoothing effect of the carrier (electrons and holes) traveling due to the flexibility of the band profile is obtained, and the movement of the carrier is achieved. It is possible to increase the degree and increase the conductivity.
【図１】実施例を示す側面図である。FIG. 1 is a side view showing an embodiment.
【図２】図１におけるＢ−Ｂ断面図である。FIG. 2 is a sectional view taken along line BB in FIG.
【図３】図１におけるＣ−Ｃ断面図である。FIG. 3 is a sectional view taken along line CC of FIG.
Claims (17)
びにハロゲンよりなる元素の群から選ばれた１種以上の
元素、及びＳｉ、Ｇｅ、Ｓｎよりなる元素の群から選ば
れた１種以上の元素とからなるアモルフアス多元系半導
体を構成要素として持つグレーデツド型半導体素子を１
つ以上含むタンデムおよび／またはマルチスタツクド半
導体素子。1. An element consisting of C, N, O and S, at least one element selected from the group of elements consisting of H and halogen, and an element consisting of Si, Ge and Sn. A graded-type semiconductor device having an amorphous multi-element semiconductor composed of one or more elements as a constituent element
Tandem and / or multi-stacked semiconductor devices containing one or more.
求項１記載の半導体素子。2. The semiconductor device according to claim 1, wherein halogen is F.
を特徴とする請求項１又は２記載の半導体素子。3. The semiconductor device according to claim 1, wherein the composition of Si is 50 atomic% or more.
約３０原子％以下であることを特徴とする請求項３記載
の半導体素子。4. The semiconductor device according to claim 3, wherein the total amount of elements consisting of C, N, O and S is about 30 atomic% or less.
合計が６０原子％以上９９原子％以下であることを特徴
とする請求項３又は４記載の半導体素子。5. The semiconductor device according to claim 3, wherein the total of elements consisting of Si and C, N, O and S is 60 at% or more and 99 at% or less.
でドーピングされた半導体を含むことを特徴とする請求
項１乃至５記載の半導体素子。6. The semiconductor device according to claim 1, further comprising a semiconductor doped with an element belonging to Group III or Group V of the periodic table.
m）-1以上であることを特徴とする請求項６記載の半導
体素子。7. The dark conductivity at 20 ° C. is 10 −8 (Ω · c)
The semiconductor device according to claim 6, wherein m) -1 or more.
層は、その光学的バンドギヤツプＥｇ・ｏｐｔが１．８
５ｅＶ以上であり、かつ少なくとも１つの接合の拡散電
位が１．１ボルト以上であることを特徴とする請求項６
又は７記載の半導体素子。8. At least one of the doping layers has an optical bandgap Eg · opt of 1.8.
7. The voltage of 5 eV or more, and the diffusion potential of at least one junction is 1.1 volt or more.
Or the semiconductor device according to 7.
層の厚みが約３０〜３０００Åであることを特徴とする
請求項８記載の半導体素子。9. The semiconductor device according to claim 8, wherein the thickness of at least one of the doping layers is about 30 to 3000Å.
に形成された複数の光電変換区域を有し、該区域の集電
手段は各区域に於る光起電力が直列関係になるように互
いに電気的に接続されてなることを特徴とする請求項８
又は９記載の半導体素子。10. The semiconductor device has a plurality of photoelectric conversion areas formed on an electrically insulating substrate, and the current collecting means of the areas is arranged so that the photovoltaics in the areas are in a series relationship. 9. The structure according to claim 8, which are electrically connected to each other.
Alternatively, the semiconductor element according to 9 above.
形成した電気絶縁性基板の上に薄膜で形成されているこ
とを特徴とする請求項１０記載の半導体素子。11. The semiconductor device according to claim 10, wherein the plurality of semiconductor devices are formed as thin films on an electrically insulating substrate formed on a metal foil.
-7（Ω・cm）-1以下の電気伝導度を有する薄膜であるこ
とを特徴とする請求１０又は１１記載の半導体素子。12. The electrically insulating thin film of the substrate has a thickness of about 10 μm.
12. The semiconductor device according to claim 10, which is a thin film having an electric conductivity of −7 (Ω · cm) −1 or less.
又はＳｉＯ、ＳｉＯ2 、Ａｌ2 Ｏ3 、又はアモルフアス
若しくは結晶性のＳｉ(1-X) Ｃ(X) 、Ｓｉ
(1-y) Ｎ(y) 、Ｓｉ(1-X-y) Ｃz Ｎy 又はアモルフアス
シリコンから選ばれることを特徴とする請求項１２記載
の半導体素子。13. The heat-insulating polymer as the electrically insulating thin film,
Or SiO, SiO 2 , Al 2 O 3 , or amorphous or crystalline Si (1-X) C (X) , Si
(1-y) N (y ), Si (1-Xy) C z N y or a semiconductor device according to claim 12, wherein the selected from Amorufu Ass silicon.
極には透明な電極を設けたことを特徴とする請求項８乃
至記載の半導体素子。14. The semiconductor element according to claim 8, wherein at least one electrode of the semiconductor element is provided with a transparent electrode.
Ｏ2 又はＩＴＯとアモルフアス層との界面に約３０〜５
００ÅのＳｎＯ2 を設けたＩＴＯ−ＳｎＯ2 複合電極で
あることを特徴とする請求項１４記載の半導体素子。15. The transparent electrode is ITO or Sn.
Approximately 30 to 5 at the interface between O 2 or ITO and the amorphous layer.
The semiconductor device according to claim 14, which is an ITO-SnO 2 composite electrode provided with 00Å SnO 2 .
が、上記基板上にてなされていることを特徴とする請求
項８乃至１５記載の半導体素子。16. The semiconductor device according to claim 8, wherein the plurality of semiconductor devices are electrically connected to each other on the substrate.
電界と少なくとも部分的には直交した領域を有する磁界
を備えている装置を用いて、グロー放電分解を行なうこ
とによつて製造されることを特徴とする請求項１乃至第
１６記載の半導体素子。17. The amorphous semiconductor is rf.
17. Semiconductor device according to claims 1 to 16, characterized in that it is manufactured by performing glow discharge decomposition using a device comprising a magnetic field having a region at least partially orthogonal to the electric field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3198724A JPH077843B2 (en) | 1982-11-01 | 1991-07-12 | Amorphous multi-element semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57192032A JPS5983916A (en) | 1982-11-01 | 1982-11-01 | Amorphous multielement semiconductor |
| JP3198724A JPH077843B2 (en) | 1982-11-01 | 1991-07-12 | Amorphous multi-element semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57192032A Division JPS5983916A (en) | 1982-11-01 | 1982-11-01 | Amorphous multielement semiconductor |
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| Publication Number | Publication Date |
|---|---|
| JPH0597412A JPH0597412A (en) | 1993-04-20 |
| JPH077843B2 true JPH077843B2 (en) | 1995-01-30 |
Family
ID=26507051
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| JP3198724A Expired - Lifetime JPH077843B2 (en) | 1982-11-01 | 1991-07-12 | Amorphous multi-element semiconductor device |
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| KR101258185B1 (en) * | 2011-07-22 | 2013-04-25 | 광주과학기술원 | Solar cell module and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4342044A (en) * | 1978-03-08 | 1982-07-27 | Energy Conversion Devices, Inc. | Method for optimizing photoresponsive amorphous alloys and devices |
| JPS5511329A (en) * | 1978-07-08 | 1980-01-26 | Shunpei Yamazaki | Semiconductor device |
| DE2941559C2 (en) * | 1979-10-13 | 1983-03-03 | Messerschmitt-Bölkow-Blohm GmbH, 8000 München | Process for depositing silicon on a substrate |
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| JPH0597412A (en) | 1993-04-20 |
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