JPH0770856B2 - Position detection method for hybrid integrated circuit board - Google Patents
Position detection method for hybrid integrated circuit boardInfo
- Publication number
- JPH0770856B2 JPH0770856B2 JP1045891A JP4589189A JPH0770856B2 JP H0770856 B2 JPH0770856 B2 JP H0770856B2 JP 1045891 A JP1045891 A JP 1045891A JP 4589189 A JP4589189 A JP 4589189A JP H0770856 B2 JPH0770856 B2 JP H0770856B2
- Authority
- JP
- Japan
- Prior art keywords
- recognition
- integrated circuit
- substrate
- hybrid integrated
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Image Analysis (AREA)
- Image Processing (AREA)
- Structure Of Printed Boards (AREA)
- Supply And Installment Of Electrical Components (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、混成集積回路基板をマウント装置やワイヤボ
ンディング装置に装填し、装填位置を画像認識によって
検出する混成集積回路基板の位置検出方法に関する。Description: TECHNICAL FIELD The present invention relates to a position detection method for a hybrid integrated circuit board, in which the hybrid integrated circuit board is mounted on a mounting device or a wire bonding device and the mounting position is detected by image recognition. .
［従来の技術］ 混成集積回路基板上にマウンター装置によって電子部品
をマウントする場合や、基板上の半導体チップにワイヤ
ーボンディング装置によってワイヤーボンディングする
場合には、電極パターン、厚膜抵抗等が形成された基板
をこれらの装置の所定の位置に配置しなければならな
い。所定の位置に配置されたか否かは、従来、第７図及
び第８図のように、基板１上に電極パターン、抵抗、ガ
ラス等の印刷時に同時に設けられた認識マーク２を、CC
Dカメラ等で光学的に読み取り、標準マークと比較して
決定する。[Prior Art] When mounting electronic components on a hybrid integrated circuit board by a mounter device or wire bonding to a semiconductor chip on the substrate by a wire bonding device, electrode patterns, thick film resistors, etc. were formed. The substrate must be placed in place on these devices. Whether or not it has been arranged at a predetermined position is determined by the CC as shown in FIG. 7 and FIG.
Optically read with a D camera, etc., and determined by comparing with a standard mark.
［発明が解決しようとする課題］ ところで、認識マーク２は、電極パターン、抵抗、ガラ
ス等の印刷時に設けられるため、その後の工程において
上面に傷が付く場合があった。認識マーク上面に傷が付
いた場合、傷により上面に乱反射が起り、認識エラーを
起こすことがある。[Problems to be Solved by the Invention] By the way, since the recognition mark 2 is provided at the time of printing an electrode pattern, a resistor, glass, etc., the upper surface of the recognition mark 2 may be damaged in the subsequent steps. When the upper surface of the recognition mark is scratched, the scratch may cause irregular reflection on the upper surface, resulting in a recognition error.
そこで、本発明の目的は、傷による認識エラーを防ぐこ
とができる混成集積回路基板の位置検出方法を提供する
ことにある。Therefore, an object of the present invention is to provide a method for detecting the position of a hybrid integrated circuit board that can prevent a recognition error due to a scratch.
［課題を解決するための手段］ 上記目的を達成するための本発明は、混成集積回路を構
成するための基板上に認識マークを設け、この認識マー
クを光学的に読み取って前記基板の位置を検出する混成
集積回路基板の位置検出方法において、第１の色の第１
の領域とこの第１の領域の外側に配設された第２の色の
第２の領域とから成る認識マークを設けると共に、前記
第２の領域の周辺に前記第１の領域を基準にして前記第
２の領域よりも突出している突出部を設け、前記第１及
び第２の領域を利用した画像認識によって前記基板の位
置検出を行う混成集積回路基板の位置検出方法に係わる
ものである。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a recognition mark on a substrate for forming a hybrid integrated circuit, and optically reads the recognition mark to determine the position of the substrate. In the method for detecting the position of a hybrid integrated circuit board, the first color of the first color is detected.
And an identification mark composed of a second region of the second color arranged outside the first region, and at the periphery of the second region with reference to the first region. The present invention relates to a position detecting method for a hybrid integrated circuit board, wherein a protruding portion protruding from the second area is provided, and the position of the board is detected by image recognition using the first and second areas.
なお、突出部は第２の領域と同一材料で形成することが
望ましい。In addition, it is desirable that the protruding portion is formed of the same material as that of the second region.
［作用］ 本発明における突出部は第２の領域の保護領域として機
能する、即ち、第２の領域は突出部よりも低いので、突
出部によって保護され、第２の領域に傷が付き難い。突
出部には傷が付いても、突出部は画像認識に無関係な領
域であるから認識エラーは発生しない。[Operation] The protrusion in the present invention functions as a protection region of the second region, that is, the second region is lower than the protrusion, and thus is protected by the protrusion and the second region is less likely to be scratched. Even if the protrusion is scratched, a recognition error does not occur because the protrusion is an area unrelated to image recognition.
［実施例］ 次に、第１図〜第４図を参照して本発明の実施例に係わ
る混成集積回路基板の位置検出方法を説明する。[Embodiment] Next, a method of detecting a position of a hybrid integrated circuit board according to an embodiment of the present invention will be described with reference to FIGS.
第３図に示すように、多数のアルミナ基板11のそれぞれ
の周辺部に認識マーク12を印刷する。この認識マーク12
は、銀パラジウム電極材料の印刷によって形成する。な
お、認識マーク12は電極即ち配線導体（図示せず）と同
時に形成する。第３図では各基板11の対角線上の２箇所
に設けられている。As shown in FIG. 3, the recognition marks 12 are printed on the periphery of each of the many alumina substrates 11. This recognition mark 12
Is formed by printing a silver-palladium electrode material. The recognition mark 12 is formed at the same time as the electrode, that is, the wiring conductor (not shown). In FIG. 3, it is provided at two positions on the diagonal of each substrate 11.
第１図及び第２図に拡大図示されている認識マーク11
は、黒（第１の色）として認識されるセラミック基板11
からなる第１の領域13とこれを囲む銀パラジウム系導体
から成る第２の色の第２の領域14と、土手のように形成
された突出部15とから成る。突出部15は第１の領域13と
同一の銀パラジウム系導体から成り、第１の領域と同時
に形成されている。第２の領域14は突出部15から基板11
の表面に向って垂れ下がっている傾斜面領域であって、
白（第２の色）として認識される。導体から成る認識マ
ーク12は四角形であって、外側の各辺の長さは約1mmで
あり、四角形の第１の領域13の各辺の長さは約0.4mmで
ある。A recognition mark 11 shown in an enlarged scale in FIGS. 1 and 2.
Is a ceramic substrate 11 recognized as black (first color)
A second region 14 of a second color composed of a silver-palladium-based conductor, which surrounds the first region 13, and a protrusion 15 formed like a bank. The protrusion 15 is made of the same silver-palladium-based conductor as the first region 13 and is formed at the same time as the first region. The second region 14 extends from the protrusion 15 to the substrate 11
A sloped area that hangs toward the surface of
It is recognized as white (second color). The recognition mark 12 made of a conductor is a quadrangle, and the length of each outer side is about 1 mm, and the length of each side of the first region 13 of the quadrangle is about 0.4 mm.
認識マーク12の形成が終了したら、厚膜抵抗（図示せ
ず）を形成する。After forming the recognition mark 12, a thick film resistor (not shown) is formed.
次に、電子部品（半導体チップ）をマウントするため
に、認識マーク12を有する基板11をマウント装置に装填
する。第４図はマウント装置における位置検出方式を原
理的に示すものであり、台16上の基板11の認識マークを
読み取るためのCCDカメラ17、及び認識装置18等を含
む。認識装置18には、第１の領域13に対応した標準マー
ク（画像データ）が予め書き込まれているメモリを内蔵
しており、この標準マークとカメラ17で読み取った認識
マークを比べて所定位置を検出する。認識装置18によっ
て認識マーク12と標準マークとが不一致であることが判
定された時には移動装置（図示せず）によって基板11を
移動して両マークを一致させる。第２図に鎖線で示す認
識エリア19の中に第１の領域13が入った場合に標準マー
クと合致したものと見なされる。Next, in order to mount an electronic component (semiconductor chip), the substrate 11 having the recognition mark 12 is loaded in the mounting device. FIG. 4 shows in principle the position detection method in the mount device, which includes a CCD camera 17 for reading the recognition mark of the substrate 11 on the base 16 and a recognition device 18. The recognition device 18 has a built-in memory in which a standard mark (image data) corresponding to the first area 13 is written in advance. The standard mark and the recognition mark read by the camera 17 are compared to determine a predetermined position. To detect. When the recognition device 18 determines that the recognition mark 12 and the standard mark do not match, the moving device (not shown) moves the substrate 11 to match the two marks. When the first area 13 is included in the recognition area 19 shown by the chain line in FIG. 2, it is considered to match the standard mark.
基板11の位置ずれが補正されたら、電子部品をマウント
し、半田付けする。しかる後、ワイヤボンディング装置
に電子部品（半導体チップ）をマウントした後の基板11
を移し、マウント時と同様な方法で基板11の位置決めを
なし、電子部品（半導体チップ）にワイヤを接続する。After the displacement of the board 11 is corrected, the electronic components are mounted and soldered. After that, the substrate 11 after mounting the electronic component (semiconductor chip) on the wire bonding device
Then, the substrate 11 is positioned by the same method as when mounting, and the wire is connected to the electronic component (semiconductor chip).
本実施例の位置検出方法は次の効果を有する。The position detecting method of this embodiment has the following effects.
（１） 突出部15によって土手状に囲まれている第１の
領域13と第２の領域14とが認識エリア19となるので、突
出部15に傷が付いても、これに無関係にパターン認識を
行うことが可能になり、認識エラーが少なくなる。(1) Since the first area 13 and the second area 14 surrounded by the protrusion 15 in a bank shape serve as the recognition area 19, even if the protrusion 15 is scratched, pattern recognition is performed regardless of this. Can be performed and recognition errors are reduced.
（２） 第２の領域14は突出部15の形成によって必然的
に生じる傾斜部であるので、認識マーク12の形成が複雑
にならない。(2) Since the second region 14 is an inclined portion that is inevitably formed by the formation of the protrusion 15, the formation of the recognition mark 12 is not complicated.
［変形例］ 本発明は上述の実施例に限定されるものでなく、例えば
次の変形が可能なものである。[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.
（１） 認識マーク12を第５図に示すように断面形状半
円形状に形成してもよい。(1) The recognition mark 12 may be formed in a semicircular cross section as shown in FIG.
（２） 第６図に示すように、複数の基板11の共通の周
辺部に認識マーク12を設けてもよい。(2) As shown in FIG. 6, the recognition mark 12 may be provided in the common peripheral portion of the plurality of substrates 11.
（３） 認識マーク12を抵抗体と基板11との組み合わせ
で形成することができる。また、認識マーク12を導体と
抵抗体との組み合わせで形成することもできる。(3) The recognition mark 12 can be formed by combining the resistor and the substrate 11. The recognition mark 12 can also be formed by combining a conductor and a resistor.
（４） 認識マーク12を平面形状円形にしてもよい。(4) The recognition mark 12 may be circular in plan view.
［発明の効果］ 上述のように本発明によれば、認識マークの傷による認
識エラーの発生が少ない混成集積回路基板の位置検出方
法を提供することができる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a method for detecting the position of a hybrid integrated circuit board in which recognition errors due to scratches on the recognition marks are less likely to occur.
第１図は本発明の実施例に係わる認識マークを示す第２
図のＩ−Ｉ線に対応する断面図、 第２図は第１図の認識マークを示す平面図、 第３図は基板と認識マークとを示す平面図、 第４図はマウント装置における画像認識システムを原理
的に示すブロック図、 第５図は変形例の認識マークを示す断面図、 第６図は変形例の基板と認識マークとを示す平面図、 第７図は従来の認識マークを示す平面図、 第８図は第７図の認識マークの断面図である。 11……基板、12……認識マーク、13……第１の領域、14
……第２の領域、突出部……15、認識装置……18。FIG. 1 is a second view showing a recognition mark according to an embodiment of the present invention.
FIG. 2 is a plan view showing a recognition mark of FIG. 1, FIG. 3 is a plan view showing a substrate and a recognition mark, and FIG. 4 is an image recognition in a mount device. FIG. 5 is a block diagram showing the system in principle, FIG. 5 is a cross-sectional view showing a modification recognition mark, FIG. 6 is a plan view showing a modification substrate and a recognition mark, and FIG. 7 is a conventional recognition mark. A plan view and FIG. 8 are cross-sectional views of the recognition mark shown in FIG. 11 ... Board, 12 ... Recognition mark, 13 ... First area, 14
...... Second area, protrusions ... 15, recognition device ... 18.
Claims (2)
識マークを設け、この認識マークを光学的に読み取って
前記基板の位置を検出する混成集積回路基板の位置検出
方法において、第１の色の第１の領域とこの第１の領域
の外側に配設された第２の色の第２の領域とから成る認
識マークを設けると共に、前記第２の領域の周辺に前記
第１の領域を基準にして前記第２の領域よりも突出して
いる突出部を設け、前記第１及び第２の領域を利用した
画像認識によって前記基板の位置検出を行うことを特徴
とする混成集積回路基板の位置検出方法。1. A method for detecting the position of a hybrid integrated circuit board, wherein a recognition mark is provided on a substrate for forming a hybrid integrated circuit, and the recognition mark is optically read to detect the position of the substrate. An identification mark composed of a first area of color and a second area of a second color arranged outside the first area is provided, and the first area is provided around the second area. The position of the substrate is detected by image recognition using the first and second regions, and the position of the substrate is detected by providing a protrusion that protrudes from the second region. Position detection method.
同時に形成されたものである請求項１記載の混成集積回
路基板の位置検出方法。2. The method for detecting the position of a hybrid integrated circuit board according to claim 1, wherein the protrusion is formed of the same material as that of the second region at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1045891A JPH0770856B2 (en) | 1989-02-27 | 1989-02-27 | Position detection method for hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1045891A JPH0770856B2 (en) | 1989-02-27 | 1989-02-27 | Position detection method for hybrid integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02224184A JPH02224184A (en) | 1990-09-06 |
| JPH0770856B2 true JPH0770856B2 (en) | 1995-07-31 |
Family
ID=12731865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1045891A Expired - Fee Related JPH0770856B2 (en) | 1989-02-27 | 1989-02-27 | Position detection method for hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770856B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103353098B (en) * | 2013-06-25 | 2015-09-23 | 陈志明 | A kind of high-powered LED lamp cooling device and preparation method thereof |
| CN103398358B (en) * | 2013-06-25 | 2015-10-21 | 陈志明 | A kind of low light attenuation high-power LED street lamp and preparation method thereof |
| WO2018155089A1 (en) | 2017-02-23 | 2018-08-30 | 株式会社村田製作所 | Electronic component, electronic apparatus, and method for mounting electronic component |
-
1989
- 1989-02-27 JP JP1045891A patent/JPH0770856B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02224184A (en) | 1990-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6038868B2 (en) | semiconductor package | |
| KR920002969B1 (en) | Printed circuit board and a method of recognizing the position of surface mounted parts | |
| JPH0770856B2 (en) | Position detection method for hybrid integrated circuit board | |
| GB2249672A (en) | Circuit board and apparatus for recognizing the position of a circuit board | |
| JPH01119088A (en) | Printed wiring board for mounting surface mounting parts | |
| JPH0236284Y2 (en) | ||
| JPH0219976B2 (en) | ||
| JP2553786B2 (en) | Circuit board recognition mark placement method | |
| KR100420434B1 (en) | Circuit board for semiconductor package | |
| JP3528366B2 (en) | Integrated circuit device | |
| JP2586410B2 (en) | Semiconductor device and mounting method thereof | |
| JP3094523B2 (en) | Electronic component mounting mark, printed circuit board, and electronic component mounting method | |
| JPH05283825A (en) | Printed-circuit board with identification mark | |
| JPH05145206A (en) | Printed wiring board | |
| JPH05110239A (en) | Printed wiring board | |
| JP3040461U (en) | Printed wiring board | |
| JPH0613741A (en) | Circuit board for surface mount component | |
| KR100384332B1 (en) | Orientation detecting method of semiconductor chip for wire bonding | |
| JP3006075B2 (en) | Lead length variation detecting method and solder tip appearance inspection method | |
| JPS60121793A (en) | Method of producing thick film hybrid integrated circuit board | |
| JPH04129259A (en) | Electronic parts | |
| JPS62214635A (en) | Detecting device and detecting/processing device | |
| JPS62118596A (en) | Parts detection | |
| JPH09238000A (en) | Recognition method of electronic components and automatic mounting equipment of electronic components | |
| JP2001015994A (en) | Method for mounting ic package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |