JPH0770645B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0770645B2 JPH0770645B2 JP61136680A JP13668086A JPH0770645B2 JP H0770645 B2 JPH0770645 B2 JP H0770645B2 JP 61136680 A JP61136680 A JP 61136680A JP 13668086 A JP13668086 A JP 13668086A JP H0770645 B2 JPH0770645 B2 JP H0770645B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- hybrid integrated
- sealing resin
- components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路に関し、特にサーマルヘッドや密
着型イメージセンサ等のような、列状に配置された同一
寸法の部品、例えば半導体集積回路を具備する混成集積
回路において、前記部品を樹脂封止（表面コートあるい
はプリコート）する際に、封止樹脂の流れを必要最小限
にし得る混成集積回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and in particular, components of the same size arranged in a row, such as a thermal head or a contact image sensor, for example, a semiconductor integrated circuit. In the hybrid integrated circuit including the above, the flow of the sealing resin can be minimized when the component is resin-sealed (surface-coated or pre-coated).
従来、この種の混成集積回路は、例えば第２図に模式的
平面図を示すように、薄膜状あるいは厚膜状に配線され
たセラミックやほうろう等の基板１上に半導体集積回路
２を列状に並べ、しかる後にこれらの半導体集積回路を
封止樹脂３によって封止する構造となっていた。第３図
は第２図のＡ−Ａ′線部における模式的断面図を示すも
のである。Conventionally, a hybrid integrated circuit of this type has semiconductor integrated circuits 2 arranged in rows on a substrate 1 such as ceramic or enamel which is wired in a thin film or thick film as shown in a schematic plan view of FIG. Then, these semiconductor integrated circuits are sealed with the sealing resin 3. FIG. 3 is a schematic sectional view taken along the line AA ′ in FIG.
上述した従来の混成集積回路、例えば８本/mmの発熱抵
抗体解像度を有するA4版サーマルヘッドにおいて、単一
の半導体集積回路が64本の発熱抵抗体を駆動する場合に
は、1728本の発熱抵抗体を駆動するために合計27個の半
導体集積回路が8mmのピッチで基板１上に配置されるこ
とになる。半導体集積回路の横寸法ｂは凡そ1.5〜2.5mm
であるので、半導体集積回路間の間隙ｃは凡そ6.5〜5.5
mmとなり、この間隙は半導体集積回路の横寸法ｂの数倍
の値となる。従って、この半導体集積回路を耐環境性向
上のために封止樹脂３によって封止すると、第２図に示
すように、封止樹脂は縦寸法ａの半導体集積回路部にお
いてはl2の寸法となり、半導体集積回路が搭載されてい
ない基板部においてはl1の寸法となり（l1〉l2），半導
体集積回路のない領域における封止樹脂の流れは大とな
る。封止樹脂の流れの差ｄ＝（l1−l2）の値は搭載部品
によって異なるが一般には１〜3mmとなる。このｄの値
が大きくなると近傍の配線パターンや実装部品等に影響
を与えることになり、混成集積回路を小型化は著しい障
害を受けることになる。In the conventional hybrid integrated circuit described above, for example, in an A4 version thermal head having a resolution of 8 heating resistors / mm, when a single semiconductor integrated circuit drives 64 heating resistors, 1728 heating resistors are generated. A total of 27 semiconductor integrated circuits are arranged on the substrate 1 at a pitch of 8 mm to drive the resistors. The lateral dimension b of the semiconductor integrated circuit is approximately 1.5 to 2.5 mm.
Therefore, the gap c between the semiconductor integrated circuits is about 6.5 to 5.5.
mm, which is several times the lateral dimension b of the semiconductor integrated circuit. Therefore, when this semiconductor integrated circuit is sealed with the sealing resin 3 in order to improve the environment resistance, the sealing resin has a dimension of l 2 in the semiconductor integrated circuit portion having the vertical dimension a as shown in FIG. In the substrate portion on which the semiconductor integrated circuit is not mounted, the dimension is l 1 (l 1 > l 2 ), and the flow of the sealing resin in the region without the semiconductor integrated circuit is large. The value of the difference d = (l 1 −l 2 ) in the flow of the sealing resin varies depending on the mounted parts, but is generally 1 to 3 mm. If the value of d becomes large, it will affect nearby wiring patterns, mounted components, etc., and miniaturization of the hybrid integrated circuit will be a serious obstacle.
本発明の目的は、列状に配置された搭載部品間隙部の封
止樹脂の流れを最小にし近傍の配線パターンや実装部品
に対する悪影響を防ぎ、かつ小型化に適した混成集積回
路を提供することにある。An object of the present invention is to provide a hybrid integrated circuit suitable for miniaturization while minimizing the flow of sealing resin in the space between mounted components arranged in rows to prevent adverse effects on nearby wiring patterns and mounted components. It is in.
本発明の混成集積回路は、基板上に複数の電子部品が、
各電子部品の幅よりも広い間隔でもって等間隔に一直線
状に搭載される混成集積回路において、隣り合う前記電
子部品の間にダミー部品をそれぞれ搭載し、かつ一直線
状に形成される樹脂で前記電子部品および前記ダミー部
品を表面コートしたことを特徴とする。The hybrid integrated circuit of the present invention has a plurality of electronic components on a substrate,
In a hybrid integrated circuit that is mounted in a straight line at equal intervals with a width wider than the width of each electronic component, dummy parts are respectively mounted between the adjacent electronic components, and the resin is formed in a straight line. The electronic component and the dummy component are surface-coated.
次に、本発明の実施例について図面を参照して説明す
る。第１図は本発明の一実施例の要部を模式的に示した
平面図である。１は配線導電体を具備する混成集積回路
用基板であり、２は所望とする電子部品、例えば半導体
集積回路である。これらの半導体集積回路間には同一形
状のダミー用シリコン片３が搭載され、シリコン片３は
搭載部品間の間隙が等間隔になるように配置される。こ
れらの半導体集積回路及びシリコン片を封止樹脂によっ
て封止すると第１図に示すように半導体集積回路（シリ
コン片）部及びこれらの間隙部における封止樹脂の流れ
の差ｄ′＝（l3−l2）は小さくなる。例えば半導体集積
回路（シリコン片）の寸法を2.5mmとし、半導体集積回
路とシリコン片との間隙を3mmとするとｄ′の値は0.5mm
以下となる。従って、本発明の実施によって封止樹脂の
流れは従来の値（ｄ＝１〜3mm）に較べて著しく小さく
なる。それ故、本発明は近傍の基板領域に与える封止樹
脂の影響を小さくし、混成集積回路を小型化する利点を
有する。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view schematically showing a main part of an embodiment of the present invention. Reference numeral 1 is a hybrid integrated circuit substrate having a wiring conductor, and 2 is a desired electronic component, for example, a semiconductor integrated circuit. Dummy silicon pieces 3 having the same shape are mounted between these semiconductor integrated circuits, and the silicon pieces 3 are arranged so that the mounting parts have equal intervals. When these semiconductor integrated circuits and silicon pieces are sealed with a sealing resin, as shown in FIG. 1, the difference in the flow of the sealing resin between the semiconductor integrated circuit (silicon pieces) and these gaps d ′ = (l 3 −l 2 ) becomes smaller. For example, if the size of the semiconductor integrated circuit (silicon piece) is 2.5 mm and the gap between the semiconductor integrated circuit and the silicon piece is 3 mm, the value of d'is 0.5 mm.
It becomes the following. Therefore, by carrying out the present invention, the flow of the sealing resin becomes significantly smaller than the conventional value (d = 1 to 3 mm). Therefore, the present invention has the advantage of reducing the influence of the sealing resin on the substrate region in the vicinity and reducing the size of the hybrid integrated circuit.
なお、本発明が上記した効果を呈する搭載部品あるいは
ダミー部品の材料，形状，機能等は特に限定されるべき
ものではなく、また部品の搭載・配置方法も特に指定さ
れるべきものではない。勿論、封止樹脂の成分、塗布方
法等も特に指定されるべきものではない。It should be noted that the material, shape, function, etc. of the mounted component or the dummy component, in which the present invention exhibits the above-described effects, should not be particularly limited, and the component mounting / arranging method should not be specifically designated. Of course, the components of the sealing resin, the coating method, and the like are not particularly specified.
しかしながら、本発明は特に微細パターンを有する混成
集積回路に対して効果があり、搭載部品としては半導体
集積回路が適し、ダミー部品としてはシリコン片が適当
であり、封止樹脂としてはプリコート用のシリコーン樹
脂が特に適している。また配置方法としては半導体集積
回路とシリコン片とを交互に等間隔で配置することが望
ましい。勿論本発明は、半導体集積回路等の搭載部品
と、シリコン片等のダミー部品とが形状，材質等が異な
っていても適用できるものであり、また半導体集積回路
間の寸法が異なっていてもよいことは論を持たない。However, the present invention is particularly effective for a hybrid integrated circuit having a fine pattern, a semiconductor integrated circuit is suitable as a mounting part, a silicon piece is suitable as a dummy part, and a silicone for precoating is a sealing resin. Resins are particularly suitable. As a placement method, it is desirable that the semiconductor integrated circuits and the silicon pieces are placed alternately at equal intervals. Of course, the present invention can be applied even if the mounted parts such as semiconductor integrated circuits and the dummy parts such as silicon pieces have different shapes and materials, and the dimensions between the semiconductor integrated circuits may be different. Things have no arguments.
以上説明したように本発明は、列状に配置された搭載部
品間間隙部に封止樹脂流れ防止用のダミー部品を配置搭
載することにより、搭載部品を封止するための樹脂の流
れを最小にできる。その結果、近傍の配線パターンや実
装部品に対する悪影響を防ぐことができ、小型化に適し
た混成集積回路が得られる。As described above, the present invention minimizes the resin flow for sealing the mounted components by disposing and mounting the dummy components for preventing the sealing resin flow in the gaps between the mounted components arranged in rows. You can As a result, it is possible to prevent adverse effects on nearby wiring patterns and mounted components, and to obtain a hybrid integrated circuit suitable for miniaturization.
第１図は本発明の一実施例の要部を模式的に示す平面
図、第２図は従来例の要部を模式的に示す平面図、第３
図は第２図のＡ−Ａ′線部における断面図である。 １……基板、２……半導体集積回路、２′……シリコン
片、３……封止樹脂。FIG. 1 is a plan view schematically showing an essential part of an embodiment of the present invention, and FIG. 2 is a plan view schematically showing an essential part of a conventional example.
The drawing is a sectional view taken along the line AA 'in FIG. 1 ... Substrate, 2 ... Semiconductor integrated circuit, 2 '... Silicon piece, 3 ... Sealing resin.
Claims (1)
幅よりも広い間隔でもって等間隔に一直線状に搭載され
る混成集積回路において、隣り合う前記電子部品の間に
ダミー部品をそれぞれ搭載し、かつ一直線状に形成され
る樹脂で前記電子部品および前記ダミー部品を表面コー
トしたことを特徴とする混成集積回路。1. A hybrid integrated circuit in which a plurality of electronic components are mounted on a substrate in a straight line at regular intervals wider than the width of each electronic component, and dummy components are provided between adjacent electronic components. A hybrid integrated circuit in which the electronic component and the dummy component are surface-coated with a resin that is respectively mounted and formed in a straight line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136680A JPH0770645B2 (en) | 1986-06-11 | 1986-06-11 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61136680A JPH0770645B2 (en) | 1986-06-11 | 1986-06-11 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62291157A JPS62291157A (en) | 1987-12-17 |
| JPH0770645B2 true JPH0770645B2 (en) | 1995-07-31 |
Family
ID=15180961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61136680A Expired - Lifetime JPH0770645B2 (en) | 1986-06-11 | 1986-06-11 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770645B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4518114B2 (en) | 2007-07-25 | 2010-08-04 | Ｔｄｋ株式会社 | Electronic component built-in substrate and manufacturing method thereof |
| JP4518113B2 (en) | 2007-07-25 | 2010-08-04 | Ｔｄｋ株式会社 | Electronic component built-in substrate and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5939940U (en) * | 1982-09-07 | 1984-03-14 | アルプス電気株式会社 | Hybrid integrated circuit device |
-
1986
- 1986-06-11 JP JP61136680A patent/JPH0770645B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62291157A (en) | 1987-12-17 |
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