JPH0752589A - Ic card module - Google Patents
Ic card moduleInfo
- Publication number
- JPH0752589A JPH0752589A JP5199577A JP19957793A JPH0752589A JP H0752589 A JPH0752589 A JP H0752589A JP 5199577 A JP5199577 A JP 5199577A JP 19957793 A JP19957793 A JP 19957793A JP H0752589 A JPH0752589 A JP H0752589A
- Authority
- JP
- Japan
- Prior art keywords
- card
- chip
- thickness
- module
- card module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＩＣカードに内蔵もしく
は装着されるＩＣカードモジュールに係わり、さらに詳
しくはその信頼性向上に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card module built in or attached to an IC card, and more particularly to improving its reliability.
【０００２】[0002]
【従来の技術】現在、キャッシュカードやクレジットカ
ードをはじめ病院の診察券に至るまで様々なカードが使
用されている。これらのカードは現在、磁気ストライプ
カードが主流である。しかし、このカードは記憶容量が
不足しているため機能拡張に限界があり、偽造、変造が
容易であるなどセキュリティ、信頼性の面でも限界があ
る。2. Description of the Related Art Currently, various cards such as cash cards, credit cards, and medical examination tickets for hospitals are used. Currently, these cards are mainly magnetic stripe cards. However, this card has a limit in expansion of functions due to lack of storage capacity, and there is a limit in terms of security and reliability such as easy forgery and alteration.
【０００３】このような問題を解消し、非常に大きな記
憶容量を持ち、高度なセキュリティ機能を有するカード
に、ＩＣチップ内蔵のモジュールを埋め込んだＩＣカー
ドがある。このＩＣカードは多方面で開発されており、
既に一部では銀行の預金通帳機能を合わせ持つキャッシ
ュカードやＩＤカードなどに実用化されている。There is an IC card in which a module having a built-in IC chip is embedded in a card which solves such a problem, has a very large storage capacity, and has a high security function. This IC card has been developed in various fields,
It has already been put to practical use in some areas, such as cash cards and ID cards that also have a bank passbook function.
【０００４】図６に一般的なＩＣカードの平面図を示
す。ＩＣカードは例えば、塩化ビニルからなるカード基
体４０の一部にＩＣカードモジュール３０が埋設されて
構成されている。FIG. 6 shows a plan view of a general IC card. The IC card is configured by embedding the IC card module 30 in a part of a card base 40 made of vinyl chloride, for example.
【０００５】図７は、図６に示したＩＣカードモジュー
ルの断面図である。ＩＣカードモジュール３０は、モジ
ュール基板２にＩＣチップ５０が接着剤５で固定され、
ＩＣチップ５０上に形成されたボンディングパッド７と
パターン電極４がボンディングワイヤ６で接続され、封
止枠９内に充填された封止材１０で気液密に封止されて
いる。FIG. 7 is a sectional view of the IC card module shown in FIG. In the IC card module 30, the IC chip 50 is fixed to the module substrate 2 with the adhesive 5,
The bonding pad 7 formed on the IC chip 50 and the pattern electrode 4 are connected by a bonding wire 6, and are sealed in a gas-liquid tight manner by a sealing material 10 filled in a sealing frame 9.
【０００６】前記モジュール基板２の片面にはＩＣカー
ド端末装置と電気的に接続される外部端子３が、また他
の片面にはパターン電極４が、それぞれ形成され、両者
はスルーホール８で電気的に接続されている。External terminals 3 electrically connected to the IC card terminal device are formed on one surface of the module substrate 2, and pattern electrodes 4 are formed on the other surface of the module substrate 2, both of which are electrically connected through a through hole 8. It is connected to the.
【０００７】このＩＣカードモジュール３０は、ＩＣチ
ップ５０の厚みが０．３ｍｍ程度と非常に薄くて割れや
すいから、それを保護するためにモジュール基板２に充
分な剛性を持たせ、ＩＣカードモジュール３０自体が変
形しないようにすることが必要である。In this IC card module 30, the IC chip 50 has a very thin thickness of about 0.3 mm and is easily cracked. Therefore, in order to protect the IC chip 50, the module substrate 2 has sufficient rigidity so that the IC card module 30 can be protected. It is necessary not to deform itself.
【０００８】[0008]
【発明が解決しようとする課題】しかし、ＩＣカードモ
ジュール３０は薄いカード（約０．８ｍｍ厚）に埋設さ
れるため、その厚みは約０．６ｍｍ以下にしなければな
らず、他の部材によって寸法制限を受け、充分な厚み
（約２００μｍ程度）の高剛性のモジュール基板２を用
いることができない。However, since the IC card module 30 is embedded in a thin card (thickness of about 0.8 mm), its thickness must be less than about 0.6 mm. Due to the limitation, it is not possible to use a highly rigid module substrate 2 having a sufficient thickness (about 200 μm).
【０００９】よって従来のＩＣカードモジュール３０は
外力によって変形し、内部のＩＣチップ５０が割れた
り、ボンディングワイヤ６が外れたりするトラブルが発
生しやすいという欠点があった。Therefore, the conventional IC card module 30 is deformed by an external force, and there is a drawback that the internal IC chip 50 is cracked and the bonding wire 6 is easily detached.
【００１０】本発明は、外力によって内部のＩＣチップ
が破損するという欠点を解決し、以て信頼性に優れたＩ
Ｃカードモジュールを提供することを目的とする。The present invention solves the drawback that the internal IC chip is damaged by an external force, and thus has an excellent reliability.
It is intended to provide a C card module.
【００１１】[0011]
【課題を解決するための手段】上記目的は、ＩＣカード
に内蔵もしくは装着されるＩＣカードモジュールにおい
て、厚さが０．３ｍｍ以上のモジュール基板上に厚さが
０．１ｍｍ以下の極薄状のＩＣチップ膜を接合した第１
の手段により達成される。SUMMARY OF THE INVENTION The above-mentioned object is to provide an IC card module built in or mounted in an IC card with an ultrathin film having a thickness of 0.1 mm or less on a module substrate having a thickness of 0.3 mm or more. 1st IC chip membrane joined
It is achieved by means of.
【００１２】また、この第１の手段は、前記ＩＣチップ
膜がｐ層とｎ層を含むアクティブ層と、そのアクティブ
層の片面に形成された保護層とからなる第２の手段によ
り達成される。The first means is achieved by the second means in which the IC chip film comprises an active layer including ap layer and an n layer, and a protective layer formed on one surface of the active layer. .
【００１３】[0013]
【作用】ＩＣカードに内蔵もしくは装着されるＩＣカー
ドモジュールにおいて、チップ厚が０．１ｍｍ以下のＩ
Ｃチップを内蔵することにより、モジュール基板の厚み
を０．３ｍｍ以上に充分に取ることができ、外力に非常
に強い構造のＩＣカードモジュールを得ることができ
る。In the IC card module built in or mounted in the IC card, the chip thickness is 0.1 mm or less
By incorporating the C chip, the thickness of the module substrate can be sufficiently set to 0.3 mm or more, and an IC card module having a structure extremely resistant to external force can be obtained.
【００１４】[0014]
【実施例】本発明のＩＣカードモジュールの第１実施例
について、図１ならびに図２を用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the IC card module of the present invention will be described with reference to FIGS.
【００１５】図１において図中の２は例えばガラスエポ
キシからなるモジュール基板で、それぞれ片面に例えば
銅箔をエッチングした後、ニッケルおよび金メッキを施
して作製された外部電極３、および外部電極３と同様に
して作製された電極パターン４が形成されている。８は
外部電極３と電極パターン４を電気的に接続するスルー
ホールである。９はＩＣチップ１を封止する封止材の流
れを堰き止める例えばガラスエポキシからなる封止枠
で、モジュール基板２にエポキシ系樹脂などで接着され
ている。In FIG. 1, reference numeral 2 in the drawing denotes a module substrate made of, for example, glass epoxy, which is the same as the external electrode 3 and the external electrode 3 which are produced by etching copper foil on one surface and then nickel and gold plating, respectively. The electrode pattern 4 manufactured as described above is formed. Reference numeral 8 is a through hole that electrically connects the external electrode 3 and the electrode pattern 4. Reference numeral 9 denotes a sealing frame that blocks the flow of the sealing material that seals the IC chip 1 and is made of, for example, glass epoxy, and is bonded to the module substrate 2 with an epoxy resin or the like.
【００１６】ＩＣチップ１は例えばエポキシ系樹脂から
なる接着剤５でモジュール基板２に固定されている。６
は例えば金線からなるボンディングワイヤで、ＩＣチッ
プ１上のボンディングパッド７と電極パターン４とを電
気的に接続している。１０は例えばＳｉＯ2 フィラ入り
のエポキシ樹脂からなる封止材である。ＩＣチップ１
は、厚みが５０μｍ程度でウェハの例えば機械的研磨も
しくはケミカルエッチングにより薄膜化される。The IC chip 1 is fixed to the module substrate 2 with an adhesive 5 made of, for example, an epoxy resin. 6
Is a bonding wire made of, for example, a gold wire, and electrically connects the bonding pad 7 on the IC chip 1 and the electrode pattern 4. Reference numeral 10 is a sealing material made of, for example, an epoxy resin containing a SiO 2 filler. IC chip 1
Is thinned to a thickness of about 50 μm by, for example, mechanical polishing or chemical etching of the wafer.
【００１７】図２は、その薄膜ＩＣチップの製造工程を
示す説明図である。FIG. 2 is an explanatory view showing a manufacturing process of the thin film IC chip.
【００１８】珪素（Ｓｉ）のウェハ１ａ上に二酸化珪素
（ＳｉＯ2 ）の保護膜１ｂを形成し、さらにその上にｐ
層、ｎ層を含むアクティブ層１ｃを形成する。この積層
体の形成方法は従来から周知の技術であり、ウェハ１ａ
を担体としてその上に保護膜１ｂならびにアクティブ層
１ｃが順次形成される。A silicon dioxide (SiO 2 ) protective film 1b is formed on a silicon (Si) wafer 1a, and p is further formed thereon.
An active layer 1c including a layer and an n layer is formed. The method of forming this laminated body is a well-known technique, and the wafer 1a
As a carrier, a protective film 1b and an active layer 1c are sequentially formed on the carrier.
【００１９】しかる後、この積層体を例えば、水酸化カ
リウムの４０％水溶液（７０℃）に１０〜２０時間浸漬
することにより、ウェハ１ａを溶解除去し、保護膜１ｂ
とアクティブ層１ｃとを有する厚さｔが約１０〜５０μ
ｍの極薄の膜状ＩＣチップ１を得ることができる。この
時、積層体のアクティブ層側は例えばガラス板などで保
護しているため、エッチング液に侵されない。Thereafter, the wafer 1a is dissolved and removed by immersing the laminated body in, for example, a 40% aqueous solution of potassium hydroxide (70 ° C.) for 10 to 20 hours to form a protective film 1b.
And the active layer 1c have a thickness t of about 10 to 50 μm.
It is possible to obtain an ultrathin film-shaped IC chip 1 of m. At this time, since the active layer side of the laminate is protected by, for example, a glass plate, it is not attacked by the etching solution.
【００２０】なお、必要に応じてケミカルエッチングの
時間を前述の条件より短くして、ウェハ１ａの一部を残
した極薄のＩＣチップ１を得ることも可能である。If necessary, the chemical etching time may be set shorter than the above conditions to obtain an ultrathin IC chip 1 in which a part of the wafer 1a remains.
【００２１】この構成によればモジュール基板２の厚み
は、ＩＣチップ１の厚みを５０μｍとした場合、約４０
０μｍ確保することができ、充分に剛性を持たせること
ができるため、外力に対して非常に強く、内部のＩＣチ
ップ１が破損されることはない。なお、一般に材料の強
度は厚みの２乗にほぼ比例することから考えて、モジュ
ール基板２の厚みを従来のモジュール基板の厚み（２０
０μｍ）の１．５倍（強度にして約２倍強）の３００μ
ｍ（０．３ｍｍ）以上にすれば、充分な効果が得られ
る。According to this structure, the thickness of the module substrate 2 is about 40 when the thickness of the IC chip 1 is 50 μm.
Since 0 μm can be secured and sufficient rigidity can be provided, it is extremely strong against external force and the internal IC chip 1 is not damaged. Since the strength of the material is generally proportional to the square of the thickness, the thickness of the module substrate 2 is set to the thickness of the conventional module substrate (20
300μ, which is 1.5 times (about 2 times stronger) than 0μm)
If it is m (0.3 mm) or more, a sufficient effect can be obtained.
【００２２】そしてＩＣチップ１の厚みを０．１ｍｍ以
下にすれば、モジュール基板２の厚み３００μｍ（０．
３ｍｍ）は充分に達成できる。If the IC chip 1 has a thickness of 0.1 mm or less, the module substrate 2 has a thickness of 300 μm (0.
3 mm) can be fully achieved.
【００２３】図３は、本発明の第２実施例を説明するた
めの断面図である。図中の１１は例えばＰＩＱ，ＳｉＯ
2 などからなる絶縁材であり、薄膜配線１２とチップの
電気的接触を防ぐためのものである。１２は例えばＡ
ｕ，Ａｌ，Ｃｕなどの金属導体からなる薄膜配線であ
る。ＩＣチップ１はボンディングパッド７とパターン電
極４を薄膜配線１２で接続することによりモジュール基
板２に電気的に接続される。FIG. 3 is a sectional view for explaining the second embodiment of the present invention. 11 in the figure is, for example, PIQ, SiO
It is an insulating material composed of 2 or the like, and is for preventing electrical contact between the thin film wiring 12 and the chip. 12 is for example A
It is a thin film wiring made of a metal conductor such as u, Al, or Cu. The IC chip 1 is electrically connected to the module substrate 2 by connecting the bonding pad 7 and the pattern electrode 4 with the thin film wiring 12.
【００２４】本構造によれば、薄膜配線１２としたこと
で図１のワイヤボンディングを施したＩＣカードモジュ
ールに比べて配線に必要な高さが縮小でき、その分モジ
ュール基板２の厚みをさらに厚くすることができるか
ら、ＩＣカードモジュールの信頼性をさらに向上でき
る。According to this structure, since the thin film wiring 12 is used, the height required for wiring can be reduced as compared with the IC card module to which the wire bonding shown in FIG. 1 is applied, and the thickness of the module substrate 2 is further increased accordingly. Therefore, the reliability of the IC card module can be further improved.
【００２５】図４に図３に示した実施例の製造方法の一
例を示す。FIG. 4 shows an example of the manufacturing method of the embodiment shown in FIG.
【００２６】まず同図（ａ）に示すように、ガラスエポ
キシからなるモジュール基板２のそれぞれ片面に、銅箔
をエッチングした後、ニッケルおよび金メッキを施して
作製された外部電極３、および外部電極３と同様にして
作製された電極パターン４が形成され、それらがスルー
ホール８で導通される。First, as shown in FIG. 3A, an external electrode 3 and an external electrode 3 each made by etching copper foil on one surface of a module substrate 2 made of glass epoxy and then plating it with nickel and gold. Electrode patterns 4 produced in the same manner as above are formed, and they are conducted through through holes 8.
【００２７】封止枠９を設けてなるＩＣカードモジュー
ル基体２０に、裏面を水酸化カリウム水溶液で適量除去
して厚みを５０μｍ以下にしたＩＣチップ１を、エポキ
シ系樹脂からなる接着剤５で接着固定する。An IC chip 1 having a thickness of 50 μm or less obtained by removing an appropriate amount of the back surface with an aqueous potassium hydroxide solution is bonded to an IC card module substrate 20 provided with a sealing frame 9 with an adhesive 5 made of an epoxy resin. Fix it.
【００２８】次に同図（ｂ）に示すように、ＰＩＱから
なる絶縁材１１を滴下し、加熱硬化させる。Next, as shown in FIG. 3B, the insulating material 11 made of PIQ is dropped and cured by heating.
【００２９】次に同図（ｃ）に示すように、パターン電
極１５およびボンディングパッド７上の絶縁材１１を公
知のリソグラフィ技術により除去する。Next, as shown in FIG. 3C, the pattern electrode 15 and the insulating material 11 on the bonding pad 7 are removed by a known lithography technique.
【００３０】次に同図（ｄ）に示すように、Ａｌからな
る薄膜配線１２をリソグラフィ技術により形成する。Next, as shown in FIG. 3D, the thin film wiring 12 made of Al is formed by the lithography technique.
【００３１】最後に同図（ｅ）に示すように、ＳｉＯ2
フィラ入りのエポキシ樹脂からなる封止材１０を充填し
て、図３に示した本発明のＩＣカードモジュールを得
る。Finally, as shown in FIG. 2 (e), SiO 2
The sealing material 10 made of epoxy resin containing filler is filled to obtain the IC card module of the present invention shown in FIG.
【００３２】図５は、本発明の第３実施例を説明するた
めの断面図である。図中の１３は例えばステンレス、セ
ラミック、ガラスエポキシ樹脂などからなる補強板で、
モジュール基板２の反対の面に例えばエポキシ系樹脂な
どの接着剤によって封止枠９に接着固定されている。FIG. 5 is a sectional view for explaining the third embodiment of the present invention. Reference numeral 13 in the figure is a reinforcing plate made of, for example, stainless steel, ceramic, glass epoxy resin, or the like.
An adhesive such as an epoxy resin is used to adhere and fix the sealing frame 9 to the opposite surface of the module substrate 2.
【００３３】本構造によれば、モジュール基板２の反対
の面にも補強手段を施すことにより、ＩＣカードモジュ
ール裏面からの直接的なストレスから内部ＩＣチップ１
を保護することができる。なお、本構成は図３に示した
実施例と組み合わせてもよい。According to this structure, the internal IC chip 1 is prevented from being directly stressed from the rear surface of the IC card module by providing the reinforcing means also on the opposite surface of the module substrate 2.
Can be protected. Note that this configuration may be combined with the embodiment shown in FIG.
【００３４】[0034]
【発明の効果】以上説明したように本発明によれば、Ｉ
Ｃカードモジュールは非常に薄いＩＣチップを用いるこ
とにより、ＩＣチップを充分な厚みの剛性の高いモジュ
ール基板で保護できるため、ＩＣカードモジュールは殆
ど曲がらず、内部のＩＣチップにダメージを与えること
はない。よって、外力に対して充分な抗力を有する信頼
性の高いＩＣカードモジュールを得ることができる。As described above, according to the present invention, I
By using a very thin IC chip in the C card module, the IC chip can be protected by a highly rigid module substrate with a sufficient thickness, so that the IC card module is hardly bent and does not damage the internal IC chip. . Therefore, it is possible to obtain a highly reliable IC card module having sufficient resistance to external force.
【図１】本発明の第１実施例に係るＩＣカードモジュー
ルの縦断面図である。FIG. 1 is a vertical cross-sectional view of an IC card module according to a first embodiment of the present invention.
【図２】ＩＣチップの製造工程を示す説明図である。FIG. 2 is an explanatory diagram showing a manufacturing process of an IC chip.
【図３】本発明の第２実施例に係るＩＣカードモジュー
ルの縦断面図である。FIG. 3 is a vertical sectional view of an IC card module according to a second embodiment of the present invention.
【図４】図３に示したＩＣカードモジュールの製造工程
を示す縦断面図である。4 is a vertical cross-sectional view showing a manufacturing process of the IC card module shown in FIG.
【図５】本発明の第３実施例に係るＩＣカードモジュー
ルの縦断面図である。FIG. 5 is a vertical sectional view of an IC card module according to a third embodiment of the present invention.
【図６】一般的なＩＣカードの平面図である。FIG. 6 is a plan view of a general IC card.
【図７】従来のＩＣカードモジュールの縦断面図であ
る。FIG. 7 is a vertical sectional view of a conventional IC card module.
１ ＩＣチップ １ａ ウェハ １ｂ 保護膜 １ｃ アクティブ層 ２ モジュール基板 ３ 外部電極 ４ 電極パターン ５ 接着剤 ６ ボンディングワイヤ ７ ボンディングパッド ８ スルーホール ９ 封止枠 １０ 封止材 1 IC Chip 1a Wafer 1b Protective Film 1c Active Layer 2 Module Substrate 3 External Electrode 4 Electrode Pattern 5 Adhesive 6 Bonding Wire 7 Bonding Pad 8 Through Hole 9 Sealing Frame 10 Sealing Material
───────────────────────────────────────────────────── フロントページの続き (72)発明者 玉田 要 大阪府茨木市丑寅一丁目１番88号 日立マ クセル株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kaname Tamada 1-88, Toyora, Ibaraki-shi, Osaka Inside Hitachi Maxell Co., Ltd.
Claims (4)
Ｃカードモジュールにおいて、厚さが０．３ｍｍ以上の
モジュール基板上に厚さが０．１ｍｍ以下の極薄状のＩ
Ｃチップ膜を接合したことを特徴とするＩＣカードモジ
ュール。1. An I built in or attached to an IC card
In the C card module, an ultra-thin I having a thickness of 0.1 mm or less is formed on a module substrate having a thickness of 0.3 mm or more.
An IC card module having a C-chip film bonded thereto.
膜がｐ層とｎ層を含むアクティブ層と、そのアクティブ
層の片面に形成された保護層とからなることを特徴とす
るＩＣカードモジュール。2. The IC card module according to claim 1, wherein the IC chip film comprises an active layer including ap layer and an n layer, and a protective layer formed on one surface of the active layer.
膜のボンディングパットと前記モジュール基板に設けら
れたパターン電極間の接続を薄膜配線で行ったことを特
徴とするＩＣカードモジュール。3. The IC card module according to claim 1, wherein the bonding pad of the IC chip film and the pattern electrode provided on the module substrate are connected by thin film wiring.
モジュールの外部電極とは反対側に補強板が設けられて
いることを特徴とするＩＣカードモジュール。4. The IC card module according to claim 1, wherein a reinforcing plate is provided on the opposite side of the IC card module from the external electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199577A JPH0752589A (en) | 1993-08-11 | 1993-08-11 | Ic card module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199577A JPH0752589A (en) | 1993-08-11 | 1993-08-11 | Ic card module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0752589A true JPH0752589A (en) | 1995-02-28 |
Family
ID=16410158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5199577A Pending JPH0752589A (en) | 1993-08-11 | 1993-08-11 | Ic card module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0752589A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005346559A (en) * | 2004-06-04 | 2005-12-15 | Nittoku Eng Co Ltd | Ic module and manufacturing method thereof |
| US7652359B2 (en) | 2002-12-27 | 2010-01-26 | Semiconductor Energy Laboratory Co., Ltd. | Article having display device |
| WO2012141246A1 (en) * | 2011-04-12 | 2012-10-18 | 凸版印刷株式会社 | Ic module and ic card |
-
1993
- 1993-08-11 JP JP5199577A patent/JPH0752589A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7652359B2 (en) | 2002-12-27 | 2010-01-26 | Semiconductor Energy Laboratory Co., Ltd. | Article having display device |
| US7863116B2 (en) | 2002-12-27 | 2011-01-04 | Semiconductor Energy Laboratory Co., Ltd. | IC card and booking-account system using the IC card |
| US8268702B2 (en) | 2002-12-27 | 2012-09-18 | Semiconductor Energy Laboratory Co., Ltd. | IC card and booking-account system using the IC card |
| US8674493B2 (en) | 2002-12-27 | 2014-03-18 | Semiconductor Energy Laboratory Co., Ltd. | IC card and booking-account system using the IC card |
| JP2005346559A (en) * | 2004-06-04 | 2005-12-15 | Nittoku Eng Co Ltd | Ic module and manufacturing method thereof |
| WO2012141246A1 (en) * | 2011-04-12 | 2012-10-18 | 凸版印刷株式会社 | Ic module and ic card |
| JP6079624B2 (en) * | 2011-04-12 | 2017-02-15 | 凸版印刷株式会社 | IC module and IC card |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI301588B (en) | Semiconductor module and production method therefor and module for ic cards and the like | |
| US6659356B2 (en) | Hybrid IC card | |
| AU710390B2 (en) | Semiconductor device | |
| JPH0930171A (en) | Method for manufacturing and assembling electronic card and electronic card obtained by said method | |
| JPS6250196A (en) | Method of mounting integrated circuit to substrate, device assembled by said method and card with microelectronic circuit device | |
| JP2004046832A (en) | Ic card, and its production method | |
| JP4289689B2 (en) | IC card and manufacturing method thereof | |
| JPH1095189A (en) | Manufacture of semiconductor device | |
| JPH11195096A (en) | Non-contact electronic card and its production | |
| JP2970411B2 (en) | Semiconductor device | |
| JPH06227189A (en) | Production of ic card module | |
| JPH0752589A (en) | Ic card module | |
| JP3468954B2 (en) | IC card | |
| JPH0387299A (en) | Ic card | |
| JP2000067200A (en) | Ic card | |
| JPH09148378A (en) | Ic module for ic card, manufacture thereof, and ic card using the ic module | |
| JP2005078101A (en) | Contact type/non-contact type hybrid ic module and contact type/non-contact type hybrid ic card using the same | |
| JPH0324383Y2 (en) | ||
| JP3350405B2 (en) | Semiconductor device | |
| JP2661101B2 (en) | IC card | |
| JP2904785B2 (en) | IC module with built-in card | |
| JPH04166396A (en) | Ic card module | |
| JPS62227796A (en) | Integrated circuit card | |
| KR100702940B1 (en) | Integrated circuit card and the fabrication method thereof | |
| JP2000200333A (en) | Ic card and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20011016 |