JPH0744251B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0744251B2
JPH0744251B2 JP60058904A JP5890485A JPH0744251B2 JP H0744251 B2 JPH0744251 B2 JP H0744251B2 JP 60058904 A JP60058904 A JP 60058904A JP 5890485 A JP5890485 A JP 5890485A JP H0744251 B2 JPH0744251 B2 JP H0744251B2
Authority
JP
Japan
Prior art keywords
semiconductor device
bump
bumps
substrate
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60058904A
Other languages
Japanese (ja)
Other versions
JPS61216455A (en
Inventor
通 前川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60058904A priority Critical patent/JPH0744251B2/en
Publication of JPS61216455A publication Critical patent/JPS61216455A/en
Publication of JPH0744251B2 publication Critical patent/JPH0744251B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】 〔概要〕 本発明は、少なくとも２個の半導体チップをIn系金属の
バンプにより結合してなる半導体装置において、両方の
チップのバンプ間にInの融点より低い温度でInと合金を
つくる、例えばAuよりなる合金形成用金属層を介在させ
て、加熱してInとの合金層を形成することにより、両方
のチップの結合力を増強するものである。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor device in which at least two semiconductor chips are bonded by In-based metal bumps, and the In between the bumps of both chips is lower than the melting point of In. By forming an alloy layer with In by interposing an alloy forming metal layer made of, for example, Au and forming an alloy layer with In, the binding force of both chips is enhanced.

〔産業上の利用分野〕[Industrial application field]

本発明はIn系金属のバンプを有する半導体装置に係り、
特にチップ間の結合力を増強するバンプ構造に関する。The present invention relates to a semiconductor device having bumps of In-based metal,
In particular, it relates to a bump structure that enhances the bonding force between chips.

In系金属のバンプを有する半導体装置として、例えば赤
外検知素子がある。An example of a semiconductor device having an In-based metal bump is an infrared detection element.

光起電力（PV）型赤外検知素子は水銀カドミウムテルル
（HgCdTe）結晶が用いられている。Mercury cadmium tellurium (HgCdTe) crystals are used for photovoltaic (PV) infrared detectors.

赤外検知素子と、これより来る信号の処理回路を形成し
た珪素（Si）素子で構成したハイブリッド半導体装置に
おいて、両素子の接続はインジウム（In）バンプが用い
られている。In a hybrid semiconductor device including an infrared detection element and a silicon (Si) element on which a processing circuit for signals coming from the infrared detection element is formed, indium (In) bumps are used to connect both elements.

この理由は、 （１） Inがｎ型HgCdTeに対して良好なオーミックコン
タクトを形成できること、 （２） Inの融点（156.4℃）が低いこと、 （両チップの接続に際し、高温で処理をするとHgCdTeか
らHgが蒸発するため、バンプ形成材料は低融点であるこ
とが必要である） である。This is because (1) In can form a good ohmic contact with n-type HgCdTe, (2) In has a low melting point (156.4 ° C), (When connecting both chips, HgCdTe is processed at high temperature. Therefore, the bump forming material must have a low melting point).

上記のようなハイブリッド半導体装置において、装置の
強度上バンプ間の結合力が要求されている。In the hybrid semiconductor device as described above, a bonding force between the bumps is required for the strength of the device.

〔従来の技術と発明が解決しようとする問題点〕[Problems to be solved by conventional technology and invention]

従来のバンプ結合では、Inバンプ同志を押しつけて結合
させていたが、素子を損傷する危険があるため強く押し
つけることができないので、結合力が弱いという欠点が
あった。In the conventional bump bonding, the In bumps are pressed against each other to be bonded, but since there is a risk of damaging the element, they cannot be pressed strongly, so there is a drawback that the bonding strength is weak.

さらにチップ間を接着剤で結合する場合もあるが、この
場合は接着剤とチップとの熱膨張係数の差により、素子
を損傷する危険がある。Further, the chips may be bonded with an adhesive, but in this case, there is a risk of damaging the element due to the difference in thermal expansion coefficient between the adhesive and the chips.

あるいはバンプを露出させてチップを樹脂で被覆し、樹
脂同志を接着する方法もあるが、この場合も樹脂とチッ
プとの熱膨張係数の差により、素子を損傷する危険があ
る。Alternatively, there is a method in which the bumps are exposed and the chip is covered with a resin, and the resins are adhered to each other, but in this case as well, there is a risk of damaging the element due to the difference in thermal expansion coefficient between the resin and the chip.

あるいはバンプを露出させてチップを樹脂で被覆し、樹
脂同志を接着する方法もあるが、この場合も樹脂とチッ
プとの熱膨張係数の差により、素子を損傷する危険があ
る。Alternatively, there is a method in which the bumps are exposed and the chip is covered with a resin, and the resins are adhered to each other, but in this case as well, there is a risk of damaging the element due to the difference in thermal expansion coefficient between the resin and the chip.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、第１の半導体チップ（１）上に形
成されたインジウム（In）、またはインジウムを含む合
金よりなるバンプ（２）を、インジウムの融点より低い
温度でインジウムと合金をつくる合金形成用金属層
（３）を介在させて、第２の半導体チップ（４）のバン
プ（５）に接触させ、加熱して両半導体チップ（１）と
（４）を結合してなる半導体装置により達成される。To solve the above problems, the bump (2) made of indium (In) or an alloy containing indium formed on the first semiconductor chip (1) is alloyed with indium at a temperature lower than the melting point of indium. A semiconductor device obtained by contacting the bumps (5) of the second semiconductor chip (4) with the alloy forming metal layer (3) interposed therebetween and heating them to bond the two semiconductor chips (1) and (4) together. Achieved by

前記いずれかの半導体チップ（１）、または（４）がHg
CdTe結晶よりなり、また前記合金形成用金属層（３）が
Auよりなる場合は特に効果がある。Any of the above semiconductor chips (1) or (4) is Hg
It is made of CdTe crystal, and the metal layer (3) for alloy formation is
It is particularly effective when it is made of Au.

〔作用〕[Action]

本発明は片方の半導体チップのInバンプを形成する時
に、Inバンプ上にAu層を形成し、他方の半導体チップの
Inバンプ上にはAu層を形成させないで、両バンプを押し
つけて結合させた後、150℃程度の低温でアニールする
とAuとInの合金ができることを利用して、半導体チップ
を損傷することなく両バンプ間の結合力を強化するもの
である。The present invention forms the Au layer on the In bump when forming the In bump of one semiconductor chip, and
Without forming an Au layer on the In bumps, press and bond both bumps and anneal at a low temperature of about 150 ° C to make an alloy of Au and In. It strengthens the bonding force between bumps.

〔実施例〕〔Example〕

第１図（１）乃至（３）は本発明の実施例を工程順に示
した基板断面図である。FIGS. 1 (1) to (3) are cross-sectional views of a substrate showing an embodiment of the present invention in the order of steps.

第１図（１）において、第１の半導体チップとしてHgCd
Te基板１の上に、高さ10μｍのInバンプ２を形成し、In
バンプ２の上に合金形成用金属として厚さ1000ÅのAu層
３を被着する。In FIG. 1 (1), HgCd is used as the first semiconductor chip.
An In bump 2 having a height of 10 μm is formed on the Te substrate 1 and
An Au layer 3 having a thickness of 1000 Å is deposited on the bump 2 as an alloy forming metal.

第１図（２）において、第２の半導体チップとしてSi基
板４上にInバンプ５を形成し、Inバンプ５をAu層３を介
してInバンプ２の上に載せ、半導体チップ１と４を結合
する。In FIG. 1 (2), In bumps 5 are formed on a Si substrate 4 as a second semiconductor chip, the In bumps 5 are placed on the In bumps 2 via the Au layer 3, and the semiconductor chips 1 and 4 are mounted. Join.

第１図（３）において、結合した半導体チップをアニー
ルすると、AuとInの合金層６が形成される。In FIG. 1 (3), when the bonded semiconductor chips are annealed, an alloy layer 6 of Au and In is formed.

アニールの条件は、例えば150℃で４時間である。The annealing condition is, for example, 150 ° C. for 4 hours.

第２図は本発明による赤外検知用ハイプリッド半導体装
置の構造を模式的に説明する基板断面図である。FIG. 2 is a substrate sectional view schematically explaining the structure of the hybrid semiconductor device for infrared detection according to the present invention.

図において、11はｐ型HgCdTe基板、12は基板内に形成さ
れたｎ型HgCdTe領域、13は絶縁層である。In the figure, 11 is a p-type HgCdTe substrate, 12 is an n-type HgCdTe region formed in the substrate, and 13 is an insulating layer.

PV型素子はｐ型HgCdTe基板11に、Inバンプ５は絶縁層13
を開口してｎ型HgCdTe領域12上に形成される。The PV type element is on the p type HgCdTe substrate 11, and the In bump 5 is the insulating layer 13.
And is formed on the n-type HgCdTe region 12 by opening.

一方、41はｐ型Si基板で、42は基板内に形成されたｎ型
Si領域、43は絶縁層である。On the other hand, 41 is a p-type Si substrate and 42 is an n-type formed in the substrate.
The Si region, 43 is an insulating layer.

ｐ型Si基板41に、入力ゲート44と転送ゲート45を形成し
て電荷結合素子（CCD）が構成され、ｎ型Si領域42とｐ
型Si基板41は入力ダイオードを構成し、Inバンプ２は絶
縁層43を開口してｎ型Si領域42上に形成される。An input gate 44 and a transfer gate 45 are formed on a p-type Si substrate 41 to form a charge coupled device (CCD), and an n-type Si region 42 and a p-type Si region 42 are formed.
The type Si substrate 41 constitutes an input diode, and the In bump 2 is formed on the n type Si region 42 by opening the insulating layer 43.

AuとInの合金層６で両チップは強く結合されている。Both chips are strongly bonded by the alloy layer 6 of Au and In.

〔発明の効果〕〔The invention's effect〕

以上詳細に説明したように本発明によれば、Inバンプ間
の合金層により、バンプ間の結合力を強化することがで
き、半導体装置の信頼性を向上することができる。As described in detail above, according to the present invention, the alloy layer between the In bumps can strengthen the bonding force between the bumps and improve the reliability of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

第１図（１）乃至（３）は本発明の実施例を工程順に示
した基板断面図、 第２図は本発明による赤外検知用ハイプリッド半導体装
置の構成を模式的に説明する基板断面図である。 図において、 １は第１の半導体チップでHgCdTe基板、 11はｐ型HgCdTe基板、 12はｎ型HgCdTe領域、 13は絶縁層、 ２はInバンプ、 ３は合金形成用金属でAu層、 ４は第２の半導体チップでSi基板、 41はｐ型Si基板、 42はｎ型Si領域、 43は絶縁層、 44は入力ゲート、 45は転送ゲート、 ５はInバンプ、 ６はAuとInの合金層 である。1 (1) to (3) are substrate cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a substrate cross-sectional view schematically illustrating the configuration of an infrared detecting hybrid semiconductor device according to the present invention. Is. In the figure, 1 is a first semiconductor chip, an HgCdTe substrate, 11 is a p-type HgCdTe substrate, 12 is an n-type HgCdTe region, 13 is an insulating layer, 2 is an In bump, 3 is an alloy forming metal Au layer, and 4 is The second semiconductor chip is a Si substrate, 41 is a p-type Si substrate, 42 is an n-type Si region, 43 is an insulating layer, 44 is an input gate, 45 is a transfer gate, 5 is an In bump, 6 is an alloy of Au and In It is a layer.

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】第１の半導体チップ（１）上に形成された
インジウム（In）、またはインジウムを含む合金よりな
るバンプ（２）を、 インジウムの融点より低い温度でインジウムと合金をつ
くる合金形成用金属層（３）を介在させて、 第２の半導体チップ（４）のバンプ（５）に接触させ、
加熱して両半導体チップ（１）と（４）を結合してなる ことを特徴とする半導体装置。1. An alloy for forming a bump (2) made of indium (In) or an alloy containing indium formed on a first semiconductor chip (1) with indium at a temperature lower than the melting point of indium. The metal layer (3) for contact with the bump (5) of the second semiconductor chip (4),
A semiconductor device, characterized by comprising heating and combining both semiconductor chips (1) and (4). 【請求項２】前記いずれかの半導体チップ（１）、また
は（４）が水銀カドミウムテルル（HgCdTe）結晶よりな
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。2. The semiconductor device according to claim 1, wherein any one of the semiconductor chips (1) or (4) is made of mercury cadmium tellurium (HgCdTe) crystal. 【請求項３】前記合金形成用金属層（３）が金（Au）よ
りなることを特徴とする特許請求の範囲第１項記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the alloy forming metal layer (3) is made of gold (Au).
JP60058904A 1985-03-22 1985-03-22 Semiconductor device Expired - Lifetime JPH0744251B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60058904A JPH0744251B2 (en) 1985-03-22 1985-03-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60058904A JPH0744251B2 (en) 1985-03-22 1985-03-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61216455A JPS61216455A (en) 1986-09-26
JPH0744251B2 true JPH0744251B2 (en) 1995-05-15

Family

ID=13097788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60058904A Expired - Lifetime JPH0744251B2 (en) 1985-03-22 1985-03-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0744251B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026718B1 (en) 1998-09-25 2006-04-11 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
WO2005060011A1 (en) 2003-12-16 2005-06-30 National University Corporation Shizuoka University Wide range energy radiation detector and manufacturing method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136349A (en) * 1981-02-16 1982-08-23 Mitsubishi Electric Corp Semiconductor device
JPS59112652A (en) * 1982-12-17 1984-06-29 Fujitsu Ltd Semiconductor image pickup device

Also Published As

Publication number Publication date
JPS61216455A (en) 1986-09-26

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