JPH07321864A - Agc circuit for dual mode cellular mobile equipment - Google Patents
Agc circuit for dual mode cellular mobile equipmentInfo
- Publication number
- JPH07321864A JPH07321864A JP6113120A JP11312094A JPH07321864A JP H07321864 A JPH07321864 A JP H07321864A JP 6113120 A JP6113120 A JP 6113120A JP 11312094 A JP11312094 A JP 11312094A JP H07321864 A JPH07321864 A JP H07321864A
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- voltage
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- 230000001413 cellular effect Effects 0.000 title claims description 7
- 230000009977 dual effect Effects 0.000 title description 5
- 238000001514 detection method Methods 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
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- Circuits Of Receivers In General (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はディジタル／アナログモ
ード兼用のデュアルモードセルラー移動機のＡＧＣ回路
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AGC circuit for a dual mode cellular mobile unit which is used for both digital and analog modes.
【０００２】[0002]
【従来の技術】図３は第１の従来のデュアルモードセル
ラー移動機のＡＧＣ回路を示すブロック図であり、ディ
ジタルモード時にはπ／４・ＱＰＳＫ、アナログモード
時にはＦＭ波を受信する。2. Description of the Related Art FIG. 3 is a block diagram showing an AGC circuit of a first conventional dual mode cellular mobile unit, which receives .pi. / 4.QPSK in a digital mode and FM waves in an analog mode.
【０００３】図３において、１は図示しない前段の受信
部からの中間周波数信号を入力する可変利得増幅器、２
は直交検波回路、４はＡ／Ｄ変換器、５は復調器であ
り、これ等は順次直列に接続され、直交検波回路２には
局部発振器３が接続されている。６はログアンプ、７は
基準レベル設定器、８は比較器であり、上記可変利得増
幅器１の利得を制御する制御回路９を構成している。In FIG. 3, reference numeral 1 is a variable gain amplifier for inputting an intermediate frequency signal from a receiving section at the preceding stage (not shown), and 2
Is a quadrature detection circuit, 4 is an A / D converter, 5 is a demodulator, which are sequentially connected in series, and a local oscillator 3 is connected to the quadrature detection circuit 2. Reference numeral 6 is a log amp, 7 is a reference level setter, and 8 is a comparator, which constitutes a control circuit 9 for controlling the gain of the variable gain amplifier 1.
【０００４】次に動作について説明する。中間周波数信
号は可変利得増幅器１で増幅され、直交検波回路２にお
いて、局部発振器３からの局部発振周波数で直交検波さ
れ、ベースバンド信号であるＩ信号とＱ信号に変換され
る。Ｉ信号とＱ信号はＡ／Ｄ変換器４でディジタル信号
に変換され、ＤＳＰ等で構成される復調器５に入力され
る。Next, the operation will be described. The intermediate frequency signal is amplified by the variable gain amplifier 1, quadrature detected by the quadrature detection circuit 2 at the local oscillation frequency from the local oscillator 3, and converted into I and Q signals which are baseband signals. The I signal and the Q signal are converted into digital signals by the A / D converter 4 and input to the demodulator 5 composed of a DSP or the like.
【０００５】復調器５は入力されたＩ信号及びＱ信号の
ディジタル値から、ディジタルモード時はディジタルデ
ータを復調し、アナログモード時はオーディオ波形（音
声）を復調する。この時、復調器５は復調信号の振幅が
一定でないと、正確に動作できない。The demodulator 5 demodulates digital data from the input digital values of the I and Q signals in the digital mode and demodulates an audio waveform (voice) in the analog mode. At this time, the demodulator 5 cannot operate correctly unless the amplitude of the demodulated signal is constant.
【０００６】一方、ログアンプ６は可変利得増幅器１で
増幅された中間周波数信号のレベルを検出し、この検出
したレベルを表す電圧値を出力する。比較器８はこの電
圧値と基準レベル設定器７で設定された基準電圧値とを
比較し、中間周波数信号のレベルが一定になるよう可変
利得増幅器１の利得を制御する。On the other hand, the log amplifier 6 detects the level of the intermediate frequency signal amplified by the variable gain amplifier 1 and outputs a voltage value representing the detected level. The comparator 8 compares this voltage value with the reference voltage value set by the reference level setting device 7, and controls the gain of the variable gain amplifier 1 so that the level of the intermediate frequency signal becomes constant.
【０００７】この第１の従来例では、レベル検出を中間
周波数信号からログアンプ６によって検出しているが、
中間周波数は周波数が高く、ログアンプ６は回路構成が
複雑となり、回路スペースが大きくかつ消費電流も多く
なる。In the first conventional example, the level detection is detected by the log amplifier 6 from the intermediate frequency signal.
The intermediate frequency has a high frequency, the circuit configuration of the log amp 6 is complicated, the circuit space is large, and the current consumption is large.
【０００８】図４はレベル検出をベースバンド信号であ
るＩ信号から検出する第２の従来例を示すもので、前記
図３における制御回路９の構成要素であるログアンプ６
の代わりにレベル検出器１０を用いて制御回路１１を構
成したもので、上記レベル検出器１０は直交検波回路２
から出力するＩ信号をピーク検波し、｜Ｉ｜のピーク値
を検出することによってレベル検出を行っている。FIG. 4 shows a second conventional example in which level detection is performed from an I signal which is a baseband signal. A log amplifier 6 which is a constituent element of the control circuit 9 shown in FIG.
The control circuit 11 is constructed by using the level detector 10 instead of the level detector 10.
The level detection is performed by detecting the peak of the I signal output from the detector and detecting the peak value of | I |.
【０００９】しかし、この第２の従来例においては、デ
ィジタルモード時は無変調にはならないが、アナログモ
ード時は無変調となる。すなわち、ＦＭ波の復調波Ｓ
（ｔ）は Ｓ（ｔ）＝√（Ｉ2 ＋Ｑ2 ） ｃｏｓ｜θ（ｔ）＋△ω
（ｔ）｜ ここで、θ（ｔ）：変調成分，△ω（ｔ）：受信器の周
波数ずれ成分 又、Ｉ＝ｃｏｓ｜θ（ｔ）＋△ω（ｔ）｜，Ｑ＝Ａｓｉ
ｎ｜θ（ｔ）＋△ω（ｔ）｜ ここでＡ：復調波の振幅 従って、正しい復調波の振幅は√（Ｉ2 ＋Ｑ2 ）である
が、√（Ｉ2 ＋Ｑ2 ）の検出を行うのは非常に難しく、
実際上、回路を構成することも非常に困難である。そこ
で、回路の構成が簡単な｜Ｉ｜のピーク値を検出して復
調波の振幅を検出している。However, in the second conventional example, no modulation occurs in the digital mode, but no modulation occurs in the analog mode. That is, the demodulated wave S of the FM wave
(T) is S (t) = √ (I 2 + Q 2 ) cos | θ (t) + Δω
(T) | Here, θ (t): modulation component, Δω (t): receiver frequency shift component, and I = cos | θ (t) + Δω (t) |, Q = Asi
n | θ (t) + Δω (t) | where A: amplitude of demodulated wave Therefore, the correct amplitude of demodulated wave is √ (I 2 + Q 2 ), but √ (I 2 + Q 2 ) is detected. Very difficult to do,
In practice, it is also very difficult to construct a circuit. Therefore, the amplitude of the demodulated wave is detected by detecting the peak value of | I | whose circuit configuration is simple.
【００１０】しかし、θ（ｔ）≒０すなわち受信周波数
のずれが少ない時は｜Ｉ｜＝Ａとなる機会が少なくな
り、又、｜Ｉ｜のピーク検波の時定数は制御回路１１の
追従速度の要求により決定され、ピーク検波の時定数を
大きくすることはできない為、正確な｜Ｉ｜のピーク値
が検出されず、実際より小さな値となる。However, when θ (t) ≈0, that is, when the deviation of the receiving frequency is small, the chance that | I | = A is small, and the time constant of the peak detection of | I | is the following speed of the control circuit 11. The peak constant of the peak detection cannot be increased, so that an accurate peak value of | I | is not detected and is smaller than the actual value.
【００１１】従って、可変利得増幅器１は正確に制御さ
れず、復調信号の振幅が大きくなってしまうという不具
合があった。Therefore, the variable gain amplifier 1 is not accurately controlled, and the amplitude of the demodulated signal becomes large.
【００１２】[0012]
【発明が解決しようとする課題】従来のデュアルモード
セルラー移動機のＡＧＣ回路は以上のように構成されて
いるので、レベル検出を中間周波数でログアンプ６を使
用して行う第１の従来例は、ログアンプ６の回路は構成
が複雑となり、コストがかかり、回路スペースが大き
く、かつ消費電流も多いという問題点があった。Since the AGC circuit of the conventional dual mode cellular mobile unit is configured as described above, the first conventional example in which the level detection is performed by using the log amp 6 at the intermediate frequency is as follows. However, the circuit of the log amplifier 6 has a complicated structure, is costly, has a large circuit space, and consumes a large amount of current.
【００１３】一方、レベル検出をベースバンド信号であ
るＩ信号で行う第２の従来例は、√（Ｉ2 ＋Ｑ2 ）の正
確な振幅検出の回路は実現不可能であり、簡単で実現可
能な｜Ｉ｜のピーク値を検出する回路では、アナログモ
ード時の無変調時に正確な制御ができないという問題点
があった。On the other hand, in the second conventional example in which the level detection is performed by the I signal which is the baseband signal, a circuit for accurate amplitude detection of √ (I 2 + Q 2 ) cannot be realized, and it can be realized easily. The circuit for detecting the peak value of | I | has a problem that accurate control cannot be performed during no modulation in the analog mode.
【００１４】又、第１、第２の従来例とも基準レベル設
定器や比較器を必要とし、コストがかかり、回路スペー
スも必要であり、消費電流も多く、携帯用の小型セルラ
ー移動機には適さないという問題点もあった。Further, both the first and second conventional examples require a reference level setting device and a comparator, which is costly, requires a circuit space, consumes a large amount of current, and is a portable small cellular mobile device. There was also the problem that it was not suitable.
【００１５】本発明は上記のような従来の問題点を解消
することを課題になされたもので、簡単な回路構成で、
実装スペースが小さく、少ない消費電力で正確に復調信
号の振幅を検出し、ＡＧＣ回路を制御することを目的と
する。The present invention has been made to solve the above-mentioned conventional problems, and has a simple circuit configuration.
An object is to accurately detect the amplitude of a demodulated signal and control the AGC circuit with a small mounting space and low power consumption.
【００１６】[0016]
【課題を解決するための手段】本発明に係るデュアルモ
ードセルラー移動機のＡＧＣ回路は、中間周波数信号を
増幅する可変利得増幅器と、前記中間周波数信号を直交
検波してＩ信号、Ｑ信号を出力する直交検波回路と、こ
の検波されたＩ信号、Ｑ信号をディジタル値に変換する
Ａ／Ｄ変換器と、前記Ｉ，Ｑ信号のディジタル値からデ
ータを復調するとともに√（Ｉ2 ＋Ｑ2 ）を計算して振
幅を検出すディジタル信号処理器と、前記ディジタル信
号処理器の計算値に基づく出力電圧値により復調信号の
振幅が一定となるよう上記可変利得増幅器の利得を制御
する制御回路とを備えたものである。An AGC circuit for a dual mode cellular mobile unit according to the present invention includes a variable gain amplifier for amplifying an intermediate frequency signal and quadrature detection of the intermediate frequency signal to output an I signal and a Q signal. A quadrature detection circuit, an A / D converter for converting the detected I and Q signals into digital values, demodulating data from the digital values of the I and Q signals, and √ (I 2 + Q 2 ) A digital signal processor for calculating and detecting the amplitude, and a control circuit for controlling the gain of the variable gain amplifier so that the amplitude of the demodulated signal becomes constant by the output voltage value based on the calculated value of the digital signal processor It is a thing.
【００１７】[0017]
【作用】本発明におけるＡＧＣ回路は、ディジタル信号
処理回路によってデータの復調と復調信号の振幅検出を
行うことにより、可変利得増幅器の制御回路を簡略化す
ることができる。その結果、部品点数が大幅に削減で
き、コストダウンを図り、回路スペースをも減らし、消
費電流も減らすことができる。In the AGC circuit of the present invention, the control circuit of the variable gain amplifier can be simplified by demodulating the data and detecting the amplitude of the demodulated signal by the digital signal processing circuit. As a result, the number of parts can be significantly reduced, cost can be reduced, circuit space can be reduced, and current consumption can be reduced.
【００１８】[0018]
実施例１．以下、本発明の実施例を図面について説明す
る。Example 1. Embodiments of the present invention will be described below with reference to the drawings.
【００１９】図１において、１は可変利得増幅器、２は
直交検波回路、３は局部発振器、４はＡ／Ｄ変換器、１
２はディジタル信号処理器であり、これらは順次直列に
接続されており、上記直交検波回路２には局部発振器３
が接続され、ディジタル信号処理器１２と可変利得増幅
器１との接続路には、制御回路を構成する抵抗１３、コ
ンデンサ１４が設けられている。In FIG. 1, 1 is a variable gain amplifier, 2 is a quadrature detection circuit, 3 is a local oscillator, 4 is an A / D converter, 1
Reference numeral 2 denotes a digital signal processor, which are sequentially connected in series. The quadrature detection circuit 2 includes a local oscillator 3
, And a resistor 13 and a capacitor 14 forming a control circuit are provided in the connection path between the digital signal processor 12 and the variable gain amplifier 1.
【００２０】次に本実施例の動作を説明する。ディジタ
ル信号処理器１２はＡ／Ｄ変換器４よりＩ信号とＱ信号
のディジタル値を取り込み、ディジタルモード時はディ
ジタルデータを、アナログモード時は音声波形を復調出
力する。Next, the operation of this embodiment will be described. The digital signal processor 12 takes in the digital values of the I and Q signals from the A / D converter 4 and demodulates and outputs digital data in the digital mode and a voice waveform in the analog mode.
【００２１】また、ディジタル信号処理器１２はＩ信号
とＱ信号のディジタル値から√（Ｉ2 ＋Ｑ2 ）の値を計
算し復調信号の振幅を検出する。この計算値から可変利
得増幅器１の利得を増幅するか、減らすかを判断し、こ
の判断結果に応じてＨ（高）又はＬ（低）の電圧を出力
する。The digital signal processor 12 calculates the value of √ (I 2 + Q 2 ) from the digital values of the I and Q signals and detects the amplitude of the demodulated signal. Based on this calculated value, it is determined whether to amplify or reduce the gain of the variable gain amplifier 1, and an H (high) or L (low) voltage is output according to the result of this determination.
【００２２】このＨ又はＬの電圧は抵抗１３、コンデン
サ１４でフィルタリングされ、このＨとＬの電圧のデュ
ーティ比に応じた直流電圧となる。この直流電圧は可変
利得増幅器１に入力し復調信号の振幅が一定になるよう
可変利得増幅器を制御する。この時、復調信号の振幅は
√（Ｉ2 ＋Ｑ2 ）で計算されるため、正確に求めること
ができ、従って、アナログモード時で無変調でかつ受信
機の周波数のずれがない時でも正確に可変利得増幅器１
が制御できる。The H or L voltage is filtered by the resistor 13 and the capacitor 14, and becomes a DC voltage corresponding to the duty ratio of the H and L voltages. This DC voltage is input to the variable gain amplifier 1 to control the variable gain amplifier so that the amplitude of the demodulated signal becomes constant. At this time, since the amplitude of the demodulated signal is calculated by √ (I 2 + Q 2 ), it can be accurately obtained. Therefore, even if there is no modulation in the analog mode and there is no frequency shift of the receiver, Variable gain amplifier 1
Can be controlled.
【００２３】上記のようにディジタル信号処理器１２は
データ及び音声の復調と復調信号の振幅検出の両方を行
うため、外付部品は抵抗１３とコンデンサ１４を付加す
るだけでよく、可変利得増幅器１の制御回路の構成が大
幅に削減され、コスト、回路スペース、消費電流が削減
される。As described above, since the digital signal processor 12 both demodulates data and voice and detects the amplitude of the demodulated signal, external parts only need to add the resistor 13 and the capacitor 14, and the variable gain amplifier 1 The configuration of the control circuit is significantly reduced, and cost, circuit space, and current consumption are reduced.
【００２４】実施例２．図２は本発明の第２の実施例を
示す回路図であり、前記図１と同一部分には同一符号を
付して重複説明を省略する。本実施例はディジタル信号
処理器１２からの出力電圧値を、制御回路としてのＤ／
Ａ変換器１５でアナログ信号に変換して可変利得増幅器
１に与えているもので、前記実施例１とは制御回路の構
成が異なるだけであり、実質的に実施例１と同一の作用
効果が得られる。Example 2. FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The same parts as those in FIG. In this embodiment, the output voltage value from the digital signal processor 12 is set to D / as a control circuit.
The A-converter 15 converts the analog signal and gives it to the variable gain amplifier 1. Only the configuration of the control circuit is different from that of the first embodiment, and substantially the same effect as the first embodiment is obtained. can get.
【００２５】[0025]
【発明の効果】以上のように、本発明によれば、ディジ
タル信号処理回路によってデータの復調と復調信号の振
幅検出を行うことにより、可変利得増幅器の制御回路を
簡略化することができる。その結果、部品点数が大幅に
削減でき、コストダウンを図り、回路スペースをも減ら
し、消費電流も減らすことができるなどの効果がある。As described above, according to the present invention, the control circuit of the variable gain amplifier can be simplified by demodulating the data and detecting the amplitude of the demodulated signal by the digital signal processing circuit. As a result, the number of parts can be significantly reduced, the cost can be reduced, the circuit space can be reduced, and the current consumption can be reduced.
【図１】本発明の第１の実施例を示すブロック図であ
る。FIG. 1 is a block diagram showing a first embodiment of the present invention.
【図２】本発明の第２の実施例２を示すブロック図であ
る。FIG. 2 is a block diagram showing a second embodiment 2 of the present invention.
【図３】従来の第１のＡＧＣ回路を示すブロック図であ
る。FIG. 3 is a block diagram showing a first conventional AGC circuit.
【図４】従来の第２のＡＧＣ回路を示すブロック図であ
る。FIG. 4 is a block diagram showing a second conventional AGC circuit.
１ 可変利得増幅器 ２ 直交検波器 ４ Ａ／Ｄ変換器 １２ ディジタル信号処理器 １３ 抵抗（制御回路） １４ コンデンサ（制御回路） １５ Ｄ／Ａ変換器（制御回路） 1 Variable Gain Amplifier 2 Quadrature Detector 4 A / D Converter 12 Digital Signal Processor 13 Resistance (Control Circuit) 14 Capacitor (Control Circuit) 15 D / A Converter (Control Circuit)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０４Ｂ 7/26 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H04B 7/26
Claims (1)
器と、前記中間周波数信号を直交検波してＩ信号、Ｑ信
号を出力する直交検波回路と、この検波されたＩ信号、
Ｑ信号をディジタル値に変換するＡ／Ｄ変換器と、前記
Ｉ，Ｑ信号のディジタル値からデータを復調するととも
に√（Ｉ2 ＋Ｑ2 ）を計算して振幅を検出するディジタ
ル信号処理器と、前記ディジタル信号処理器の計算値に
基づく出力電圧値により復調信号の振幅が一定となるよ
う上記可変利得増幅器の利得を制御する制御回路とを備
えたデュアルモードセルラー移動機のＡＧＣ回路。1. A variable gain amplifier for amplifying an intermediate frequency signal, a quadrature detection circuit for orthogonally detecting the intermediate frequency signal and outputting an I signal and a Q signal, and the detected I signal,
An A / D converter for converting the Q signal into a digital value, a digital signal processor for demodulating data from the digital values of the I and Q signals and calculating √ (I 2 + Q 2 ) to detect the amplitude, An AGC circuit for a dual-mode cellular mobile device, comprising: a control circuit that controls the gain of the variable gain amplifier so that the amplitude of the demodulated signal becomes constant according to the output voltage value based on the calculated value of the digital signal processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6113120A JPH07321864A (en) | 1994-05-26 | 1994-05-26 | Agc circuit for dual mode cellular mobile equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6113120A JPH07321864A (en) | 1994-05-26 | 1994-05-26 | Agc circuit for dual mode cellular mobile equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07321864A true JPH07321864A (en) | 1995-12-08 |
Family
ID=14604033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6113120A Pending JPH07321864A (en) | 1994-05-26 | 1994-05-26 | Agc circuit for dual mode cellular mobile equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07321864A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08163195A (en) * | 1994-12-06 | 1996-06-21 | Nec Corp | Reception circuit using quadrature demodulator |
-
1994
- 1994-05-26 JP JP6113120A patent/JPH07321864A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08163195A (en) * | 1994-12-06 | 1996-06-21 | Nec Corp | Reception circuit using quadrature demodulator |
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