JPH0727701Y2 - Wideband PLL circuit - Google Patents
Wideband PLL circuitInfo
- Publication number
- JPH0727701Y2 JPH0727701Y2 JP1988080502U JP8050288U JPH0727701Y2 JP H0727701 Y2 JPH0727701 Y2 JP H0727701Y2 JP 1988080502 U JP1988080502 U JP 1988080502U JP 8050288 U JP8050288 U JP 8050288U JP H0727701 Y2 JPH0727701 Y2 JP H0727701Y2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- vco
- divider
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Superheterodyne Receivers (AREA)
- Transmitters (AREA)
Description
【考案の詳細な説明】 （産業上の利用分野） 本考案はPLLを用いた周波数シンセサイザに係わり、特
に無線電話装置等の高周波源に使用するPLL回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a frequency synthesizer using a PLL, and more particularly to a PLL circuit used for a high frequency source such as a wireless telephone device.
（従来の技術） 従来無線電話装置等で用いる高周波源としては電圧制御
発振器（以下「VCO」と呼ぶ）を用い、VCOの発振周波数
を決定するコイルやコンデンサをダイオード等の電子的
スイッチにより切り換えて広帯域化を図っていた。(Prior Art) A voltage-controlled oscillator (hereinafter referred to as "VCO") is used as a high-frequency source used in a conventional radiotelephone device, etc., and a coil or capacitor that determines the oscillation frequency of the VCO is switched by an electronic switch such as a diode. The band was widened.
（考案が解決しようとする課題） しかし乍らこのようなVCOでは切換回路の部品数が多
く、又コイル等の大形の部品が複数使用されているため
ユニットの小型化、低価格化が困難であった。(Problems to be solved by the invention) However, in such a VCO, it is difficult to reduce the size and cost of the unit because the switching circuit has a large number of parts and a plurality of large parts such as coils are used. Met.
又切換回路での損失が大きいため同調回路のＱが低下し
C/Nの良好な発振器が得られなかった。Also, since the loss in the switching circuit is large, the Q of the tuning circuit decreases.
A good oscillator of C / N could not be obtained.
（課題を解決するための手段） 本考案はこれらの欠点を解決するため、PLLを構成するV
COの発振周波数決定素子のコイルやコンデンサを固定と
し、VCOの後に該VCOの発振出力を分周する可変分周器
と、該分周出力を逓倍する逓倍器とを付加し、この逓倍
器の出力を高周波源としたものである。この可変分周器
の分周数を変化させることにより広帯域に亘り高C/Nの
出力を得ることができる。以下実施例につき図面により
詳細に説明する。(Means for Solving the Problems) In order to solve these drawbacks, the present invention uses a V that constitutes a PLL.
A coil and a capacitor of the oscillation frequency determining element of CO are fixed, a variable frequency divider that divides the oscillation output of the VCO after the VCO, and a multiplier that multiplies the divided output are added, and The output is used as a high frequency source. By changing the frequency division number of this variable frequency divider, a high C / N output can be obtained over a wide band. Hereinafter, embodiments will be described in detail with reference to the drawings.
（実施例） 図は本考案の一実施例の構成図で、１は基準周波数発振
器、２は固定分周器、３は位相比較器、４はLPF（ロー
パスフィルタ）、５は電圧制御発振器（VCO）、６は第
２の分周器、７は逓倍器、８は第１の分周器である。(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a reference frequency oscillator, 2 is a fixed frequency divider, 3 is a phase comparator, 4 is an LPF (low pass filter), 5 is a voltage controlled oscillator ( VCO), 6 is a second frequency divider, 7 is a multiplier, and 8 is a first frequency divider.
同図において、基準周波数発振器１からの出力は固定分
周器２により適当な値の基準信号として位相比較器３の
一端子に加えられ、第１の分周器８の出力とそこで位相
比較される。誤差電圧はLPF4を経てVCO5の有する可変ダ
イオードに加えることによりVCO5の発振周波数を変化さ
せる。VCO5の出力は第２の分周器６を経て逓倍器７に加
わりその出力が高周波源となる。又、この出力は第１の
分周器８に入力し位相比較器３の他の端子に加えられて
PLL回路を構成する。In the figure, the output from the reference frequency oscillator 1 is applied to one terminal of the phase comparator 3 as a reference signal having an appropriate value by the fixed frequency divider 2, and the phase is compared therewith with the output of the first frequency divider 8. It The error voltage changes the oscillation frequency of VCO5 by being applied to the variable diode of VCO5 via LPF4. The output of VCO5 passes through the second frequency divider 6 and is applied to the multiplier 7, and its output becomes a high frequency source. Also, this output is input to the first frequency divider 8 and added to the other terminal of the phase comparator 3.
Configure the PLL circuit.
この構成において、いまVCO5の発振周波数をfV、そのロ
ックレンジをΔfV、第２の分周器６の分周数をＭ、逓倍
器の逓倍数をＰ（通常2n）とすれば、出力周波数f0はf0
＝P/MfVとなる。又分周数Ｍ＋1,M,M−１のときの出力の
周波数をf1，f2，f3とすればf1＝P/（Ｍ＋１）fV，f2＝
P/MfV，f3＝P/（Ｍ−１）fVとなる。In this configuration, if the oscillation frequency of VCO5 is f V , its lock range is Δf V , the frequency division number of the second frequency divider 6 is M, and the frequency multiplication number of the frequency multiplier is P (usually 2 n ), Output frequency f 0 is f 0
= P / Mf V Also, if the frequencies of the outputs at the frequency division numbers M + 1, M, M−1 are f 1 , f 2 , and f 3 , then f 1 = P / (M + 1) f V , f 2 =
P / Mf V , f 3 = P / (M−1) f V.
ここでfV／（Ｍ−１）−fV/M≦ΔfVとすると、分周数Ｍ
をＭ−1,M,M＋１と変えたとき出力の周波数f0は第１の
分周器８の分周数Ｎを変えることによって連続的にP/
（Ｍ＋１）fV−ΔfV/2からP/（Ｍ−１）fV＋ΔfV/2まで
変化し広帯域化される。ΔfV,M,Pを適当な値に設定する
ことによってさらに広帯域化が可能である。第１の分周
器８は従来行われていたように主として基準周波数と共
に帯域内の周波数ステップの細かさを決めるものであ
る。一例として、fV＝400MHz,ΔfV＝16MHz,M＝32,P＝12
とすればf0＝150MHzである。VCO5の発振周波数fVはロッ
クレンジが±8MHzであることから392〜408MHzである。
Ｍを27〜32まで変えた場合Ｍ＝27のときf0＝174.3〜18
1.3MHz,M＝28のときf0＝168.0〜174.8MHz,M＝29のときf
0＝162.2〜168.8MHz,M＝30のときf0＝156.8〜163.2MHz,
M＝31のときf0＝151.7〜157.9MHz,M＝32のときf0＝147.
0〜153.0MHzとなる。従って、147.0MHzから181.3MHzま
での34.3MHz幅の広帯域PLL回路が得られる。Ｍを64まで
にすると73.5MHzから181.3MHzとなり、その幅は107.8MH
zとなる。Here, if f V / (M-1) −f V / M ≦ Δf V , the frequency division number M
Is changed to M−1, M, M + 1, the output frequency f 0 is continuously changed to P / by changing the frequency division number N of the first frequency divider 8.
The band is changed from (M + 1) f V −Δf V / 2 to P / (M−1) f V + Δf V / 2 to broaden the band. A wider band can be achieved by setting Δf V , M and P to appropriate values. The first frequency divider 8 mainly determines the fineness of the frequency step within the band together with the reference frequency as is conventionally done. As an example, f V = 400 MHz, Δf V = 16 MHz, M = 32, P = 12
Then, f 0 = 150MHz. The oscillation frequency f V of VCO5 is 392 to 408 MHz because the lock range is ± 8 MHz.
When M is changed from 27 to 32 When M = 27 f 0 = 174.3 to 18
When 1.3MHz, M = 28 f 0 = 168.0 to 174.8MHz, M = 29 f
0 = 162.2 to 168.8MHz, M = 30 f 0 = 156.8 to 163.2MHz,
When M = 31, f 0 = 151.7 to 157.9 MHz, when M = 32, f 0 = 147.
It becomes 0-153.0MHz. Therefore, a wideband PLL circuit with a width of 34.3 MHz from 147.0 MHz to 181.3 MHz can be obtained. When M is up to 64, it goes from 73.5MHz to 181.3MHz, and its width is 107.8MH
It becomes z.
なお、本考案では、分周器の分周数を変えているので、
この分周数を大きくすることによって、VCOの発振周波
数を高くすることができ、コンデンサやコイルが小形と
なる。また、同時に発振周波数の変化範囲も狭くするこ
とができるので、この点でも高C/Nが達成できる。In this invention, since the frequency division number of the frequency divider is changed,
By increasing the frequency division number, the VCO oscillation frequency can be increased and the capacitors and coils can be made smaller. At the same time, the change range of the oscillation frequency can be narrowed, so that a high C / N can be achieved in this respect as well.
（考案の効果） 以上説明したように、発振周波数の決定素子であるコン
デンサやコイル等を変化させずに広帯域化が可能とな
り、かつ損失のある切換回路を使用しないので、またVC
Oの発振周波数が高くなると共に変化範囲も狭くなるの
で、ユニット小形化、低価格及び高C/Nが達成できる。
さらに本考案に使用する逓倍器は本出願人による単安定
マルチバイブレータを使用した逓倍器とすればコイル等
の大形部品は使用せずに済み一層小形化が可能となる。(Effect of the device) As described above, it is possible to widen the band without changing the capacitors and coils that are the elements that determine the oscillation frequency, and since no switching circuit with loss is used,
Since the oscillation frequency of O becomes higher and the range of change becomes narrower, it is possible to achieve unit miniaturization, lower cost, and higher C / N.
Further, if the multiplier used in the present invention is a multiplier using a monostable multivibrator of the present applicant, it is possible to further reduce the size without using large parts such as a coil.
図は本考案の一実施例の構成図を示す。 １……基準周波数発振器、３……位相比較器、４……LP
F、５……電圧制御発振器（VCO）、６……第２の分周
器、７……逓倍器、８……第１の分周器。The figure shows a block diagram of an embodiment of the present invention. 1 ... Reference frequency oscillator, 3 ... Phase comparator, 4 ... LP
F, 5 ... Voltage controlled oscillator (VCO), 6 ... Second frequency divider, 7 ... Multiplier, 8 ... First frequency divider.
Claims (1)
（３）、ローパスフィルタ（４）、電圧制御発振器（VC
O）（５）及び周波数シンセサイザの出力周波数を変化
させる可変分周形の第１の分周器（８）から成るPLL
（位相同期ループ）を用いた周波数シンセサイザにおい
て、前記VCOと前記周波数シンセサイザの出力端との間
に、前記VCOの発振出力を分周する可変分周形の第２の
分周器（６）と、該分周出力を逓倍し周波数シンセサイ
ザ出力とする逓倍器（７）とを設けて、前記第２の分周
器の分周数を変化させることにより広帯域の周波数シン
セサイザ出力を得ると共に前記逓倍器によりVCOの発振
周波数の変化幅を小さくすることを特徴とする広帯域PL
L回路。1. A reference frequency oscillator (1), a phase comparator (3), a low pass filter (4), a voltage controlled oscillator (VC).
O) (5) and a variable frequency division type first frequency divider (8) for changing the output frequency of the frequency synthesizer
In a frequency synthesizer using a (phase locked loop), a variable frequency division type second frequency divider (6) for dividing the oscillation output of the VCO between the VCO and the output terminal of the frequency synthesizer. And a multiplier (7) for multiplying the frequency division output to obtain a frequency synthesizer output, and changing the frequency division number of the second frequency divider to obtain a wide band frequency synthesizer output and the frequency multiplier. Wideband PL characterized by reducing the variation width of the VCO oscillation frequency by
L circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988080502U JPH0727701Y2 (en) | 1988-06-17 | 1988-06-17 | Wideband PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988080502U JPH0727701Y2 (en) | 1988-06-17 | 1988-06-17 | Wideband PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH021930U JPH021930U (en) | 1990-01-09 |
| JPH0727701Y2 true JPH0727701Y2 (en) | 1995-06-21 |
Family
ID=31305327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988080502U Expired - Lifetime JPH0727701Y2 (en) | 1988-06-17 | 1988-06-17 | Wideband PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727701Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4811417B2 (en) * | 2008-02-14 | 2011-11-09 | パナソニック株式会社 | Receiving device and electronic device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5027730U (en) * | 1973-07-07 | 1975-03-31 | ||
| JPS5676640A (en) * | 1979-11-27 | 1981-06-24 | Sanyo Electric Co Ltd | Receiver of frequency synthesizer system |
| JPS5719603A (en) * | 1980-07-11 | 1982-02-01 | Hitachi Ltd | Device for measuring corner |
| FR2510287B1 (en) * | 1981-07-24 | 1985-01-04 | Thomson Csf | RELATIVE BROADBAND FREQUENCY SYNTHESIZER |
-
1988
- 1988-06-17 JP JP1988080502U patent/JPH0727701Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH021930U (en) | 1990-01-09 |
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