JPH07201988A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07201988A JPH07201988A JP33725393A JP33725393A JPH07201988A JP H07201988 A JPH07201988 A JP H07201988A JP 33725393 A JP33725393 A JP 33725393A JP 33725393 A JP33725393 A JP 33725393A JP H07201988 A JPH07201988 A JP H07201988A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- mask
- forming
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、金配線を有する半導体
装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having gold wiring.
【０００２】[0002]
【従来の技術】従来の半導体装置の製造方法は、図２５
に示すように、半導体基板１上に多層配線構造を形成す
るために半導体基板１上に層間絶縁膜２を形成する。密
着金属として第１チタンタングステン合金膜１９および
主配線材料として第１金膜２０から構成される下層配線
の形成された半導体基板１上に、既知の手法であるＣＶ
Ｄ技術、フォトリソグラフィー技術、ドライエッチング
技術等を用いて、シリコン酸化膜、シリコン窒化膜及び
平坦化塗布膜より構成される厚さ０．５〜１．０μｍの
層間絶縁膜２１、０．４〜１．０μｍ径の層間接続孔２
２を形成する。2. Description of the Related Art A conventional semiconductor device manufacturing method is shown in FIG.
As shown in, an interlayer insulating film 2 is formed on the semiconductor substrate 1 to form a multilayer wiring structure on the semiconductor substrate 1. The CV, which is a known technique, is formed on the semiconductor substrate 1 on which the lower layer wiring composed of the first titanium-tungsten alloy film 19 as the adhesion metal and the first gold film 20 as the main wiring material is formed.
Using the D technique, the photolithography technique, the dry etching technique, etc., the interlayer insulating film 21 having a thickness of 0.5 to 1.0 μm and made of a silicon oxide film, a silicon nitride film, and a planarization coating film, 0.4 to Interlayer connection hole with a diameter of 1.0 μm 2
Form 2.
【０００３】更に、第２チタンタングステン合金膜２３
をＤ．Ｃ．マグネトロンスパッタ法を用いて成膜パワー
１．０〜５．０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒと
し、０．０５〜０．２μｍの厚みで、層間絶縁膜２１、
第１金膜２０上に形成する。第２チタンタングステン合
金膜２３の表面のメッキ液からの保護、密着性の改善及
びメッキ電流の供給を目的として、金、白金、パラジウ
ム等より構成されるメッキ下地膜２４を、Ｄ．Ｃ．マグ
ネトロンスパッタ法を用いて成膜ハーワー０．５〜１．
０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒの条件の下、０．
０１〜０．１μｍの厚みで第２チタンタングステン合金
膜２３上に形成する。Further, the second titanium-tungsten alloy film 23
D. C. Using the magnetron sputtering method, the film forming power is 1.0 to 5.0 kW, the film forming pressure is 2 to 10 mTorr, the thickness is 0.05 to 0.2 μm, and the interlayer insulating film 21 is formed.
It is formed on the first gold film 20. For the purpose of protecting the surface of the second titanium-tungsten alloy film 23 from a plating solution, improving adhesion, and supplying a plating current, a plating underlayer film 24 made of gold, platinum, palladium, or the like was used. C. Deposition harwa 0.5-1. Using the magnetron sputtering method.
Under the conditions of 0 kW and a film forming pressure of 2 to 10 mTorr, 0.
It is formed on the second titanium-tungsten alloy film 23 with a thickness of 01 to 0.1 μm.
【０００４】図２６に示すように、フォトリソグラフィ
ー技術を用いてフォトレジスト２５を１．０〜２．０μ
ｍの厚みでメッキ下地膜２４上に選択的に形成し、硫酸
金ナトリウム、硫酸、燐酸等より構成される電解金メッ
キ液を用い、メッキ下地膜２４を陰極、白金あるいはチ
タンに白金を被覆したメッシュ状電極を陽極として通電
し、メッキ温度３０〜６０℃、電流密度１〜４ｍＡ／ｃ
ｍ2 の条件の下で電解金メッキを行い、第２金膜２６を
０．５〜２．０μｍの厚みで選択的に形成する。第２金
膜２５は配線全体の電気抵抗の低減を目的として形成さ
れるものである。As shown in FIG. 26, a photo resist 25 is applied to form a photoresist 25 of 1.0 to 2.0 .mu.m.
A mesh formed by selectively forming a thickness of m on the plating base film 24 and using an electrolytic gold plating solution composed of sodium gold sulfate, sulfuric acid, phosphoric acid, etc. to coat the plating base film 24 with a cathode, platinum or titanium with platinum. Current is used as a positive electrode with a plate-shaped electrode as the anode, plating temperature 30 to 60 ° C., current density 1 to 4 mA / c
Electrolytic gold plating is performed under the condition of m 2 to selectively form the second gold film 26 with a thickness of 0.5 to 2.0 μm. The second gold film 25 is formed for the purpose of reducing the electric resistance of the entire wiring.
【０００５】図２７に示すように、有機溶剤を用いてフ
ォトレジスト２５を除去した後、アルゴンガスをソース
としたミリング法、ＣＦ4 ，ＳＦ6 をエッチングガスと
した反応性イオンエッチング法により、第２金膜２６を
エッチングマスクとして下層の第２チタンタングステン
合金２３およびメッキ下地膜の不要部分のみを除去し
て、第２チタンタングステン合金２３、メッキ下地膜２
４、第２金膜２６より構成される半導体集積回路装置の
金属配線を形成していた。（例えば、特開昭６３−２６
９５４６号を参照）。As shown in FIG. 27, after removing the photoresist 25 using an organic solvent, a milling method using argon gas as a source and a reactive ion etching method using CF 4 and SF 6 as an etching gas are used to remove the photoresist. The second gold-tungsten alloy 23 and the plating base film 2 are removed by removing only unnecessary portions of the second titanium-tungsten alloy 23 and the plating base film, which are lower layers, by using the gold film 26 as an etching mask.
4. The metal wiring of the semiconductor integrated circuit device composed of the second gold film 26 was formed. (For example, JP-A-63-26
9546).
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
配線形成方法においては、層間接続孔２２の金属膜埋設
性がスパッタ金膜やメッキ金膜の段差被覆性に依存して
おり、これらの段差被覆性は充分ではない。However, in the conventional wiring forming method, the metal film burying property of the interlayer connection hole 22 depends on the step coverage of the sputtered gold film or the plated gold film. The sex is not enough.
【０００７】従って、微細な層間接続孔２２をメッキ金
膜により完全に埋設することがむずかしいことから、金
属配線の安定した良好な電気特性や高い長期信頼性が得
にくい。したがって、高い長期信頼性と安定した特性を
有する半導体装置を得にくくなり、さらにその製造過程
での高い歩留は実現できないとう問題がある。Therefore, it is difficult to completely fill the fine inter-layer connection holes 22 with the plated gold film, so that it is difficult to obtain stable and good electrical characteristics and high long-term reliability of the metal wiring. Therefore, it is difficult to obtain a semiconductor device having high long-term reliability and stable characteristics, and there is a problem that a high yield in the manufacturing process cannot be realized.
【０００８】[0008]
【課題を解決するための手段】本発明によれば、下層に
半導体素子、電極及び金配線の金膜（４）が形成された
半導体基板（１）上に層間絶縁膜（５）を形成する工程
と、該層間絶縁膜上に第１導電膜（６）を形成する工程
と、前記第１導電膜上に第１マスク膜（７）を形成する
工程と、該第１マスク膜、前記第１導電膜及び前記層間
絶縁膜に接続孔（９）を形成する工程と、前記第１マス
ク膜及び前記接続孔上に第２導電膜（１０）を形成する
工程と、該第２導電膜上に第２マスク膜（１１）を形成
する工程と、平坦部と前記接続孔底部の前記第２マスク
膜を除去し前記接続孔側壁部の前記第２マスク膜のみを
残す工程と、平坦部と前記接続孔底部の前記第２導電膜
を除去し前記平坦部に於て前記第１マスク膜を露出させ
ると共に前記接続孔底部に於て下層金配線の前記金膜を
露出させる工程と、前記接続孔側壁部の前記第２マスク
膜のみを除去する工程と、前記第１マスク膜と前記第２
導電膜をマスクとし、前記第１導電膜と前記第２導電膜
を電流経路とし、前記接続孔底部に露出した前記下層配
線の前記金膜を種付け層として、電解金メッキ法を用い
て前記接続孔内に第３導電膜（１２）を形成する工程を
有することを特徴とした半導体装置の製造方法が得られ
る。According to the present invention, an interlayer insulating film (5) is formed on a semiconductor substrate (1) having a semiconductor element, an electrode and a gold film (4) of gold wiring formed on the lower layer. A step, a step of forming a first conductive film (6) on the interlayer insulating film, a step of forming a first mask film (7) on the first conductive film, the first mask film, the A step of forming a connection hole (9) in the first conductive film and the interlayer insulating film; a step of forming a second conductive film (10) on the first mask film and the connection hole; and on the second conductive film. A step of forming a second mask film (11) on the flat portion, a step of removing the second mask film on the flat portion and the bottom portion of the connection hole and leaving only the second mask film on the sidewall portion of the connection hole, and a flat portion. The second conductive film at the bottom of the connection hole is removed to expose the first mask film at the flat part and the connection is made. A step of the bottom Te at expose the gold film of the lower gold wire, the connection comprising the steps of only removing the second mask layer of the hole side wall portion, wherein the first mask layer second
Using the conductive film as a mask, the first conductive film and the second conductive film as a current path, and using the gold film of the lower layer wiring exposed at the bottom of the connection hole as a seeding layer, the connection hole is formed by electrolytic gold plating. A method of manufacturing a semiconductor device is obtained which has a step of forming a third conductive film (12) therein.
【０００９】また、第１マスクを除去した後に前記第１
導電膜と前記第２導電膜をマスクとして電解金メッキ膜
により前記接続孔内に前記第３導電膜を形成してもよ
い。Further, after removing the first mask, the first mask is removed.
The third conductive film may be formed in the connection hole by an electrolytic gold plating film using the conductive film and the second conductive film as a mask.
【００１０】[0010]
［実施例１］次に本発明について図面を参照して第１の
実施例を説明する。[Embodiment 1] Next, a first embodiment of the present invention will be described with reference to the drawings.
【００１１】図１に示す通り、半導体基板１上に層間絶
縁膜２が形成されており、層間絶縁膜２上に密着金属と
してチタンタングステン合金あるいはタンタルを用いた
導電膜３、及びこの導電膜３上に主導電材料として金を
用いた導電膜（金膜）４から構成される下層金配線が形
成されている。As shown in FIG. 1, an interlayer insulating film 2 is formed on a semiconductor substrate 1, and a conductive film 3 using a titanium tungsten alloy or tantalum as an adhesion metal on the interlayer insulating film 2, and this conductive film 3. A lower layer gold wiring formed of a conductive film (gold film) 4 using gold as a main conductive material is formed on the top.
【００１２】図２に示すように、ＣＶＤ技術、ドライエ
ッチング技術等を用いて、シリコン酸化膜、シリコン窒
化膜、平坦化塗布膜より構成される厚さ０．５〜１．０
μｍの層間絶縁膜５を層間絶縁膜２及び導電膜４上に形
成する。続いて、電解金メッキ工程における電流経路と
してタンタルより構成される導電膜（第１導電膜）６
を、ＤＣマグネトロンスパッタ法を用いて成膜パワー
１．０〜５．０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒと
し、０．０５〜０．２μｍの厚みで、層間絶縁膜５上に
形成する。続いて、導電膜６上にプラズマＣＶＤ技術を
用いて０．０５〜０．２μｍの厚みでプラズマ窒化膜
（第１マスク膜）７を形成する。但し、導電膜６の低抵
抗化のために導電膜６をタンタル窒化膜とタンタルの積
層構造としてもよい。As shown in FIG. 2, a thickness of 0.5 to 1.0 composed of a silicon oxide film, a silicon nitride film, and a flattening coating film is formed by using a CVD technique, a dry etching technique, or the like.
A μm interlayer insulating film 5 is formed on the interlayer insulating film 2 and the conductive film 4. Subsequently, a conductive film (first conductive film) 6 made of tantalum as a current path in the electrolytic gold plating process
Is formed on the interlayer insulating film 5 by DC magnetron sputtering with a film forming power of 1.0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr and a thickness of 0.05 to 0.2 μm. Then, a plasma nitride film (first mask film) 7 is formed on the conductive film 6 with a thickness of 0.05 to 0.2 μm by the plasma CVD technique. However, the conductive film 6 may have a laminated structure of a tantalum nitride film and tantalum in order to reduce the resistance of the conductive film 6.
【００１３】図３に示すように、所望の位置が開口して
いるフォトレジスト８をマスクとして、ＳＦ4 ，Ｏ2 ，
Ｃｌ2 などを反応ガスとした異方性ドライエッチングを
行い、プラズマ窒化膜７、導電膜６および層間絶縁膜５
に層間接続孔９を形成し、下層金配線の導電膜４を露出
させる。As shown in FIG. 3, using the photoresist 8 having openings at desired positions as a mask, SF 4 , O 2 ,
Anisotropic dry etching is performed using Cl 2 or the like as a reaction gas to perform plasma nitride film 7, conductive film 6 and interlayer insulating film 5.
An inter-layer connection hole 9 is formed in the film to expose the conductive film 4 of the lower layer gold wiring.
【００１４】図４に示すようにフォトレジスト８を除去
した後、電解金メッキ工程における導電膜６と導電膜４
との間の電流経路としてタンタルより構成される導電膜
（第２導電膜）１０を、ＤＣマグネトロンスパッタ法を
用いて成膜パワー１．０〜５．０ｋＷ、成膜圧力２〜１
０ｍＴｏｒｒとし、０．０５〜０．２μｍの厚みで形成
する。続いて、導電膜１０上にプラズマＣＶＤ法を用い
て０．０５〜０．２μｍの厚みでプラズマ酸化化膜（第
２マスク膜）１１を形成する。但し、第４導電膜１０の
低抵抗化のために第４導電膜１０をタンタル窒化膜とタ
ンタルの積層構造としてもよい。After removing the photoresist 8 as shown in FIG. 4, the conductive film 6 and the conductive film 4 in the electrolytic gold plating process are performed.
The conductive film (second conductive film) 10 made of tantalum as a current path between the film and the film is formed by the DC magnetron sputtering method at a film forming power of 1.0 to 5.0 kW and a film forming pressure of 2-1.
The thickness is 0 mTorr and the thickness is 0.05 to 0.2 μm. Then, a plasma oxidation film (second mask film) 11 is formed on the conductive film 10 by plasma CVD with a thickness of 0.05 to 0.2 μm. However, in order to reduce the resistance of the fourth conductive film 10, the fourth conductive film 10 may have a laminated structure of a tantalum nitride film and tantalum.
【００１５】図５に示すように、ＣＦ4 ，ＣＨＦ3 ，Ｏ
2 などを反応ガスとし導電膜２をエッチング停止層とし
た異方性ドライエッチングを行い、平坦部及び層間接続
孔９９底部のプラズマ酸化膜１１を除去し層間接続孔９
側壁部のみを残す。ここで、平坦部では導電膜１０が露
出しており、層間接続孔９側壁ではプラズマ酸化膜１１
が露出しており、層間接続孔９底部は導電膜１０が露出
している。As shown in FIG. 5, CF 4 , CHF 3 , O
Anisotropic dry etching is performed using 2 as a reaction gas and the conductive film 2 as an etching stop layer to remove the plasma oxide film 11 at the flat portion and the bottom of the interlayer connection hole 99 to remove the interlayer connection hole 9
Leave only the side wall. Here, the conductive film 10 is exposed in the flat portion, and the plasma oxide film 11 is formed on the sidewall of the interlayer connection hole 9.
Is exposed, and the conductive film 10 is exposed at the bottom of the interlayer connection hole 9.
【００１６】図６に示すように、ＳＦ4 ，Ｃｌ2 ，Ｏ2
などを反応ガスとし、プラズマ窒化膜７と導電膜２とを
エッチング停止層とした異方性ドライエッチングを行
い、平坦部及び層間接続孔９底部の導電膜１０を除去す
る。ここで、平坦部ではプラズマ窒化膜７が露出してお
り、層間接続孔９側壁ではプラズマ酸化膜１１が露出し
ており、層間接続孔９底部は導電膜２が露出している。As shown in FIG. 6, SF 4 , Cl 2 , O 2
Anisotropic dry etching using the plasma nitride film 7 and the conductive film 2 as an etching stop layer is performed by using the above as a reaction gas to remove the conductive film 10 on the flat part and the bottom of the interlayer connection hole 9. Here, the plasma nitride film 7 is exposed in the flat portion, the plasma oxide film 11 is exposed in the sidewall of the interlayer connection hole 9, and the conductive film 2 is exposed in the bottom portion of the interlayer connection hole 9.
【００１７】図７に示すように、層間接続孔９側壁のプ
ラズマ酸化膜１１をバッファードフッ酸を用いて除去す
る。As shown in FIG. 7, the plasma oxide film 11 on the side wall of the interlayer connection hole 9 is removed by using buffered hydrofluoric acid.
【００１８】図８に示すように、プラズマ窒化膜７と導
電膜１０とをメッキマスクとし導電膜６と導電膜１０を
電流経路とし導電膜４を種付け層として電解金メッキ法
を用いて層間接続孔９内を金より構成される金属膜（第
３導電膜）１２で埋設する。ここで、導電膜１０はタン
タルより構成されており、表面に自然酸化膜が存在する
ためメッキ電流が供給されない。したがって導電膜１０
上にはメッキ金膜が成長しない。As shown in FIG. 8, the plasma nitride film 7 and the conductive film 10 are used as a plating mask, the conductive film 6 and the conductive film 10 are used as a current path, and the conductive film 4 is used as a seed layer. The inside of 9 is filled with a metal film (third conductive film) 12 made of gold. Here, the conductive film 10 is made of tantalum, and since a natural oxide film exists on the surface, the plating current is not supplied. Therefore, the conductive film 10
No plated gold film grows on top.
【００１９】図９に示すように、ＣＦ4 ，Ｏ2 などを反
応ガスとし、導電膜６をエッチング停止層としたドライ
エッチングを行い、平坦部のプラズマ窒化膜７を除去し
導電膜６を露出させる。As shown in FIG. 9, dry etching is performed using CF 4 , O 2 and the like as a reaction gas and the conductive film 6 as an etching stop layer to remove the plasma nitride film 7 in the flat portion and expose the conductive film 6. Let
【００２０】図１０に示すように、メッキ種付け層とし
て金より構成される導電膜（第４導電膜）１３を、ＤＣ
マグネトロンスパッタ法を用いて成膜パワー０．５〜
１．０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒの条件の下、
０．０１〜０．１μｍの厚みで導電膜６、導電膜１２上
に形成する。As shown in FIG. 10, a conductive film (fourth conductive film) 13 made of gold as a plating seed layer is formed by DC.
Film formation power of 0.5-using the magnetron sputtering method
Under the conditions of 1.0 kW and film forming pressure of 2 to 10 mTorr,
It is formed on the conductive film 6 and the conductive film 12 with a thickness of 0.01 to 0.1 μm.
【００２１】図１１に示すように、フォトリソグラフィ
ー技術を用いてフォトレジスト（配線形成用マスク膜）
１４を１．０〜２．０μｍの厚みで導電膜１３上に選択
的に形成し、硫酸金ナトリウム、硫酸、燐酸等より構成
される電解金メッキ液を用い、導電膜１３を陰極、白金
あるいはチタンに白金を被覆したメッシュ状電極を陽極
として通電し、メッキ温度３０〜６０℃、電流密度１〜
４ｍＡ／ｃｍ2 の条件の下で電解金メッキを行い、金よ
り構成される低い電気抵抗を有する導電膜（メッキ金
膜）１５を０．５〜２．０μｍの厚みで選択的に形成す
る。As shown in FIG. 11, photoresist (wiring formation mask film) is formed by using a photolithography technique.
14 is selectively formed on the conductive film 13 with a thickness of 1.0 to 2.0 μm, and the conductive film 13 is formed of a cathode, platinum or titanium by using an electrolytic gold plating solution composed of sodium gold sulfate, sulfuric acid, phosphoric acid or the like. The platinum-coated mesh electrode is used as an anode and electricity is applied, and the plating temperature is 30 to 60 ° C and the current density is 1 to
Electrolytic gold plating is performed under the condition of 4 mA / cm 2 , and a conductive film (plated gold film) 15 made of gold and having a low electric resistance is selectively formed with a thickness of 0.5 to 2.0 μm.
【００２２】図１２に示すように有機溶剤を用いてフォ
トレジスト１４を除去し、アルゴンガスをソースとした
ミリング法、ＣＦ4 ，ＳＦ6 をエッチングガスとした反
応性イオンエッチング法により、導電膜１５をエッチン
グマスクとして導電膜１２および導電膜１３の不要部分
のみを除去して、導電膜１２、導電膜１３及び導電膜１
５より構成される半導体集積回路装置の金属配線を形成
する。As shown in FIG. 12, the photoresist 14 is removed using an organic solvent, and the conductive film 15 is formed by a milling method using argon gas as a source and a reactive ion etching method using CF 4 and SF 6 as etching gases. Only the unnecessary portions of the conductive film 12 and the conductive film 13 are removed by using the etching mask as the etching mask, and the conductive film 12, the conductive film 13, and the conductive film 1 are removed.
The metal wiring of the semiconductor integrated circuit device constituted by 5 is formed.
【００２３】このような金属配線形成方法に於いては、
下層金配線の金膜を種付け層として層間接続孔９底部だ
けからメッキ金膜が成長するため、スパッタ金膜やメッ
キ金膜の段差被覆性が依存する事なく微細な層間接続孔
９をメッキ金膜により完全に埋設する事が可能である。
また、上層配線金属膜と接続孔金属膜の接続及び接続孔
金属膜と下層金配線の接続が金膜同士で行われているた
め、従来のような異種金属が接した構造に比べて接続抵
抗が低く、信頼性が高い配線構造となっている。本発明
の半導体装置の製造方法は、モス、バイポーラ等の半導
体集積回路装置の種類にかかわらず適応可能である事は
言うまでもない。 ［実施例２］次に本発明について図面を参照して第２の
実施例を説明する。In such a metal wiring forming method,
Since the plated gold film grows only from the bottom of the interlayer connection hole 9 using the gold film of the lower layer gold wiring as a seeding layer, the fine interlevel connection hole 9 is plated with gold without depending on the step coverage of the sputtered gold film or the plated gold film. It is possible to completely embed it with a membrane.
In addition, since the connection between the upper wiring metal film and the connection hole metal film and the connection between the connection hole metal film and the lower layer gold wiring are performed between the gold films, the connection resistance is different from the conventional structure in which different metals are in contact. Has a low and highly reliable wiring structure. It goes without saying that the semiconductor device manufacturing method of the present invention is applicable regardless of the type of semiconductor integrated circuit device such as moss or bipolar. [Embodiment 2] Next, a second embodiment of the present invention will be described with reference to the drawings.
【００２４】図１３に示す通り、半導体基板１上に層間
絶縁膜２が形成されており、層間絶縁膜２上に密着金属
としてチタンタングステン合金あるいはタンタルを用い
た第１導電膜３および第１導電膜３上に主導電材料とし
て金を用いた導電膜（金膜）４から構成される下層金配
線が形成されている。As shown in FIG. 13, the interlayer insulating film 2 is formed on the semiconductor substrate 1, and the first conductive film 3 and the first conductive film 3 using titanium-tungsten alloy or tantalum as the adhesion metal are formed on the interlayer insulating film 2. On the film 3 is formed a lower layer gold wiring composed of a conductive film (gold film) 4 using gold as a main conductive material.
【００２５】図１４に示すように、ＣＶＤ技術、ドライ
エッチング技術等を用いて、シリコン酸化膜、シリコン
窒化膜、平坦化塗布膜より構成される厚さ０．５〜１．
０μｍの層間絶縁膜５を層間絶縁膜２及び導電膜４上に
形成する。続いて、電解金メッキ工程における電流経路
としてタンタルより構成される導電膜（第１導電膜）６
を、ＤＣマグネトロンスパッタ法を用いて成膜パワー
１．０〜５．０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒと
し、０．０５〜０．２μｍの厚みで、層間絶縁膜５上に
形成する。続いて、導電膜６上にプラズマＣＶＤ技術を
用いて０．０５〜０．２μｍの厚みで第１プラズマ酸化
膜１６を形成する。但し、導電膜６の低抵抗化のために
導電膜６をタンタル窒化膜とタンタルの積層構造として
もよい。As shown in FIG. 14, a thickness of 0.5-1..cm including a silicon oxide film, a silicon nitride film, and a planarization coating film is formed by using a CVD technique, a dry etching technique, or the like.
An interlayer insulating film 5 of 0 μm is formed on the interlayer insulating film 2 and the conductive film 4. Subsequently, a conductive film (first conductive film) 6 made of tantalum as a current path in the electrolytic gold plating process
Is formed on the interlayer insulating film 5 by DC magnetron sputtering with a film forming power of 1.0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr and a thickness of 0.05 to 0.2 μm. Then, the first plasma oxide film 16 is formed on the conductive film 6 by the plasma CVD technique to have a thickness of 0.05 to 0.2 μm. However, the conductive film 6 may have a laminated structure of a tantalum nitride film and tantalum in order to reduce the resistance of the conductive film 6.
【００２６】図１５に示すように、所望の位置が開口し
ているフォトレジスト８をマスクとして、ＳＦ4 ，
Ｏ2 ，Ｃｌ2 などを反応ガスとした異方性ドライエッチ
ングを行い、第１プラズマ酸化膜１６、導電膜６および
層間絶縁膜５に層間接続孔９を形成し、下層金配線の導
電膜４を露出させる。As shown in FIG. 15, using the photoresist 8 having an opening at a desired position as a mask, SF 4 ,
Anisotropic dry etching using O 2 , Cl 2 or the like as a reaction gas is performed to form an interlayer connection hole 9 in the first plasma oxide film 16, the conductive film 6 and the interlayer insulating film 5, and the conductive film 4 of the lower gold wiring. Expose.
【００２７】図１６に示すようにフォトレジスト８を除
去した後、電解金メッキ工程における導電膜６と導電膜
４との間の電流経路としてタンタルより構成される導電
膜（第２導電膜）１０を、ＤＣマグネトロンスパッタ法
を用いて成膜パワー１．０〜５．０ｋＷ、成膜圧力２〜
１０ｍＴｏｒｒとし、０．０５〜０．２μｍの厚みで形
成する。続いて、導電膜１０上にプラズマＣＶＤ法を用
いて０．０５〜０．２μｍの厚みで第２プラズマ酸化膜
１７を形成する。但し、第４導電膜１０の低抵抗化のた
めに導電膜１０をタンタル窒化膜とタンタルの積層構造
としてもよい。After removing the photoresist 8 as shown in FIG. 16, a conductive film (second conductive film) 10 made of tantalum is formed as a current path between the conductive film 6 and the conductive film 4 in the electrolytic gold plating process. , DC magnetron sputtering method, film formation power 1.0 to 5.0 kW, film formation pressure 2
The thickness is set to 10 mTorr and the thickness is set to 0.05 to 0.2 μm. Then, the second plasma oxide film 17 is formed on the conductive film 10 by plasma CVD with a thickness of 0.05 to 0.2 μm. However, in order to reduce the resistance of the fourth conductive film 10, the conductive film 10 may have a laminated structure of a tantalum nitride film and tantalum.
【００２８】図１７に示すように、ＣＦ4 ，ＣＨＦ3 ，
Ｏ2 などを反応ガスとし導電膜６をエッチング停止層と
した異方性ドライエッチングを行い、平坦部及び層間接
続孔９底部の第２プラズマ酸化膜１７を除去し層間接続
孔９側壁部のみを残す。ここで、平坦部では導電膜１０
が露出しており、層間接続孔９側壁では第２プラズマ酸
化膜１７が露出しており、層間接続孔９底部では導電膜
１０が露出している。As shown in FIG. 17, CF 4 , CHF 3 ,
Anisotropic dry etching is performed using O 2 or the like as a reaction gas and the conductive film 6 as an etching stop layer to remove the second plasma oxide film 17 at the flat portion and the bottom of the interlayer connection hole 9 to remove only the sidewall portion of the interlayer connection hole 9. leave. Here, the conductive film 10 is formed in the flat portion.
Are exposed, the second plasma oxide film 17 is exposed at the sidewall of the interlayer connection hole 9, and the conductive film 10 is exposed at the bottom of the interlayer connection hole 9.
【００２９】図１８に示すように、ＳＦ4 ，Ｃｌ2 ，Ｏ
2 などを反応ガスとし、第１プラズマ酸化膜１６と導電
膜６をエッチング停止層とした異方性ドライエッチング
を行い、平坦部及び層間接続孔９底部の導電膜１０を除
去する。ここで、平坦部では第１プラズマ酸化膜１６が
露出しており、層間接続孔９側壁では第２プラズマ酸化
膜１７が露出しており、層間接続孔９底部は導電膜２が
露出している。As shown in FIG. 18, SF 4 , Cl 2 , O
Anisotropic dry etching using the first plasma oxide film 16 and the conductive film 6 as an etching stop layer is performed by using 2 or the like as a reaction gas to remove the conductive film 10 on the flat part and the bottom of the interlayer connection hole 9. Here, the first plasma oxide film 16 is exposed in the flat portion, the second plasma oxide film 17 is exposed in the sidewall of the interlayer connection hole 9, and the conductive film 2 is exposed in the bottom portion of the interlayer connection hole 9. .
【００３０】図１９に示すように、平坦部の第１プラズ
マ酸化膜１６及び層間接続孔９側壁の第２プラズマ酸化
膜１７をバッファードフッ酸を用いて除去する。As shown in FIG. 19, the first plasma oxide film 16 on the flat portion and the second plasma oxide film 17 on the side wall of the interlayer connection hole 9 are removed by using buffered hydrofluoric acid.
【００３１】図２０に示すように、導電膜６と導電膜１
０をメッキマスクとし導電膜６と導電膜１０を電流経路
とし導電膜４を種付け層として電解金メッキ法を用いて
層間接続孔９内を金より構成される導電膜（第３導電
膜）１２で埋設する。As shown in FIG. 20, the conductive film 6 and the conductive film 1
A conductive film (third conductive film) 12 made of gold is formed in the interlayer connection hole 9 by electrolytic gold plating using 0 as a plating mask, the conductive film 6 and the conductive film 10 as current paths, and the conductive film 4 as a seeding layer. Buried.
【００３２】図２１に示すように、ドライエッチング技
術を用いて導電膜６を除去する。図２２に示すように、
層間絶縁膜５と導電膜１２上にタンタルあるいはチタン
タングステン合金により構成される導電膜（積層導電
膜）１８をＤＣマグネトロンスパッタ法を用いて成膜パ
ワー０．５〜１．０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒ
の条件の下、０．０１〜０．１μｍの厚みで形成する。As shown in FIG. 21, the conductive film 6 is removed by using the dry etching technique. As shown in FIG. 22,
A conductive film (laminated conductive film) 18 made of tantalum or a titanium-tungsten alloy is formed on the interlayer insulating film 5 and the conductive film 12 by a DC magnetron sputtering method at a film forming power of 0.5 to 1.0 kW and a film forming pressure of 2. -10mTorr
Under the conditions described above, the film is formed with a thickness of 0.01 to 0.1 μm.
【００３３】図２３に示すように、メッキ種付け層とし
て金より構成される導電膜（第４導電膜）１３を、ＤＣ
マグネトロンスパッタ法を用いて成膜パワー０．５〜
１．０ｋＷ、成膜圧力２〜１０ｍＴｏｒｒの条件の下、
０．０１〜０．１μｍの厚みで導電膜１８上に形成す
る。As shown in FIG. 23, a conductive film (fourth conductive film) 13 made of gold as a plating seed layer is formed by DC.
Film formation power of 0.5-using the magnetron sputtering method
Under the conditions of 1.0 kW and film forming pressure of 2 to 10 mTorr,
It is formed on the conductive film 18 with a thickness of 0.01 to 0.1 μm.
【００３４】図２４に示すように、フォトリソグラフィ
ー技術を用いてフォトレジスト（配線形成用マスク膜）
１４を１．０〜２．０μｍの厚みで導電膜１３上に選択
的に形成し、硫酸ナトリウム、硫酸、燐酸などにより構
成される電解金メッキ液を用い導電膜１３を陰極、白金
あるいはチタンに白金を被覆したメッシュ状電極を陽極
として通電し、メッキ温度３０〜６０℃、電流密度１〜
４ｍＡ／ｃｍ2 の条件の下で電解金メッキを行い、金よ
り構成される低い電気抵抗を有する導電膜（メッキ金
膜）１５を０．５〜２．０μｍの厚みで選択的に形成す
る。As shown in FIG. 24, a photoresist (wiring formation mask film) is formed by using a photolithography technique.
14 is selectively formed on the conductive film 13 with a thickness of 1.0 to 2.0 μm, and the conductive film 13 is formed on the cathode, platinum or titanium by using an electrolytic gold plating solution composed of sodium sulfate, sulfuric acid, phosphoric acid or the like. The mesh-shaped electrode coated with is energized as an anode, the plating temperature is 30 to 60 ° C., the current density is 1 to
Electrolytic gold plating is performed under the condition of 4 mA / cm 2 , and a conductive film (plated gold film) 15 made of gold and having a low electric resistance is selectively formed with a thickness of 0.5 to 2.0 μm.
【００３５】図１２に示すように有機溶剤を用いてフォ
トレジスト１４を除去し、アルゴンガスをソースとした
ミリング法、ＣＦ4 ，ＳＦ6 をエッチングガスとした反
応性イオンエッチング法により、導電膜（メッキ金膜）
１５をエッチングマスクとして導電膜１８および導電膜
１３の不要部分のみを除去して、導電膜１８、導電膜１
３及び導電膜１５より構成される半導体集積回路装置の
金属配線を形成する。As shown in FIG. 12, the photoresist 14 is removed by using an organic solvent, and a conductive film is formed by a milling method using argon gas as a source and a reactive ion etching method using CF 4 and SF 6 as etching gases. Plated gold film)
By using 15 as an etching mask, only the unnecessary portions of the conductive film 18 and the conductive film 13 are removed to remove the conductive film 18 and the conductive film 1.
The metal wiring of the semiconductor integrated circuit device composed of 3 and the conductive film 15 is formed.
【００３６】本実施例では、平坦部の第１プラズマ酸化
膜１６を層間接続孔９側壁部の第２プラズマ酸化膜１７
と同時に除去しているため、実施例１に比べて工程が簡
略化されている。また、実施例１と同様に層間接続孔底
部からメッキ金膜を成長させているため、微細な層間接
続孔をメッキ金膜により完全に埋設する事が可能であ
り、信頼性が高い配線構造となっている。本発明の半導
体装置の製造方法は、モス、バイポーラ等の半導体集積
回路装置の種類にかかわらず適応可能である事は言うま
でもない。In this embodiment, the first plasma oxide film 16 on the flat portion is replaced with the second plasma oxide film 17 on the sidewall portion of the interlayer connection hole 9.
Since it is removed at the same time, the process is simplified as compared with the first embodiment. Further, since the plated gold film is grown from the bottom of the interlayer connection hole as in the case of Example 1, it is possible to completely bury the fine interlayer connection hole with the plated gold film, and to provide a highly reliable wiring structure. Has become. It goes without saying that the semiconductor device manufacturing method of the present invention is applicable regardless of the type of semiconductor integrated circuit device such as moss or bipolar.
【００３７】[0037]
【発明の効果】以上説明したように本発明の半導体装置
の製造方法においては、層間接続孔をメッキ金膜で完全
に埋設することが可能であり、また上層配線と下層配線
を金膜同士で接続することにより接続抵抗を低下させる
効果を有する。As described above, in the method of manufacturing a semiconductor device of the present invention, the interlayer connection hole can be completely filled with the plated gold film, and the upper layer wiring and the lower layer wiring can be formed by the gold films. The connection has the effect of reducing the connection resistance.
【図１】本発明の半導体装置の製造方法における第１の
実施例の工程を示す縦断面図である。FIG. 1 is a vertical sectional view showing a process of a first embodiment in a method for manufacturing a semiconductor device of the present invention.
【図２】図１の工程の次工程を示す縦断面図である。FIG. 2 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図３】図２の工程の次工程を示す縦断面図である。FIG. 3 is a vertical cross-sectional view showing a step subsequent to the step shown in FIG.
【図４】図３の工程の次工程を示す縦断面図である。FIG. 4 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図５】図４の工程の次工程を示す縦断面図である。5 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図６】図５の工程の次工程を示す縦断面図である。FIG. 6 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図７】図５の工程の次工程を示す縦断面図である。FIG. 7 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図８】図７の工程の次工程を示す縦断面図である。8 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図９】図８の工程の次工程を示す縦断面図である。9 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図１０】図９の工程の次工程を示す縦断面図である。FIG. 10 is a vertical cross-sectional view showing a step subsequent to the step shown in FIG.
【図１１】図１０の工程の次工程を示す縦断面図であ
る。FIG. 11 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図１２】図１１の工程の次工程を示す縦断面図であ
る。12 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図１３】本発明の半導体装置の製造方法における第２
の実施例の工程を示す縦断面図である。FIG. 13 is a second view of the method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a vertical cross-sectional view showing the process of the example of FIG.
【図１４】図１３の工程の次工程を示す縦断面図であ
る。FIG. 14 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図１５】図１４の工程の次工程を示す縦断面図であ
る。FIG. 15 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図１６】図１５の工程の次工程を示す縦断面図であ
る。16 is a vertical sectional view showing a step subsequent to the step shown in FIG.
【図１７】図１６の工程の次工程を示す縦断面図であ
る。FIG. 17 is a vertical sectional view showing a step subsequent to the step shown in FIG. 16.
【図１８】図１７の工程の次工程を示す縦断面図であ
る。FIG. 18 is a vertical sectional view showing a step subsequent to the step shown in FIG. 17.
【図１９】図１８の工程の次工程を示す縦断面図であ
る。FIG. 19 is a vertical sectional view showing a step subsequent to the step shown in FIG. 18.
【図２０】図１９の工程の次工程を示す縦断面図であ
る。FIG. 20 is a vertical sectional view showing a step subsequent to the step shown in FIG. 19.
【図２１】図２０の工程の次工程を示す縦断面図であ
る。21 is a vertical sectional view showing a step subsequent to the step shown in FIG. 20. FIG.
【図２２】図２１の工程の次工程を示す縦断面図であ
る。22 is a vertical sectional view showing a step that follows the step of FIG. 21. FIG.
【図２３】図２２の工程の次工程を示す縦断面図であ
る。FIG. 23 is a vertical cross-sectional view showing a step that follows the step of FIG. 22.
【図２４】図２３の工程の次工程を示す縦断面図であ
る。FIG. 24 is a vertical cross-sectional view showing a step subsequent to the step of FIG.
【図２５】従来の半導体装置の金属配線形成方法の工程
縦断面図である。FIG. 25 is a process vertical cross-sectional view of the conventional method for forming a metal wiring of a semiconductor device.
【図２６】図２５の工程の次工程を示す縦断面図であ
る。26 is a vertical sectional view showing a step subsequent to the step shown in FIG. 25. FIG.
【図２７】図２６の工程の次工程を示す縦断面図であ
る。27 is a vertical sectional view showing a step subsequent to the step shown in FIG. 26. FIG.
１ 半導体基板 ２ 層間絶縁膜 ３ 導電膜 ４ 導電膜（金膜） ５ 層間絶縁膜 ６ 導電膜（第１の導電膜） ７ プラズマ窒化膜（第１マスク膜） ８ フォトレジスト ９ 層間接続孔 １０ 導電膜（第２導電膜） １１ プラズマ酸化膜（第２マスク膜） １２ 導電膜（第３導電膜） １３ 導電膜（積層導電膜） １４ フォトレジスト（配線形成用マスク膜） １５ 導電膜（メッキ金膜） １６ 第１プラズマ酸化膜 １７ 第２プラズマ酸化膜 １８ 導電膜（積層導電膜） １９ 第１チタンタングステン合金 ２０ 第１金膜 ２１ 層間絶縁膜 ２２ 層間接続孔 ２３ 第２チタンタングステン合金 ２４ メッキ下地膜 ２５ フォトレジスト ２６ 第２金膜 1 semiconductor substrate 2 interlayer insulating film 3 conductive film 4 conductive film (gold film) 5 interlayer insulating film 6 conductive film (first conductive film) 7 plasma nitride film (first mask film) 8 photoresist 9 interlayer connection hole 10 conductive Film (second conductive film) 11 Plasma oxide film (second mask film) 12 Conductive film (third conductive film) 13 Conductive film (laminated conductive film) 14 Photoresist (mask film for wiring formation) 15 Conductive film (plated gold) Film 16 first plasma oxide film 17 second plasma oxide film 18 conductive film (laminated conductive film) 19 first titanium-tungsten alloy 20 first gold film 21 interlayer insulating film 22 interlayer connection hole 23 second titanium tungsten alloy 24 under plating Underlayer film 25 Photoresist 26 Second gold film
Claims (6)
膜（４）が形成された半導体基板（１）上に層間絶縁膜
（５）を形成する工程と、該層間絶縁膜上に第１導電膜
（６）を形成する工程と、前記第１導電膜上に第１マス
ク膜（７）を形成する工程と、該第１マスク膜、前記第
１導電膜及び前記層間絶縁膜に接続孔（９）を形成する
工程と、前記第１マスク膜及び前記接続孔上に第２導電
膜（１０）を形成する工程と、該第２導電膜上に第２マ
スク膜（１１）を形成する工程と、平坦部と前記接続孔
底部の前記第２マスク膜を除去し前記接続孔側壁部の前
記第２マスク膜のみを残す工程と、前記平坦部と前記接
続孔底部の前記第２導電膜を除去し前記平坦部に於て前
記第１マスク膜を露出させると共に前記接続孔底部に於
て前記金膜を露出させる工程と、前記接続孔側壁部の前
記第２マスク膜のみを除去する工程と、前記第１マスク
膜と前記第２導電膜をマスクとし、前記第１導電膜と前
記第２導電膜を電流経路とし、前記接続孔底部に露出し
た前記下層配線の前記金膜を種付け層として、電解金メ
ッキ法を用いて前記接続孔内に第３導電膜（１２）を形
成する工程とを含むことを特徴とした半導体装置の製造
方法。1. A step of forming an interlayer insulating film (5) on a semiconductor substrate (1) on which a semiconductor element, an electrode and a gold film (4) of gold wiring are formed in a lower layer, and a step of forming an interlayer insulating film (5) on the interlayer insulating film. Forming a first conductive film (6), forming a first mask film (7) on the first conductive film, and connecting to the first mask film, the first conductive film and the interlayer insulating film. Forming a hole (9), forming a second conductive film (10) on the first mask film and the connection hole, and forming a second mask film (11) on the second conductive film. A step of removing the second mask film on the flat portion and the bottom portion of the connection hole and leaving only the second mask film on the sidewall portion of the connection hole, and the second conductivity of the flat portion and the bottom portion of the connection hole. The film is removed to expose the first mask film on the flat portion and expose the gold film on the bottom of the connection hole. And a step of removing only the second mask film on the side wall of the connection hole, and a current is applied to the first conductive film and the second conductive film by using the first mask film and the second conductive film as a mask. Forming a third conductive film (12) in the connection hole by using an electrolytic gold plating method, using the gold film of the lower wiring exposed at the bottom of the connection hole as a seeding layer. And a method for manufacturing a semiconductor device.
おいて、前記平坦部の前記第１マスク膜を除去すること
により前記第１導電膜を露出させる工程と、前記第１導
電膜上に金より構成される第４導電膜（１３）を形成す
る工程と、該第４導電膜上に配線形成用マスク膜（１
４）を形成する工程と、該配線形成用マスク膜をマスク
としてメッキ金膜（１５）を形成する工程と、前記配線
形成用マスク膜を除去する工程と、前記メッキ金膜をマ
スクとして不要部分の前記第１導電膜及び前記第４導電
膜を除去する事により上層金配線を形成する工程とを含
むことを特徴とした半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive film is exposed by removing the first mask film on the flat portion, and a gold film is formed on the first conductive film. A step of forming a fourth conductive film (13) composed of the above, and a mask film (1) for forming a wiring on the fourth conductive film.
4), a step of forming a plated gold film (15) using the wiring formation mask film as a mask, a step of removing the wiring formation mask film, and an unnecessary portion using the plated gold film as a mask And a step of forming an upper layer gold wiring by removing the first conductive film and the fourth conductive film.
おいて、前記平坦部の前記第１マスク膜を除去すること
により前記第１導電膜を露出させる工程と、前記平坦部
の前記第１導電膜を除去し前記層間絶縁膜を露出させる
工程と、前記層間絶縁膜上に金／タンタルあるいは金／
チタンタングステンより構成される積層導電膜（１３，
１８）を形成する工程と、該積層導電膜上に配線形成用
マスク膜（１４）を形成する工程と、該配線形成用マス
ク膜をマスクとして前記積層導電膜上に前記メッキ金膜
を形成する工程と、前記配線形成用マスク膜を除去する
工程と、前記メッキ金膜をマスクとして不要部分の前記
積層導電膜を除去する事により上層金配線を形成する工
程とを含むことを特徴とした半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive film is exposed by removing the first mask film on the flat portion, and the first conductive film on the flat portion. Removing the film to expose the interlayer insulating film, and gold / tantalum or gold / on the interlayer insulating film.
Laminated conductive film (13,
18), a step of forming a wiring forming mask film (14) on the laminated conductive film, and a step of forming the plated gold film on the laminated conductive film using the wiring forming mask film as a mask. A semiconductor characterized by including a step, a step of removing the wiring forming mask film, and a step of forming an upper layer gold wiring by removing an unnecessary portion of the laminated conductive film using the plated gold film as a mask. Device manufacturing method.
膜（４）が形成された半導体基板（１）上に層間絶縁膜
（５）を形成する工程と、該層間絶縁膜上に第１導電膜
（６）を形成する工程と、該第１導電膜上に第１マスク
膜（７）を形成する工程と、該第１マスク膜、前記第１
導電膜及び前記層間絶縁膜に接続孔（９）を形成する工
程と、前記第１マスク膜及び前記接続孔上に第２導電膜
（１０）を形成する工程と、該第２導電膜上に第２マス
ク膜（１１）を形成する工程と、平坦部と前記接続孔底
部の前記第２マスク膜を除去し前記接続孔側壁部の前記
第２マスク膜のみを残す工程と、前記平坦部と前記接続
孔底部の前記第２導電膜を除去し前記平坦部に於て前記
第１マスク膜を露出させると共に前記接続孔底部に於て
下層金配線の前記金膜を露出させる工程と、前記平坦部
の前記第１マスク膜と前記接続孔側壁部の前記第２マス
ク膜を除去する工程と、前記第１導電膜と前記第２導電
膜をメッキマスクおよび電流経路とし、前記接続孔底部
に露出した前記下層配線の前記金膜を種付け層として、
電解金メッキ法を用いて前記接続孔内に第３導電膜（１
２）を形成する工程とを含むことを特徴とした半導体装
置の製造方法。4. A step of forming an interlayer insulating film (5) on a semiconductor substrate (1) having a semiconductor element, an electrode and a gold film (4) of gold wiring formed on a lower layer, and a step of forming an interlayer insulating film (5) on the interlayer insulating film. A step of forming a first conductive film (6), a step of forming a first mask film (7) on the first conductive film, the first mask film, the first film
Forming a connection hole (9) on the conductive film and the interlayer insulating film; forming a second conductive film (10) on the first mask film and the connection hole; and forming a second conductive film on the second conductive film. A step of forming a second mask film (11); a step of removing the second mask film on the flat portion and the bottom portion of the connection hole and leaving only the second mask film on the sidewall portion of the connection hole; and the flat portion. Removing the second conductive film at the bottom of the contact hole to expose the first mask film at the flat portion and exposing the gold film of the lower-layer gold wiring at the bottom of the contact hole; Part of the first mask film and the second mask film on the side wall of the connection hole, and the first conductive film and the second conductive film are used as a plating mask and a current path and exposed at the bottom of the connection hole. As the seeding layer, the gold film of the lower wiring is
A third conductive film (1) is formed in the connection hole using an electrolytic gold plating method.
2) The method of manufacturing a semiconductor device, comprising the step of forming.
おいて、前記第１導電膜（６）上に金より構成される第
４導電膜（１３）を形成する工程と、前記第４導電膜
（１３）上に配線形成用マスク膜（１４）を形成する工
程と、該配線形成用マスク膜をマスクとしてメッキ金膜
（１５）を形成する工程と、該配線形成用マスク膜を除
去する工程と、前記メッキ金膜をマスクとして不要部分
の前記第１導電膜及び前記第４導電膜を除去する事によ
り前記上層金配線を形成する工程を含むことを特徴とし
た半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein a step of forming a fourth conductive film (13) made of gold on the first conductive film (6), and the fourth conductive film. (13) A step of forming a wiring forming mask film (14), a step of forming a plated gold film (15) using the wiring forming mask film as a mask, and a step of removing the wiring forming mask film And a step of forming the upper-layer gold wiring by removing unnecessary portions of the first conductive film and the fourth conductive film using the plated gold film as a mask.
おいて、前記平坦部の前記第１導電膜を除去し前記層間
絶縁膜を露出させる工程と、前記層間絶縁膜上に金／タ
ンタルあるいは金／チタンタングステンより構成される
積層導電膜（１３，１８）を形成する工程と、該積層導
電膜上に配線形成用マスク膜（１４）を形成する工程
と、該配線形成用マスク膜をマスクとして前記積層導電
膜上にメッキ金膜（１５）を形成する工程と、前記配線
形成用マスク膜を除去する工程と、前記メッキ金膜をマ
スクとして不要部分の前記積層導電膜を除去する事によ
り前記上層金配線を形成する工程を含むことを特徴とし
た半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 4, wherein the step of removing the first conductive film in the flat portion to expose the interlayer insulating film, and gold / tantalum or gold on the interlayer insulating film. / Forming a laminated conductive film (13, 18) made of titanium tungsten, forming a wiring forming mask film (14) on the laminated conductive film, and using the wiring forming mask film as a mask Forming a plated gold film (15) on the laminated conductive film; removing the wiring forming mask film; and removing the unnecessary portion of the laminated conductive film by using the plated gold film as a mask. A method of manufacturing a semiconductor device, comprising the step of forming an upper layer gold wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5337253A JP2737762B2 (en) | 1993-12-28 | 1993-12-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5337253A JP2737762B2 (en) | 1993-12-28 | 1993-12-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07201988A true JPH07201988A (en) | 1995-08-04 |
| JP2737762B2 JP2737762B2 (en) | 1998-04-08 |
Family
ID=18306889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5337253A Expired - Fee Related JP2737762B2 (en) | 1993-12-28 | 1993-12-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2737762B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011082231A (en) * | 2009-10-05 | 2011-04-21 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the semiconductor device |
| US8049989B2 (en) | 2007-12-26 | 2011-11-01 | Hitachi Global Storage Technologies Netherlands B.V. | Magnetic head for perpendicular recording having stepped wrap around shield with independent control of write pole track width and flare point dimensions |
| US8179634B2 (en) | 2007-12-27 | 2012-05-15 | Hitachi Global Storage Technologies Netherlands B.V. | Perpendicular magnetic recording writer main pole having imbedded non-magnetic core and de-coupled pole tip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529315A (en) * | 1991-07-23 | 1993-02-05 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH05206064A (en) * | 1991-12-10 | 1993-08-13 | Nec Corp | Manufacture of semiconductor device |
-
1993
- 1993-12-28 JP JP5337253A patent/JP2737762B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529315A (en) * | 1991-07-23 | 1993-02-05 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH05206064A (en) * | 1991-12-10 | 1993-08-13 | Nec Corp | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8049989B2 (en) | 2007-12-26 | 2011-11-01 | Hitachi Global Storage Technologies Netherlands B.V. | Magnetic head for perpendicular recording having stepped wrap around shield with independent control of write pole track width and flare point dimensions |
| US8179634B2 (en) | 2007-12-27 | 2012-05-15 | Hitachi Global Storage Technologies Netherlands B.V. | Perpendicular magnetic recording writer main pole having imbedded non-magnetic core and de-coupled pole tip |
| JP2011082231A (en) * | 2009-10-05 | 2011-04-21 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2737762B2 (en) | 1998-04-08 |
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