JPH07170078A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH07170078A JPH07170078A JP31704893A JP31704893A JPH07170078A JP H07170078 A JPH07170078 A JP H07170078A JP 31704893 A JP31704893 A JP 31704893A JP 31704893 A JP31704893 A JP 31704893A JP H07170078 A JPH07170078 A JP H07170078A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- plating
- copper plating
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プリント配線板の製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board.
【０００２】[0002]
【従来の技術】近年、高密度化・高集積化する傾向にあ
る電子部品を実装するためのプリント配線板として、基
板の外表面のみならず、基板の内面にも導体回路を備え
た多層プリント配線板が主流になりつつある。この種の
プリント配線板は、例えば以下のようなプロセスによっ
て作製される。2. Description of the Related Art In recent years, as a printed wiring board for mounting electronic parts which tend to be highly integrated and highly integrated, a multilayer printed board having conductor circuits not only on the outer surface of the board but also on the inner surface of the board. Wiring boards are becoming mainstream. This type of printed wiring board is manufactured by the following process, for example.
【０００３】まず、基板の表面に電気銅からなる内層導
体回路を形成する。プリプレグをラミネートすることな
どによって、内層導体回路が形成された基板の表面に層
間絶縁層を形成する。ドリル加工を行うことなどによっ
て基板にスルーホール形成用孔を透設した後、必要に応
じてデスミア処理等を行う。スルーホール形成用孔の内
壁面などに、無電解銅めっきの最初の析出に必要な触媒
核を付与する。必要に応じてめっき前処理を行った後、
無電解銅めっきを行うことによって、スルーホール形成
用孔の内壁面全体にスルーホールめっきを析出させる。
以下、所定のプロセスを経ることによって、最終的には
スルーホールを介して内層導体回路と外層導体回路とが
接続された多層プリント配線板が得られるようになって
いる。First, an inner conductor circuit made of electrolytic copper is formed on the surface of a substrate. By laminating the prepreg or the like, an interlayer insulating layer is formed on the surface of the substrate on which the inner conductor circuit is formed. After forming through-hole forming holes in the substrate by drilling or the like, desmear treatment or the like is performed if necessary. The catalyst nuclei necessary for the initial deposition of electroless copper plating are provided on the inner wall surface of the through hole forming hole. After performing plating pretreatment as necessary,
By performing electroless copper plating, the through hole plating is deposited on the entire inner wall surface of the through hole forming hole.
After that, through a predetermined process, finally, a multilayer printed wiring board in which the inner layer conductor circuit and the outer layer conductor circuit are connected via a through hole can be obtained.
【０００４】[0004]
【発明が解決しようとする課題】ところで、従来のプロ
セスによると、基板がドリルで削りとられることによっ
て、スルーホール形成用孔の内壁面が粗面化してしまう
場合がある。そして、通常はこのような内壁面全体に対
して触媒核が付与され、かつ無電解銅めっきによってス
ルーホールめっきが形成されることになる。By the way, according to the conventional process, the inner wall surface of the through-hole forming hole may be roughened due to the substrate being drilled. Then, usually, the catalyst nuclei are applied to the entire inner wall surface and the through-hole plating is formed by the electroless copper plating.
【０００５】しかしながら、上記のようなプロセスによ
ると、ヒートショック遭遇時などに内層導体回路とスル
ーホールめっきとの界面に接続不良が発生し易くなると
いう欠点があった。ゆえに、従来においては信頼性に優
れたプリント配線板を得ることが困難であった。However, according to the above-mentioned process, there is a drawback that a connection failure is likely to occur at the interface between the inner layer conductor circuit and the through hole plating when a heat shock is encountered. Therefore, conventionally, it was difficult to obtain a printed wiring board having excellent reliability.
【０００６】本発明は上記の事情に鑑みてなされたもの
であり、その目的は、内層導体回路とスルーホールとの
界面における接続不良を確実に低減することができ、接
続信頼性を向上させることができるプリント配線板の製
造方法を提供することにある。The present invention has been made in view of the above circumstances, and an object thereof is to reliably reduce connection defects at the interface between an inner layer conductor circuit and a through hole and to improve connection reliability. Another object of the present invention is to provide a method for manufacturing a printed wiring board that can be manufactured.
【０００７】[0007]
【課題を解決するための手段】上記の課題を解決するた
めに、請求項１に記載の発明では、内層導体回路を備え
る基板にスルーホール形成用孔を透設し、そのスルーホ
ール形成用孔の内壁面に触媒核を付与した後、無電解銅
めっきによって前記スルーホール形成用孔の内壁面全体
にスルーホールめっきを析出させるプリント配線板の製
造方法において、触媒核を付与する工程の前に無電解銅
めっきを行うことによって、前記スルーホール形成用孔
の内壁面に露出している前記内層導体回路の一部に銅め
っきを析出させることを特徴としたプリント配線板の製
造方法をその要旨としている。In order to solve the above-mentioned problems, according to the invention as defined in claim 1, a through hole is formed in a substrate having an inner conductor circuit, and the through hole is formed. In the method for producing a printed wiring board in which the catalyst nuclei are applied to the inner wall surface of the printed wiring board and then the through hole plating is deposited on the entire inner wall surface of the through hole forming hole by electroless copper plating, before the step of applying the catalyst nuclei. A method of manufacturing a printed wiring board, characterized in that electroless copper plating is performed to deposit copper plating on a part of the inner layer conductor circuit exposed on the inner wall surface of the through hole forming hole. I am trying.
【０００８】請求項２に記載の発明では、内層導体回路
を備える基板にスルーホール形成用孔を透設し、そのス
ルーホール形成用孔の内壁面に触媒核を付与した後、無
電解銅めっきによって前記スルーホール形成用孔の内壁
面全体にスルーホールめっきを析出させるプリント配線
板の製造方法において、触媒核を付与する工程の前に電
解銅めっきを行うことによって、前記スルーホール形成
用孔の内壁面に露出している前記内層導体回路の一部に
銅めっきを析出させることを特徴としたプリント配線板
の製造方法をその要旨としている。According to the second aspect of the present invention, a through hole forming hole is provided through a substrate having an inner layer conductor circuit, and a catalyst nucleus is provided on the inner wall surface of the through hole forming hole, and then electroless copper plating is performed. In the method for manufacturing a printed wiring board in which through-hole plating is deposited on the entire inner wall surface of the through-hole forming hole by electrolytic copper plating before the step of applying the catalyst nucleus, the through-hole forming hole is formed. The gist is a method for manufacturing a printed wiring board, which is characterized in that copper plating is deposited on a part of the inner conductor circuit exposed on the inner wall surface.
【０００９】[0009]
【作用】請求項１に記載の発明の方法によると、無電解
銅めっきによって界面に銅めっきを析出させた後に触媒
核が付与され、次いでスルーホールめっき形成のための
無電解銅めっきが行われる。つまり、触媒核は前記内層
導体回路の一部に直接的に付与されるのではなく、その
部分に析出した銅めっきを介して間接的に付与されるこ
とになる。従って、内層導体回路とスルーホールとの界
面に銅めっきが介在した状態となり、結果として当該部
分における接続不良が減少する。According to the method of the present invention as set forth in claim 1, after the copper plating is deposited on the interface by the electroless copper plating, the catalyst nuclei are added, and then the electroless copper plating for forming the through-hole plating is performed. . That is, the catalyst nucleus is not directly applied to a part of the inner layer conductor circuit, but is indirectly applied through the copper plating deposited on that part. Therefore, the copper plating is interposed at the interface between the inner layer conductor circuit and the through hole, and as a result, the connection failure at the relevant portion is reduced.
【００１０】請求項２に記載の発明の方法によると、電
解銅めっきによって界面に銅めっきを析出させた後に触
媒核が付与され、次いでスルーホールめっき形成のため
の無電解銅めっきが行われる。つまり、触媒核は前記内
層導体回路の一部に直接的に付与されるのではなく、そ
の部分に析出した銅めっきを介して間接的に付与される
ことになる。従って、内層導体回路とスルーホールとの
界面に銅めっきが介在した状態となり、結果として当該
部分における接続不良が減少する。According to the method of the present invention as defined in claim 2, after the copper plating is deposited on the interface by electrolytic copper plating, catalyst nuclei are added, and then electroless copper plating for forming through-hole plating is performed. That is, the catalyst nucleus is not directly applied to a part of the inner layer conductor circuit, but is indirectly applied through the copper plating deposited on that part. Therefore, the copper plating is interposed at the interface between the inner layer conductor circuit and the through hole, and as a result, the connection failure at the relevant portion is reduced.
【００１１】以下、本発明のプリント配線板の製造方法
を図３，図４に基づき詳細に説明する。図３は、本発明
の製造方法によって作製されるプリント配線板における
内層導体回路２１とスルーホール２２との界面Ｂの様子
を示している。一方、図４は、従来の製造方法によって
作製されるプリント配線板における内層導体回路２１と
スルーホール２２との界面Ｂの様子を示している。な
お、図３及び図４に示されるように、スルーホール形成
用孔の内壁面２３は、いずれもドリルに削りとられるこ
とによって粗面化した状態となっている。同様に、スル
ーホール２２との界面Ｂにあたる内層導体回路の一部
（以下、内端部２１ａという）も粗面化した状態になっ
ている。The method for manufacturing a printed wiring board according to the present invention will be described in detail below with reference to FIGS. FIG. 3 shows a state of the interface B between the inner layer conductor circuit 21 and the through hole 22 in the printed wiring board manufactured by the manufacturing method of the present invention. On the other hand, FIG. 4 shows a state of the interface B between the inner layer conductor circuit 21 and the through hole 22 in the printed wiring board manufactured by the conventional manufacturing method. As shown in FIGS. 3 and 4, the inner wall surface 23 of the through-hole forming hole is roughened by being cut by a drill. Similarly, a part of the inner layer conductor circuit (hereinafter referred to as the inner end portion 21a) corresponding to the interface B with the through hole 22 is also roughened.
【００１２】図４に示される従来のプリント配線板で
は、上記のように粗くなった内端部２１ａに対して触媒
核２４が付与された後、スルーホールめっき２５を析出
させるための無電解銅めっきが行われる。従って、従来
のプリント配線板の場合、必然的に界面Ｂの接続状態が
悪くなり、接続不良が発生し易くなるものと推測され
る。また、触媒核２４のような不純物が界面Ｂに存在し
ていることも両者間の接続状態を悪化させる原因の１つ
になっていると考えられる。In the conventional printed wiring board shown in FIG. 4, the electroless copper for depositing the through-hole plating 25 after the catalyst nuclei 24 are applied to the inner end portion 21a roughened as described above. Plating is performed. Therefore, in the case of the conventional printed wiring board, it is inferred that the connection state of the interface B is inevitably deteriorated and the connection failure is likely to occur. Further, the presence of impurities such as the catalyst nuclei 24 at the interface B is considered to be one of the causes of deteriorating the connection state between the two.
【００１３】一方、図４に示される本発明のプリント配
線板の場合、あらかじめ無電解銅めっきまたは電解銅め
っきによって内端部２５ａに銅めっき２６を析出させた
後に、触媒核２４が付与される。つまり、この方法では
スルーホールめっき２５は表面の粗い内端部２１ａ上に
ではなく、比較的平滑な銅めっき２６上に析出すること
になる。また、この方法によると、内端部２１ａと銅め
っき２６との界面Ｂに何ら不純物が存在することがない
という特徴がある。以上のようなことから界面Ｂにおけ
る接続状態が向上し、当該部分における接続不良が減少
するものと推測される。On the other hand, in the case of the printed wiring board of the present invention shown in FIG. 4, the catalyst nucleus 24 is applied after the copper plating 26 is deposited on the inner end portion 25a in advance by electroless copper plating or electrolytic copper plating. . That is, in this method, the through-hole plating 25 is deposited on the relatively smooth copper plating 26, not on the inner end portion 21a having a rough surface. Further, this method is characterized in that no impurities are present at the interface B between the inner end portion 21a and the copper plating 26. From the above, it is presumed that the connection state at the interface B is improved and the connection failure at that portion is reduced.
【００１４】また、特に請求項１に記載の発明のよう
に、無電解銅めっきによって形成された銅めっき２６で
あることが良い。スルーホールめっき２５と銅めっき２
６との間の接合強度を更に向上させるためには、結晶組
織が近いもの同士の組合せにすることが好ましいからで
ある。Further, it is particularly preferable that the copper plating 26 is formed by electroless copper plating as in the first aspect of the invention. Through hole plating 25 and copper plating 2
This is because, in order to further improve the bonding strength with No. 6, it is preferable to combine those having similar crystal structures.
【００１５】[0015]
【実施例】〔実施例１〕以下、本発明をアディティブプ
ロセスによる多層プリント配線板の製造方法に具体化し
た実施例１を図１に基づき詳細に説明する。EXAMPLE 1 Example 1 in which the present invention is embodied in a method for manufacturing a multilayer printed wiring board by an additive process will be described in detail below with reference to FIG.
【００１６】まず、内層導体回路１ａを備えた基板１の
両面にプリプレグ２ａを設けた後、そのプリプレグ２ａ
の両面にローラコータ等によってアディティブ用接着剤
を塗布する。本実施例では、粗化液に難溶なエポキシ樹
脂（マトリクス）と、粗化液に可溶なエポキシ樹脂微粒
子（フィラー）とを含むアディティブ用接着剤が用いら
れている。前記接着剤を乾燥・硬化させることによって
図１（ａ）に示されるように樹脂絶縁層２を形成した
後、基板１をクロム酸等の粗化液で処理する。この粗化
処理の結果、樹脂絶縁層２の表面には多数のアンカー用
凹部が形成される。First, after the prepregs 2a are provided on both surfaces of the substrate 1 having the inner conductor circuit 1a, the prepregs 2a are formed.
Adhesive adhesive is applied to both surfaces of the above with a roller coater or the like. In this embodiment, an adhesive for additives containing an epoxy resin (matrix) which is hardly soluble in the roughening liquid and fine epoxy resin particles (filler) soluble in the roughening liquid is used. After the resin insulating layer 2 is formed by drying and curing the adhesive as shown in FIG. 1A, the substrate 1 is treated with a roughening liquid such as chromic acid. As a result of this roughening treatment, a large number of anchor recesses are formed on the surface of the resin insulating layer 2.
【００１７】次に、図１（ｂ）に示されるように、ドリ
ル加工によって基板１の所定位置にスルーホール形成用
孔３を透設する。スルーホール形成用孔３の内壁面３ａ
は、ドリルに削りとられることによって粗面化する。そ
の後、基板１をデスミア液で処理することによって、ス
ルーホール形成用孔３の内壁面３ａに発生したスミアを
除去する。Next, as shown in FIG. 1B, a through hole forming hole 3 is provided at a predetermined position of the substrate 1 by drilling. Inner wall surface 3a of the through hole forming hole 3
Roughens by being cut by a drill. After that, the substrate 1 is treated with a desmear solution to remove smear generated on the inner wall surface 3a of the through-hole forming hole 3.
【００１８】基板１を酸処理した後、無電解銅めっき浴
を用いてめっきを行う。この無電解銅めっき工程によっ
て、図１（ｃ）に示されるようにスルーホール形成用孔
３の内壁面３ａに露出している内層導体回路１ａの一
部、即ち内端部１ｂに、厚さ約２μｍの銅めっき４を析
出させる。After acid-treating the substrate 1, plating is performed using an electroless copper plating bath. By this electroless copper plating step, as shown in FIG. 1C, the thickness of a part of the inner layer conductor circuit 1a exposed on the inner wall surface 3a of the through hole forming hole 3, that is, the inner end portion 1b, is increased. A copper plating 4 of about 2 μm is deposited.
【００１９】ここで基板１の表面を脱脂した後、常法
（キャタリスト−アクセラレータ法）に従って基板１を
所定の処理液で処理する。この処理によって、図１
（ｄ）に示されるように樹脂絶縁層２の表面全体及び前
記内壁面３ａ全体に、無電解銅めっきの最初の析出に必
要なＰｄ触媒核５が付与される。なお、本実施例の場
合、Ｐｄ触媒核５は内端部１ｂにではなく銅めっき４上
に付与される。After degreasing the surface of the substrate 1, the substrate 1 is treated with a predetermined treatment liquid according to a conventional method (catalyst-accelerator method). By this process,
As shown in (d), the Pd catalyst nucleus 5 necessary for the first deposition of the electroless copper plating is applied to the entire surface of the resin insulating layer 2 and the entire inner wall surface 3a. In the case of the present embodiment, the Pd catalyst nucleus 5 is applied not on the inner end portion 1b but on the copper plating 4.
【００２０】次に、図１（ｅ）に示されるように、樹脂
絶縁層２上に感光性樹脂製のめっきレジスト６をラミネ
ートした後、露光・現像を行う。この後、めっき前処理
として基板１を塩酸等で処理することにより、基板１に
付与されたＰｄ触媒核５を活性化する。そして、基板１
を上記の無電解銅めっき浴に浸漬することによって、図
１（ｆ）に示されるように内壁面３ａ等に厚さ約２０μ
ｍのスルーホールめっき７を析出させる。以下、所定の
プロセスを経ることによって、最終的にはスルーホール
８を介して内層導体回路１ａと外層導体回路９とが接続
された多層プリント配線板が得られる。Next, as shown in FIG. 1E, a plating resist 6 made of a photosensitive resin is laminated on the resin insulating layer 2 and then exposed and developed. Then, the Pd catalyst nucleus 5 provided on the substrate 1 is activated by treating the substrate 1 with hydrochloric acid or the like as a pretreatment for plating. And the substrate 1
By soaking it in the above electroless copper plating bath, as shown in FIG. 1 (f), the inner wall surface 3a etc. has a thickness of about 20 μm.
m through-hole plating 7 is deposited. Thereafter, a predetermined process is performed to finally obtain a multilayer printed wiring board in which the inner layer conductor circuit 1a and the outer layer conductor circuit 9 are connected via the through holes 8.
【００２１】さて、得られた多層プリント配線板を用い
てヒートサイクル試験（260 ℃で10秒, 20℃で20秒×30
サイクルのオイルディップ）を行ったところ、接続不良
の発生率は０％であった。一方、従来の製造方法によっ
て得られた比較例の多層プリント配線板を用いて同じ試
験を行ったところ、接続不良の発生率は１．８％であっ
た。A heat cycle test (10 seconds at 260 ° C., 20 seconds at 20 ° C. × 30 seconds) was performed using the obtained multilayer printed wiring board.
When a cycle oil dip) was performed, the incidence of connection failure was 0%. On the other hand, when the same test was performed using the multilayer printed wiring board of the comparative example obtained by the conventional manufacturing method, the incidence of connection failure was 1.8%.
【００２２】以上の結果から明らかなように、実施例１
の方法に従えば界面における接続不良が確実に解消され
ることがわかる。従って、極めて接続信頼性に優れた多
層プリント配線板が得られる結果となる。つまり、この
方法によると、電解銅からなる内層導体回路１ａと無電
解銅からなるスルーホールめっき７との間に、無電解銅
からなる銅めっき４が介在した状態となる。この場合、
結晶組織が近いもの同士であるスルーホールめっき７と
銅めっき４とが接することによって、両者間の接合強度
が向上する。 〔実施例２〕以下、本発明をサブトラクティブプロセス
による多層プリント配線板の製造方法に具体化した実施
例２を図２に基づき詳細に説明する。As is clear from the above results, Example 1
It can be seen that the connection failure at the interface is surely eliminated by following the method of. As a result, a multilayer printed wiring board having excellent connection reliability can be obtained. That is, according to this method, the copper plating 4 made of electroless copper is interposed between the inner layer conductor circuit 1a made of electrolytic copper and the through-hole plating 7 made of electroless copper. in this case,
When the through-hole plating 7 and the copper plating 4, which have similar crystal structures, come into contact with each other, the joint strength between the two is improved. [Embodiment 2] Hereinafter, Embodiment 2 in which the present invention is embodied in a method for manufacturing a multilayer printed wiring board by a subtractive process will be described in detail with reference to FIG.
【００２３】まず、絶縁性の基材の両面に銅箔を貼着し
た銅張積層板などを出発材料として用い、表裏両面に内
層導体回路１１ａを持つ基板１１を作製する。次に、図
２（ａ）に示されるように、その基板１１の両面に層間
絶縁層１２となるプリプレグ１２ａと、銅箔１２ｂとを
積層しかつラミネートを行う。First, a substrate 11 having inner layer conductor circuits 11a on both front and back surfaces is prepared by using, as a starting material, a copper clad laminate in which copper foil is attached to both surfaces of an insulating base material. Next, as shown in FIG. 2A, a prepreg 12a to be the interlayer insulating layer 12 and a copper foil 12b are laminated and laminated on both surfaces of the substrate 11.
【００２４】次に、図２（ｂ）に示されるように、ドリ
ル加工によって基板１１の所定位置にスルーホール形成
用孔１３を透設する。スルーホール形成用孔１３の内壁
面１３ａは、ドリルによって削り取られることによって
粗面化する。その後、基板１１をデスミア液で処理する
ことによって、スルーホール形成用孔１３の内壁面１３
ａに発生したスミアを除去する。Next, as shown in FIG. 2B, a through hole forming hole 13 is formed at a predetermined position of the substrate 11 by drilling. The inner wall surface 13a of the through hole forming hole 13 is roughened by being scraped off by a drill. Then, the substrate 11 is treated with a desmear solution to remove the inner wall surface 13 of the through hole forming hole 13.
The smear generated in a is removed.
【００２５】基板１１を酸処理した後、無電解銅めっき
浴を用いてめっきを行う。そして、図２（ｃ）に示され
るように、内壁面１３ａに露出している内層導体回路１
１ａの一部、即ち内端部１１ｂに、厚さ約２μｍの銅め
っき１４を析出させる。After treating the substrate 11 with an acid, plating is performed using an electroless copper plating bath. Then, as shown in FIG. 2C, the inner layer conductor circuit 1 exposed on the inner wall surface 13a.
A copper plating 14 having a thickness of about 2 μm is deposited on a part of 1a, that is, the inner end 11b.
【００２６】ここでプリプレグ１２ａの表面の銅箔１２
ｂを脱脂した後、常法（キャタリスト−アクセラレータ
法）に従って基板１１を所定の処理液で処理する。この
処理によって、図２（ｄ）に示されるように銅箔１２ｂ
の表面全体及び内壁面１３ａ全体に、無電解銅めっきの
最初の析出に必要なＰｄ触媒核１５が付与される。な
お、本実施例の場合、Ｐｄ触媒核１５は内端部１１ｂに
ではなく銅めっき１４上に付与される。Here, the copper foil 12 on the surface of the prepreg 12a
After degreasing b, the substrate 11 is treated with a predetermined treatment liquid according to a conventional method (catalyst-accelerator method). By this treatment, as shown in FIG. 2 (d), the copper foil 12b
The Pd catalyst nuclei 15 necessary for the first deposition of the electroless copper plating are provided on the entire surface and the entire inner wall surface 13a. In the case of the present embodiment, the Pd catalyst nucleus 15 is applied not on the inner end 11b but on the copper plating 14.
【００２７】この後、めっき前処理として基板１１を塩
酸等で処理することにより、基板１１に付与されたＰｄ
触媒核１５を活性化する。そして、基板１１に対する無
電解銅めっき及び電解銅めっきによって、図２（ｄ）に
示されるように内壁面１３ａ等に厚さ約２０μｍのスル
ーホールめっき１６を析出させる。なお、図２では図面
作成の便宜上、無電解銅めっきと電解めっきとの境界を
省略している。After that, as a pretreatment for plating, the substrate 11 is treated with hydrochloric acid or the like, so that the Pd applied to the substrate 11 is removed.
The catalyst core 15 is activated. Then, by electroless copper plating and electrolytic copper plating on the substrate 11, a through-hole plating 16 having a thickness of about 20 μm is deposited on the inner wall surface 13a and the like as shown in FIG. 2D. In FIG. 2, the boundary between electroless copper plating and electrolytic plating is omitted for convenience of drawing.
【００２８】次に、図２（ｅ）に示されるように、基板
１１の表裏両面に感光性樹脂製のエッチングレジスト１
７をラミネートした後、露光・現像を行う。この後、銅
を溶解し得るエッチャントを用いたエッチングによっ
て、図２（ｆ）に示されるように、基板１１の表裏両面
に外層導体回路１８を形成する。以下、所定のプロセス
を経ることによって、最終的にはスルーホール１９を介
して内層導体回路１１ａと外層導体回路１８とが接続さ
れた多層プリント配線板が得られる。Next, as shown in FIG. 2E, an etching resist 1 made of a photosensitive resin is formed on both front and back surfaces of the substrate 11.
After laminating No. 7, exposure and development are performed. After that, the outer layer conductor circuits 18 are formed on both the front and back surfaces of the substrate 11 by etching using an etchant capable of dissolving copper, as shown in FIG. Thereafter, a predetermined process is performed to finally obtain a multilayer printed wiring board in which the inner layer conductor circuit 11a and the outer layer conductor circuit 18 are connected via the through holes 19.
【００２９】さて、得られた多層プリント配線板を用い
て実施例１と同様のヒートサイクル試験を行ったとこ
ろ、本実施例についても接続不良の発生率は０％であっ
た。以上の結果から明らかなように、実施例２の方法で
あっても界面における接続不良が確実に解消されること
がわかる。従って、前記実施例１の場合と同じく、極め
て接続信頼性に優れた多層プリント配線板が得られる結
果となる。つまり、この方法によると、電解銅からなる
内層導体回路１１ａと無電解銅からなるスルーホールめ
っき１６との間に、無電解銅からなる銅めっき１４が介
在した状態となる。この場合、結晶組織が近いもの同士
であるスルーホールめっき１６と銅めっき１４とが接す
ることによって、両者間の接合強度が向上する。When a heat cycle test similar to that of Example 1 was conducted using the obtained multilayer printed wiring board, the occurrence rate of connection failure was 0% also in this example. As is clear from the above results, even with the method of Example 2, the connection failure at the interface can be reliably eliminated. Therefore, as in the case of Example 1, the result is that a multilayer printed wiring board having extremely excellent connection reliability can be obtained. That is, according to this method, the copper plating 14 made of electroless copper is interposed between the inner layer conductor circuit 11a made of electrolytic copper and the through-hole plating 16 made of electroless copper. In this case, the through-hole plating 16 and the copper plating 14, which have similar crystal structures, come into contact with each other, so that the joint strength between the two is improved.
【００３０】なお、本発明は上記実施例のみに限定され
ることはなく、以下のように変更することが可能であ
る。例えば、 （ａ）内端部とスルーホールめっきとの間に介在される
銅めっきは無電解めっきによるものに限定されるわけで
はなく、電解めっきによるものであっても勿論良い。こ
の場合であっても、スルーホールめっきと内層導体回路
との間の接合強度を向上させることができる。The present invention is not limited to the above embodiment, but can be modified as follows. For example, (a) the copper plating interposed between the inner end portion and the through-hole plating is not limited to electroless plating, but may be electrolytic plating. Even in this case, the joint strength between the through-hole plating and the inner conductor circuit can be improved.
【００３１】（ｂ）Ｐｄ触媒核に代えて、他の金属触媒
核を使用しても良い。 （ｃ）スルーホールめっきを形成する場合、無電解銅め
っきと電解銅めっきとを行う実施例２に代えて、無電解
めっきのみによることとしても良い。(B) Instead of the Pd catalyst nucleus, another metal catalyst nucleus may be used. (C) When forming the through-hole plating, only electroless plating may be used instead of the second embodiment in which electroless copper plating and electrolytic copper plating are performed.
【００３２】[0032]
【発明の効果】以上詳述したように、本発明のプリント
配線板の製造方法によれば、内層導体回路とスルーホー
ルとの間の接続不良を確実に低減することができ、接続
信頼性を向上させることができるという優れた効果を奏
する。As described above in detail, according to the method for manufacturing a printed wiring board of the present invention, the connection failure between the inner layer conductor circuit and the through hole can be surely reduced and the connection reliability can be improved. It has an excellent effect that it can be improved.
【図１】（ａ）〜（ｆ）は実施例１におけるプリント配
線板の製造方法を示す部分概略断面図である。1A to 1F are partial schematic cross-sectional views showing a method for manufacturing a printed wiring board according to a first embodiment.
【図２】（ａ）〜（ｆ）は実施例２におけるプリント配
線板の製造方法を示す部分概略断面図である。2 (a) to (f) are partial schematic cross-sectional views showing a method for manufacturing a printed wiring board in Example 2. FIG.
【図３】（ａ）〜（ｃ）は本発明の製造方法によって作
製されたプリント配線板において、内層導体回路とスル
ーホールとの界面の様子を示す要部拡大概略断面図であ
る。3 (a) to 3 (c) are enlarged schematic cross-sectional views showing a state of an interface between an inner layer conductor circuit and a through hole in a printed wiring board manufactured by the manufacturing method of the present invention.
【図４】（ａ）〜（ｃ）は従来の製造方法によって作製
されたプリント配線板において、内層導体回路とスルー
ホールとの界面の様子を示す要部拡大概略断面図であ
る。4 (a) to 4 (c) are enlarged schematic cross-sectional views showing a state of an interface between an inner layer conductor circuit and a through hole in a printed wiring board manufactured by a conventional manufacturing method.
１，１１…基板、１ａ，１１ａ…内層導体回路、１ｂ，
１１ｂ…内端部、３，１３…スルーホール形成用孔、３
ａ，１３ａ…（スルーホール形成用孔の）内壁面、４，
１４…銅めっき、５，１５…（Ｐｄ）触媒核、７，１６
…スルーホールめっき、Ｂ…界面。1, 11 ... Substrate, 1a, 11a ... Inner layer conductor circuit, 1b,
11b ... Inner end portions, 3, 13 ... Through-hole forming holes, 3
a, 13a ... Inner wall surface (of through-hole forming hole), 4,
14 ... Copper plating, 5, 15 ... (Pd) catalyst nucleus, 7, 16
… Through-hole plating, B… interface.
Claims (2)
形成用孔を透設し、そのスルーホール形成用孔の内壁面
に触媒核を付与した後、無電解銅めっきによって前記ス
ルーホール形成用孔の内壁面全体にスルーホールめっき
を析出させるプリント配線板の製造方法において、 触媒核を付与する工程の前に無電解銅めっきを行うこと
によって、前記スルーホール形成用孔の内壁面に露出し
ている前記内層導体回路の一部に銅めっきを析出させる
ことを特徴としたプリント配線板の製造方法。1. A through hole forming hole is provided through a substrate having an inner layer conductor circuit, a catalyst nucleus is provided on the inner wall surface of the through hole forming hole, and the through hole forming hole is formed by electroless copper plating. In the method for manufacturing a printed wiring board in which through-hole plating is deposited on the entire inner wall surface of the through hole, by exposing the inner wall surface of the through-hole forming hole by performing electroless copper plating before the step of applying the catalyst nucleus. A method of manufacturing a printed wiring board, characterized in that copper plating is deposited on a part of the inner layer conductor circuit that is present.
形成用孔を透設し、そのスルーホール形成用孔の内壁面
に触媒核を付与した後、無電解銅めっきによって前記ス
ルーホール形成用孔の内壁面全体にスルーホールめっき
を析出させるプリント配線板の製造方法において、 触媒核を付与する工程の前に電解銅めっきを行うことに
よって、前記スルーホール形成用孔の内壁面に露出して
いる前記内層導体回路の一部に銅めっきを析出させるこ
とを特徴としたプリント配線板の製造方法。2. A through hole forming hole is provided through a substrate having an inner layer conductor circuit, a catalyst nucleus is provided on the inner wall surface of the through hole forming hole, and then the through hole forming hole is formed by electroless copper plating. In a method for manufacturing a printed wiring board in which through-hole plating is deposited on the entire inner wall surface of the through hole, the copper is exposed to the inner wall surface of the through-hole forming hole by performing electrolytic copper plating before the step of applying the catalyst nucleus. A method for producing a printed wiring board, characterized in that copper plating is deposited on a part of the inner layer conductor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31704893A JP3217563B2 (en) | 1993-12-16 | 1993-12-16 | Manufacturing method of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31704893A JP3217563B2 (en) | 1993-12-16 | 1993-12-16 | Manufacturing method of printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07170078A true JPH07170078A (en) | 1995-07-04 |
| JP3217563B2 JP3217563B2 (en) | 2001-10-09 |
Family
ID=18083841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31704893A Expired - Lifetime JP3217563B2 (en) | 1993-12-16 | 1993-12-16 | Manufacturing method of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3217563B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104144571A (en) * | 2014-06-18 | 2014-11-12 | 四川深北电路科技有限公司 | High-density interconnection integrated circuit board manufacturing method |
| CN105072825A (en) * | 2015-09-08 | 2015-11-18 | 深圳市迅捷兴电路技术有限公司 | Fabrication method of linear impedance circuit board |
-
1993
- 1993-12-16 JP JP31704893A patent/JP3217563B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104144571A (en) * | 2014-06-18 | 2014-11-12 | 四川深北电路科技有限公司 | High-density interconnection integrated circuit board manufacturing method |
| CN105072825A (en) * | 2015-09-08 | 2015-11-18 | 深圳市迅捷兴电路技术有限公司 | Fabrication method of linear impedance circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3217563B2 (en) | 2001-10-09 |
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