JPH07161996A - Insulated-gate field-effect device and its manufacture - Google Patents
Insulated-gate field-effect device and its manufactureInfo
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- JPH07161996A JPH07161996A JP5311519A JP31151993A JPH07161996A JP H07161996 A JPH07161996 A JP H07161996A JP 5311519 A JP5311519 A JP 5311519A JP 31151993 A JP31151993 A JP 31151993A JP H07161996 A JPH07161996 A JP H07161996A
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- sio
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁ゲート型電界効果半
導体装置及びその製造方法に関し、より詳細には低温プ
ロセスで製造することのできる絶縁ゲート型電界効果半
導体装置及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect semiconductor device and its manufacturing method, and more particularly to an insulated gate field effect semiconductor device which can be manufactured by a low temperature process and its manufacturing method. .
【０００２】[0002]
【従来の技術】近年、ガラス基板を用いることにより、
６００℃程度の低温プロセスで、ディスプレイやイメー
ジセンサ等の大面積な部分に薄膜トランジスタ（以下Ｔ
ＦＴと略す）が作製されるようになっている。2. Description of the Related Art Recently, by using a glass substrate,
In a low temperature process of about 600 ° C, thin film transistors (hereinafter referred to as T
Abbreviated as FT).
【０００３】ＴＦＴのチャネル半導体層にポリＳｉある
いはアモルファスＳｉを、ゲート絶縁膜にＳｉＯ2膜を
用いた場合、そのＴＦＴの製造時の熱処理温度は約６０
０℃以下である。このため、ゲート絶縁膜のＳｉＯ2膜
を作製するためには、低温成膜が可能であるプラズマＣ
ＶＤ法(例えば、Jounal of Applied Physics Vol.60(9)
p3136 (1986))、リモートプラズマＣＶＤ法(例えば、J
ounal of Vacuum Science Technology A5(4) p2231 (19
87))、ＡＰＣＶＤ法、ＬＰＣＶＤ法、スパッタリング法
(例えば、IEEE Trans.Electron Devices 135(12) p3104
(1989))等の堆積法によるゲート絶縁膜の形成が行われ
ている。ところが、これらの方法で得られたＳｉＯ2膜
は緻密なものではないためＴＦＴの信頼性の低下の原因
となる。When poly-Si or amorphous Si is used for the channel semiconductor layer of the TFT and a SiO 2 film is used for the gate insulating film, the heat treatment temperature at the time of manufacturing the TFT is about 60.
It is 0 ° C or lower. Therefore, in order to form the SiO 2 film of the gate insulating film, plasma C which can be formed at a low temperature can be used.
VD method (eg, Jounal of Applied Physics Vol. 60 (9)
p3136 (1986)), remote plasma CVD method (for example, J
ounal of Vacuum Science Technology A5 (4) p2231 (19
87)), APCVD method, LPCVD method, sputtering method
(For example, IEEE Trans.Electron Devices 135 (12) p3104
(1989)) and the like are used to form a gate insulating film. However, since the SiO 2 film obtained by these methods is not dense, it causes a decrease in the reliability of the TFT.
【０００４】また、これらのＳｉＯ2膜の緻密化の方法
としてはＮ2雰囲気中において９００℃程度の高温アニ
ールやランプアニール等があるが、いずれも６００℃以
上の高温熱処理で行わないと、高品質なゲート絶縁膜が
得られない。Further, as a method of densifying these SiO 2 films, there is a high temperature anneal at about 900 ° C. or a lamp anneal in an N 2 atmosphere. A quality gate insulating film cannot be obtained.
【０００５】さらに、ＳｉＯ2膜の窒化により、ホット
キャリア注入に強い信頼性の高いトランジスタを得る技
術が従来報告されている(例えば、IEEE Trans.Electron
Devices ED-29 p498 (1982))が、ここでも窒化を行う
ためには９００℃以上の高温が必要である。Further, a technique for obtaining a highly reliable transistor which is resistant to hot carrier injection by nitriding a SiO 2 film has been conventionally reported (for example, IEEE Trans. Electron.
Devices ED-29 p498 (1982)) also require high temperatures of 900 ° C or higher to perform nitriding.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記方
法で作製されたゲート絶縁膜は比較的高温での作製とな
るか、あるいは６００℃以下の低温作製をすると緻密で
高品質なものが得られず、ＳｉＯ2膜中に多量のトラッ
プを含んでいるためＴＦＴ特性に悪影響を及ぼす。ま
た、これらのトラップがホットエレクトロン注入の原因
となるため、素子の信頼性に対しても問題となる。ま
た、低温形成のために界面準位密度も高く、良好な界面
が形成されにくい。一方、熱歪み等から低温でのＴＦＴ
作製の要望も強い。However, if the gate insulating film produced by the above method is produced at a relatively high temperature, or if it is produced at a low temperature of 600 ° C. or less, a dense and high quality product cannot be obtained. , The SiO 2 film contains a large amount of traps, which adversely affects the TFT characteristics. Further, since these traps cause hot electron injection, there is a problem in reliability of the device. In addition, since the interface state density is high because of low temperature formation, it is difficult to form a good interface. On the other hand, due to thermal distortion, etc., TFT at low temperature
There are strong demands for fabrication.
【０００７】本発明は、このような問題に鑑みなされた
ものであり、界面近傍のＳｉＯ2膜の緻密化と界面原子
のネットワークを再構成させることで、界面準位密度を
減少させ、界面付近にＳｉＯＮ層を導入することでホッ
トエレクトロン注入に対して強いゲート絶縁膜を形成し
て、比較的低温で高品質なゲート絶縁膜を得ることを目
的としている。The present invention has been made in view of such a problem. The density of the interface state is reduced by densifying the SiO 2 film near the interface and reconfiguring the network of interface atoms, thereby reducing the interface state density. The purpose is to form a SiON layer to form a gate insulating film that is strong against hot electron injection, and obtain a high-quality gate insulating film at a relatively low temperature.
【０００８】[0008]
【課題を解決するための手段】請求項１に記載の本発明
の絶縁ゲート型電界効果半導体装置は、絶縁基板上に形
成されたポリＳｉ層と、該ポリＳｉ層上に形成されたＳ
ｉＯＮ層と該ＳｉＯＮ層上に形成されたＳｉＯ2層とか
らなる絶縁ゲート層と、該絶縁ゲート層上に形成された
ゲート電極とを備えたことを特徴とする。According to another aspect of the present invention, there is provided an insulated gate field effect semiconductor device including a poly Si layer formed on an insulating substrate and an S formed on the poly Si layer.
It is characterized by comprising an insulated gate layer formed of an iON layer and a SiO 2 layer formed on the SiON layer, and a gate electrode formed on the insulated gate layer.
【０００９】請求項２に記載の本発明の絶縁ゲート型電
界効果半導体装置は、絶縁基板上に形成されたポリＳｉ
層と、該ポリＳｉ層上に形成されたＳｉＯＮ層と該Ｓｉ
ＯＮ層上に形成されたＳｉＯ2層とからなる絶縁ゲート
層と、該絶縁ゲート層上に形成されたゲート電極と、上
記ポリＳｉ層表面にソース領域とドレイン領域とを備
え、ＴＦＴをなしていることを特徴とする。According to another aspect of the present invention, there is provided an insulated gate field effect semiconductor device including poly-Si formed on an insulating substrate.
Layer, a SiON layer formed on the poly-Si layer, and the Si
An insulated gate layer formed of an SiO 2 layer formed on the ON layer, a gate electrode formed on the insulated gate layer, and a source region and a drain region on the surface of the poly-Si layer are provided to form a TFT. It is characterized by being
【００１０】請求項３に記載の本発明の絶縁ゲート型電
界効果半導体装置は、請求項１また請求項２に記載の絶
縁ゲート型電界効果半導体装置において、上記ＳｉＯＮ
層の厚さが１ｎｍ以上１０ｎｍ以下であることを特徴と
する。An insulated gate field effect semiconductor device according to a third aspect of the present invention is the insulated gate field effect semiconductor device according to the first or second aspect, wherein
The layer thickness is 1 nm or more and 10 nm or less.
【００１１】請求項４に記載の本発明の絶縁ゲート型電
界効果半導体装置の製造方法は、請求項１、請求項２、
または請求項３に記載の絶縁ゲート型電界効果半導体装
置の製造方法において、絶縁基板上にポリＳｉ層を形成
する工程と、該ポリＳｉ層上に第１のＳｉＯ2層を形成
する工程と、第１のＳｉＯ2層をプラズマ窒化してＳｉ
ＯＮ層とする工程と、該ＳｉＯＮ層上に第２のＳｉＯ2
層を形成する工程と、第２のＳｉＯ2層上に導電膜を形
成してゲート電極を形成する工程とを含むことを特徴と
する。A method of manufacturing an insulated gate field effect semiconductor device according to a fourth aspect of the present invention is the method according to the first aspect, the second aspect, or the second aspect.
Alternatively, in the method for manufacturing the insulated gate field effect semiconductor device according to claim 3, a step of forming a poly-Si layer on the insulating substrate, and a step of forming a first SiO 2 layer on the poly-Si layer, Plasma nitriding the first SiO 2 layer to form Si
A step of forming an ON layer and a second SiO 2 layer on the SiON layer.
The method is characterized by including a step of forming a layer and a step of forming a conductive film on the second SiO 2 layer to form a gate electrode.
【００１２】[0012]
【作用】本発明によれば、極薄（１〜１０ｎｍ程度）の
絶縁膜を作製した後、引き続きＮ（窒素）を含むガスの
プラズマでプラズマ窒化処理することで、界面近傍の絶
縁膜の緻密化と界面原子の再構成を行い、３配位のＮが
界面準位密度を減少させ良好な界面を得ることで、高移
動度、Ｖｔｈ、Ｓ係数の低いＴＦＴ特性を得ることが可
能となる。また、界面近傍のＳｉＯＮ層がホットエレク
トロン注入に対して強くなるため、信頼性に優れたＴＦ
Ｔを得ることができる。According to the present invention, after forming an extremely thin (about 1 to 10 nm) insulating film, plasma nitriding treatment is subsequently performed with plasma of a gas containing N (nitrogen), so that the insulating film near the interface becomes dense. And the reconstruction of the interface atoms to reduce the interface state density of tricoordinate N and obtain a good interface, whereby it becomes possible to obtain TFT characteristics with high mobility, low Vth, and S coefficient. . In addition, since the SiON layer near the interface becomes strong against hot electron injection, the TF has excellent reliability.
T can be obtained.
【００１３】なお、本発明では製造工程におけるゲート
絶縁膜のＳｉＯ2膜を作製する工程を３つに分け、まず
最初に極薄い（１〜１０ｎｍ程度が最も望ましい）Ｓｉ
Ｏ2膜をチャネル半導体上に作製し、次にＮ2等のＮ原子
を含むガス（例えばＮＨ3，Ｎ2Ｏ等）のプラズマでＳｉ
Ｏ2上からプラズマ処理を行う。最後に必要なＳｉＯ2膜
を成膜してゲート絶縁膜を構成する。この時、初期Ｓｉ
Ｏ2の膜厚が厚すぎる（通常１０ｎｍ以上）と界面付近
のＳｉＯ2膜に対するプラズマ処理の効果小さく、薄す
ぎる（通常１ｎｍ以下）とプラズマによるチャネル半導
体へのダメージが問題となるため、プラズマ処理の条件
に応じた最適膜厚範囲が存在する。In the present invention, the step of manufacturing the SiO 2 film of the gate insulating film in the manufacturing process is divided into three steps, and first, an extremely thin (about 1 to 10 nm is most preferable) Si film is formed.
An O 2 film is formed on the channel semiconductor, and then Si is formed by plasma of a gas containing N atoms such as N 2 (for example, NH 3 , N 2 O, etc.).
Plasma treatment is performed from above O 2 . Finally, a necessary SiO 2 film is formed to form a gate insulating film. At this time, the initial Si
If the film thickness of O 2 is too thick (usually 10 nm or more), the effect of plasma treatment on the SiO 2 film in the vicinity of the interface is small, and if it is too thin (usually 1 nm or less), plasma damage to the channel semiconductor poses a problem. There is an optimum film thickness range according to the condition of.
【００１４】[0014]
【実施例】以下に、本発明の実施例に係るＴＦＴの製造
方法を図面に基づいて説明する。なお、ここではチャネ
ル半導体としてポリＳｉ膜を用いているが、他のＳｉ系
半導体として、アモルファスＳｉ，単結晶Ｓｉ，ＳｉＧ
ｅ等を用いることも可能である。また、以下の実施例で
はＴＦＴについて説明するが、後述するソース、ドレイ
ンの形成を行わないことにより、ただ単にキャパシタの
ゲート絶縁膜として用い得ることは明白である。さら
に、ゲート絶縁膜直下にＶｔｈ等を調整するため適宜不
純物を上記ポリＳｉ膜に導入することも可能である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a TFT according to an embodiment of the present invention will be described below with reference to the drawings. Although a poly-Si film is used as the channel semiconductor here, other Si-based semiconductors include amorphous Si, single crystal Si, and SiG.
It is also possible to use e or the like. Further, although a TFT will be described in the following embodiments, it is obvious that the TFT can be simply used as a gate insulating film of a capacitor by not forming a source and a drain described later. Further, it is possible to appropriately introduce impurities into the poly-Si film in order to adjust Vth and the like immediately below the gate insulating film.
【００１５】まず、図１（ａ）に示すように、約６００
℃の熱処理に耐える歪み点温度の高いガラス基板１上に
Ｓｉ2Ｈ6ガスでＬＰＣＶＤ法により約４５０℃の基板温
度でアモルファスＳｉ膜を成膜する。このアモルファス
Ｓｉ膜をＮ2雰囲気中において６００℃で約２０時間ア
ニールして、固相成長によりポリＳｉ膜を得、エッチン
グにより所望の形にアイランド化し、半導体層２を形成
する。First, as shown in FIG. 1 (a), about 600
An amorphous Si film is formed at a substrate temperature of about 450 ° C. by a LPCVD method using Si 2 H 6 gas on a glass substrate 1 having a high strain point temperature that can withstand a heat treatment at a temperature of ° C. The amorphous Si film is annealed at 600 ° C. for about 20 hours in an N 2 atmosphere to obtain a poly Si film by solid phase growth, and is etched into an island in a desired shape to form the semiconductor layer 2.
【００１６】次に、図１（ｂ）に示すように、この半導
体層２上にゲート絶縁膜となるＳｉＯ2膜３をリモート
プラズマＣＶＤ法により、膜厚１〜１０ｎｍ程度、本実
施例では５ｎｍ成膜する。リモートプラズマＣＶＤ法に
よる成膜条件は基板温度３００℃、反応圧力０．２Ｔｏ
ｒｒ，ＳｉＨ4流量１ｓｃｃｍ，Ｏ2流量５０ｓｃｃｍ，
ＲＦパワー２００Ｗで行った。この際のＳｉＯ2膜３の
成膜方法はリモートプラズマＣＶＤ法に限らず、低温成
膜が可能であればプラズマＣＶＤ法、ＥＣＲＣＶＤ法、
ＬＰＣＶＤ法、ＡＰＣＶＤ法等でもよい。また、ＳｉＯ
2膜３の膜厚は１０ｎｍ以上では、後述するプラズマ処
理の効果が少ないため、１０ｎｍ以下が望ましい。ま
た、膜厚の範囲はプラズマ処理装置や処理条件に依存し
て異なるが、１ｎｍ以下と薄すぎると半導体層２に対す
るダメージがあり、１０ｎｍ以上と厚すぎるとＮ（窒
素）の界面（半導体層２とプラズマ処理したＳｉＯ2膜
３との界面）への拡散が行われないため、それぞれプラ
ズマ処理の効果が減少する。従って、ＳｉＯ2膜３の膜
厚は１ｎｍ以上１０ｎｍ以下が望ましい。Next, as shown in FIG. 1B, a SiO 2 film 3 to be a gate insulating film is formed on the semiconductor layer 2 by a remote plasma CVD method to a film thickness of about 1 to 10 nm, in this embodiment 5 nm. Form a film. The film formation conditions by the remote plasma CVD method are a substrate temperature of 300 ° C. and a reaction pressure of 0.2 To.
rr, SiH 4 flow rate 1 sccm, O 2 flow rate 50 sccm,
The RF power was 200 W. The method of forming the SiO 2 film 3 at this time is not limited to the remote plasma CVD method, and if the low temperature film formation is possible, the plasma CVD method, the ECRCVD method,
An LPCVD method, an APCVD method or the like may be used. Also, SiO
If the film thickness of the two films 3 is 10 nm or more, the effect of the plasma treatment described later is small, so 10 nm or less is desirable. Although the range of the film thickness varies depending on the plasma processing apparatus and the processing conditions, if the thickness is less than 1 nm, the semiconductor layer 2 will be damaged, and if it is more than 10 nm, the interface of the N (nitrogen) (semiconductor layer 2) will be damaged. And the plasma-treated SiO 2 film 3) is not diffused, so that the effect of the plasma treatment is reduced. Therefore, the film thickness of the SiO 2 film 3 is preferably 1 nm or more and 10 nm or less.
【００１７】次に、図１（ｃ）に示すように、引き続い
て１０分間、Ｎ2プラズマでプラズマ処理（ここではＮ2
ガスを用いているが、例えばＮ2ＯやＮＨ3等のＮを含む
ガスであれば特にガスは限定されない）して、ＳｉＯ2
膜３をＳｉＯＮ膜にする。ここで、ＳｉＯ2膜３すべて
をＳｉＯＮ膜に変化させなくてもよい。また、この時の
プラズマ処理の条件は基板温度３００℃，反応圧力０．
５Ｔｏｒｒ，Ｎ2流量１００ｓｃｃｍ，パワー密度０．
１Ｗ／ｃｍ2で行った。なお、プラズマ処理温度は、６
００℃以下であればよい。また、プラズマ処理をここで
は平行平板プラズマＣＶＤ装置で行っているが、リモー
トプラズマＣＶＤ装置やＥＣＲＣＶＤ装置で行うことも
可能である。Next, as shown in FIG. 1C, a plasma treatment (N 2 in this case) with N 2 plasma is continued for 10 minutes.
Although a gas is used, the gas is not particularly limited as long as it is a gas containing N such as N 2 O or NH 3 ) and SiO 2
The film 3 is a SiON film. Here, it is not necessary to change the entire SiO 2 film 3 into a SiON film. The conditions of the plasma treatment at this time are as follows: substrate temperature 300 ° C., reaction pressure 0.
5 Torr, N 2 flow rate 100 sccm, power density 0.
It was performed at 1 W / cm 2 . The plasma processing temperature is 6
It may be 00 ° C or lower. Further, although the plasma treatment is performed by the parallel plate plasma CVD apparatus here, it may be performed by a remote plasma CVD apparatus or an ECRCVD apparatus.
【００１８】次に、図１（ｄ）に示すように、ＳｉＯ2
膜３’を膜厚９０〜１００ｎｍ程度、本実施例では９５
ｎｍの厚さでリモートプラズマＣＶＤ装置により成膜し
てプラズマ処理したＳｉＯ2膜３とＳｉＯ2膜３’とから
なるゲート絶縁膜を形成する。Next, as shown in FIG. 1D, SiO 2
The film 3 ′ is formed to have a film thickness of about 90 to 100 nm, and in the present embodiment, 95.
A gate insulating film composed of a SiO 2 film 3 and a SiO 2 film 3 ′, which is formed by a remote plasma CVD apparatus and has a thickness of nm, is plasma-processed.
【００１９】次に、図１（ｅ）に示すように、ガラス基
板１上に膜厚２５０ｎｍ程度のポリシリコンＳｉ膜を成
膜し、所望の形状にパターニングしてゲート電極４を形
成する。これを自己整合的に不純物元素（Ｎｃｈの場合
はリン、Ｐｃｈの場合はボロン）を１×１０15ｉｏｎ／
ｃｍ2，４０ｋｅＶ程度でイオン注入し、活性化を行う
ことにより図示しないＴＦＴのソース及びドレインを形
成する。そして、この工程と同時に不純物イオン注入に
より、ゲート電極４の低抵抗化を行った後、膜厚５００
ｎｍ程度のＳｉＯ2膜からなる層間絶縁膜５を成膜す
る。Next, as shown in FIG. 1E, a polysilicon Si film having a film thickness of about 250 nm is formed on the glass substrate 1 and patterned into a desired shape to form a gate electrode 4. In a self-aligned manner, the impurity element (phosphorus for Nch, boron for Pch) is added at 1 × 10 15 ion /
Ions are implanted at a pressure of about cm 2 and 40 keV and activated to form the source and drain of a TFT (not shown). Then, at the same time as this step, the resistance of the gate electrode 4 is reduced by impurity ion implantation, and then the film thickness 500 is obtained.
An interlayer insulating film 5 made of a SiO 2 film having a thickness of about nm is formed.
【００２０】最後に、図１（ｆ）に示すように、ソー
ス、ドレイン上の層間絶縁膜５にコンタクトホールを形
成した後、例えばアルミニウムの引き出し電極６を形成
し、ＴＦＴは完成する。Finally, as shown in FIG. 1F, a contact hole is formed in the interlayer insulating film 5 on the source and drain, and then an aluminum lead electrode 6 is formed to complete the TFT.
【００２１】このようにしてゲート絶縁膜を３工程に分
けて作製したＴＦＴ特性は下表に示す値を示した。The TFT characteristics of the gate insulating film thus manufactured in three steps are as shown in the table below.
【００２２】[0022]
【表１】 [Table 1]
【００２３】ここでは、比較例として、プラズマ処理な
しでリモートプラズマＣＶＤ法によりＳｉＯ2膜を形成
して作製したＴＦＴ特性を同時に示す。ここで、比較例
として用いたＴＦＴのゲート絶縁膜とプラズマ処理を加
えて作製したＴＦＴのゲート絶縁膜の換算膜厚は等し
い。表から明らかなように、移動度、Ｖｔｈ，Ｓ係数は
プラズマ処理を加えないＳｉＯ2膜でゲート絶縁膜を構
成したＴＦＴ特性に比べて、高移動度、および低いＶｔ
ｈ、低いＳ係数を示しており、界面構造の改善を示して
いる。Here, as a comparative example, TFT characteristics produced by forming a SiO 2 film by a remote plasma CVD method without plasma treatment are also shown. Here, the equivalent thickness of the gate insulating film of the TFT used as the comparative example and the gate insulating film of the TFT manufactured by applying the plasma treatment are the same. As is clear from the table, the mobility, Vth, and S coefficient are higher in mobility and lower in Vt than the TFT characteristics in which the gate insulating film is composed of the SiO 2 film without plasma treatment.
h, a low S coefficient, indicating an improvement in the interface structure.
【００２４】図２に、ゲート印加電界強度８ＭＶ／ｃ
ｍ、大気中温度１５０℃でのＴＤＤＢ特性を示す。この
図から明らかな通りプラズマ処理を加えたゲート絶縁膜
のＴＤＤＢ特性は、プラズマ処理を加えていない特性に
比べて優れた値を示しており、電子の注入の起こりにく
い信頼性の高い絶縁膜になっている。したがって、プラ
ズマ処理を加えたＴＦＴは特性とともに信頼性において
も優れていることがわかる。In FIG. 2, the electric field strength applied to the gate is 8 MV / c.
m, TDDB characteristics at an atmospheric temperature of 150 ° C. As is clear from this figure, the TDDB characteristics of the gate insulating film that has been subjected to the plasma treatment are superior to those of the characteristics that are not subjected to the plasma treatment, and it is possible to obtain a highly reliable insulating film in which electron injection does not easily occur. Has become. Therefore, it is understood that the TFT subjected to the plasma treatment is excellent not only in characteristics but also in reliability.
【００２５】[0025]
【発明の効果】本発明によれば、極薄ＳｉＯ2上からＮ
を含むガスのプラズマで処理することで、界面近傍のＳ
ｉＯ2層の緻密化と界面原子の再構成を行い、界面に３
配位のＮを導入することで界面準位密度を減少させるこ
とで、移動度、Ｖｔｈ、Ｓ係数等のＴＦＴ特性を向上さ
せることが出来る。According to the present invention, N is applied from the ultrathin SiO 2 layer.
By treating with plasma of gas containing
The io 2 layer was densified and the interface atoms were reconstructed,
By introducing the coordinated N to reduce the interface state density, TFT characteristics such as mobility, Vth, and S coefficient can be improved.
【００２６】また、界面層にＳｉＯＮ層が形成されるこ
とでホットエレクトロン注入に対して強くなり、信頼性
の高いＴＦＴを得ることが出来る。Further, since the SiON layer is formed on the interface layer, it becomes strong against hot electron injection, and a highly reliable TFT can be obtained.
【図１】本発明の実施例に係るゲート絶縁膜およびＴＦ
Ｔの製造方法を示す工程断面図である。FIG. 1 is a gate insulating film and TF according to an embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing T.
【図２】本発明の実施例及び比較例により作製したゲー
ト絶縁膜のＴＤＤＢ特性を示すグラフである。FIG. 2 is a graph showing TDDB characteristics of gate insulating films manufactured according to Examples and Comparative Examples of the present invention.
１ ガラス基板 ２ 半導体層 ３ プラズマ処理をしたＳｉＯ2膜 ３’ ＳｉＯ2膜 ４ ゲート電極 ５ 層間絶縁膜 ６ 引き出し電極1 glass substrate 2 semiconductor layer 3 plasma-treated SiO 2 film 3'SiO 2 film 4 gate electrode 5 interlayer insulating film 6 extraction electrode
Claims (4)
該ポリＳｉ層上に形成されたＳｉＯＮ層と該ＳｉＯＮ層
上に形成されたＳｉＯ2層とからなる絶縁ゲート層と、
該絶縁ゲート層上に形成されたゲート電極とを備えたこ
とを特徴とする絶縁ゲート型電界効果半導体装置。1. A poly-Si layer formed on an insulating substrate,
An insulated gate layer comprising a SiON layer formed on the poly-Si layer and a SiO 2 layer formed on the SiON layer;
An insulated gate field effect semiconductor device, comprising: a gate electrode formed on the insulated gate layer.
該ポリＳｉ層上に形成されたＳｉＯＮ層と該ＳｉＯＮ層
上に形成されたＳｉＯ2層とからなる絶縁ゲート層と、
該絶縁ゲート層上に形成されたゲート電極と、上記ポリ
Ｓｉ層表面にソース領域とドレイン領域とを備え、ＴＦ
Ｔをなしていることを特徴とする絶縁ゲート型電界効果
半導体装置。2. A poly-Si layer formed on an insulating substrate,
An insulated gate layer comprising a SiON layer formed on the poly-Si layer and a SiO 2 layer formed on the SiON layer;
A gate electrode formed on the insulated gate layer; and a source region and a drain region on the surface of the poly-Si layer.
An insulated gate field effect semiconductor device having T.
ｎｍ以下であることを特徴とする請求項１また請求項２
に記載の絶縁ゲート型電界効果半導体装置。3. The thickness of the SiON layer is 1 nm or more 10
It is below 1 nm, Claim 1 or Claim 2 characterized by the above-mentioned.
Insulated gate type field effect semiconductor device according to.
と、該ポリＳｉ層上に第１のＳｉＯ2層を形成する工程
と、第１のＳｉＯ2層をプラズマ窒化してＳｉＯＮ層と
する工程と、該ＳｉＯＮ層上に第２のＳｉＯ2層を形成
する工程と、第２のＳｉＯ2層上に導電膜を形成してゲ
ート電極を形成する工程とを含むことを特徴とする請求
項１、請求項２、または請求項３に記載の絶縁ゲート型
電界効果半導体装置の製造方法。Forming a wherein the poly Si layer on an insulating substrate, forming a first SiO 2 layer on the poly-Si layer, and the SiON layer of the first SiO 2 layer to plasma nitriding And a step of forming a second SiO 2 layer on the SiON layer, and a step of forming a conductive film on the second SiO 2 layer to form a gate electrode. A method of manufacturing an insulated gate field effect semiconductor device according to claim 1, claim 2, or claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5311519A JP3051807B2 (en) | 1993-12-13 | 1993-12-13 | Insulated gate field effect semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5311519A JP3051807B2 (en) | 1993-12-13 | 1993-12-13 | Insulated gate field effect semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07161996A true JPH07161996A (en) | 1995-06-23 |
| JP3051807B2 JP3051807B2 (en) | 2000-06-12 |
Family
ID=18018221
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5311519A Expired - Fee Related JP3051807B2 (en) | 1993-12-13 | 1993-12-13 | Insulated gate field effect semiconductor device and method of manufacturing the same |
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| JP (1) | JP3051807B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429483B1 (en) | 1994-06-09 | 2002-08-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6601308B2 (en) | 2002-01-02 | 2003-08-05 | Bahram Khoshnood | Ambient light collecting bow sight |
| JP2007081414A (en) * | 2006-10-10 | 2007-03-29 | Seiko Epson Corp | Method of manufacturing semiconductor device |
| US8318554B2 (en) | 2005-04-28 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming gate insulating film for thin film transistors using plasma oxidation |
| US10541128B2 (en) | 2016-08-19 | 2020-01-21 | International Business Machines Corporation | Method for making VFET devices with ILD protection |
-
1993
- 1993-12-13 JP JP5311519A patent/JP3051807B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6429483B1 (en) | 1994-06-09 | 2002-08-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7547915B2 (en) | 1994-06-09 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having SiOxNy film |
| US8330165B2 (en) | 1994-06-09 | 2012-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6601308B2 (en) | 2002-01-02 | 2003-08-05 | Bahram Khoshnood | Ambient light collecting bow sight |
| USRE39686E1 (en) * | 2002-01-02 | 2007-06-12 | Bahram Khoshnood | Ambient light collecting bow sight |
| US8318554B2 (en) | 2005-04-28 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming gate insulating film for thin film transistors using plasma oxidation |
| KR101313124B1 (en) * | 2005-04-28 | 2013-09-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Manufacturing method of thin film transistor, display device using thin film transistor, and electronic device incorporating display device |
| JP2007081414A (en) * | 2006-10-10 | 2007-03-29 | Seiko Epson Corp | Method of manufacturing semiconductor device |
| US10541128B2 (en) | 2016-08-19 | 2020-01-21 | International Business Machines Corporation | Method for making VFET devices with ILD protection |
| US11164959B2 (en) | 2016-08-19 | 2021-11-02 | International Business Machines Corporation | VFET devices with ILD protection |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3051807B2 (en) | 2000-06-12 |
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